[PATCH v2 00/11] Check pixel clock when setting mode

[PATCH v2 00/11] Check pixel clock when setting mode

[Mika Kahola]

From EDID we can read and request higher pixel clock than
our HW can support. This set of patches add checks if
requested pixel clock is lower than the one supported by the HW.
The requested mode is discarded if we cannot support the requested
pixel clock. For example for Cherryview

'cvt 2560 1600 60' gives

# 2560x1600 59.99 Hz (CVT 4.10MA) hsync: 99.46 kHz; pclk: 348.50 MHz
Modeline "2560x1600_60.00"  348.50  2560 2760 3032 3504  1600 1603 1609 1658 -hsync +vsync

where pixel clock 348.50 MHz is higher than the supported 304 MHz.

The checks are implemented for DisplayPort, HDMI, LVDS, DVO, SDVO, DSI,
CRT, TV, and DP-MST.

V2:
- The maximum DOT clock frequency is added to debugfs i915_frequency_info.
- max dotclock cached in dev_priv structure
- moved computation of max dotclock to 'intel_display.c'

Mika Kahola (11):
  drm/i915: Store max dotclock
  drm/i915: DisplayPort pixel clock check
  drm/i915: HDMI pixel clock check
  drm/i915: LVDS pixel clock check
  drm/i915: SDVO pixel clock check
  drm/i915: DSI pixel clock check
  drm/i915: CRT pixel clock check
  drm/i915: TV pixel clock check
  drm/i915: DisplayPort-MST pixel clock check
  drm/i915: DVO pixel clock check
  drm/i915: Max DOT clock frequency to debugfs

 drivers/gpu/drm/i915/i915_debugfs.c  |  2 ++
 drivers/gpu/drm/i915/i915_drv.h      |  1 +
 drivers/gpu/drm/i915/intel_crt.c     |  7 ++++++-
 drivers/gpu/drm/i915/intel_display.c | 20 ++++++++++++++++++++
 drivers/gpu/drm/i915/intel_dp.c      |  6 +++++-
 drivers/gpu/drm/i915/intel_dp_mst.c  | 12 ++++++++++++
 drivers/gpu/drm/i915/intel_dsi.c     |  8 ++++++++
 drivers/gpu/drm/i915/intel_dvo.c     |  5 +++++
 drivers/gpu/drm/i915/intel_hdmi.c    |  9 ++++++++-
 drivers/gpu/drm/i915/intel_lvds.c    |  4 ++++
 drivers/gpu/drm/i915/intel_sdvo.c    |  6 ++++++
 drivers/gpu/drm/i915/intel_tv.c      |  6 ++++++
 12 files changed, 83 insertions(+), 3 deletions(-)

-- 
1.9.1

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[PATCH v2 01/11] drm/i915: Store max dotclock

[Mika Kahola]

Store max dotclock into dev_priv structure so we are able
to filter out the modes that are not supported by our
platforms.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h      |  1 +
 drivers/gpu/drm/i915/intel_display.c | 20 ++++++++++++++++++++
 2 files changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 04aa34a..1f69211b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1777,6 +1777,7 @@ struct drm_i915_private {
 	unsigned int fsb_freq, mem_freq, is_ddr3;
 	unsigned int skl_boot_cdclk;
 	unsigned int cdclk_freq, max_cdclk_freq;
+	unsigned int max_dotclk;
 	unsigned int hpll_freq;
 
 	/**
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 43b0f17..9031261 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5259,6 +5259,24 @@ static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
 			modeset_put_power_domains(dev_priv, put_domains[i]);
 }
 
+static int intel_update_max_dotclk(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int max_cdclk_freq = dev_priv->max_cdclk_freq;
+	int max_dotclk_freq;
+
+	if (IS_BROADWELL(dev) || IS_CHERRYVIEW(dev))
+		max_dotclk_freq = DIV_ROUND_UP(max_cdclk_freq * 100, 95);
+	else if (IS_VALLEYVIEW(dev))
+		max_dotclk_freq = DIV_ROUND_UP(max_cdclk_freq * 100, 90);
+	else if (IS_GEN2(dev) || IS_GEN3(dev))
+		max_dotclk_freq = DIV_ROUND_UP(2 * max_cdclk_freq * 100, 90);
+	else
+		max_dotclk_freq = max_cdclk_freq;
+
+	return max_dotclk_freq;
+}
+
 static void intel_update_max_cdclk(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -5298,6 +5316,8 @@ static void intel_update_max_cdclk(struct drm_device *dev)
 		dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
 	}
 
+	dev_priv->max_dotclk = intel_update_max_dotclk(dev);
+
 	DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
 			 dev_priv->max_cdclk_freq);
 }
-- 
1.9.1

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[PATCH v2 02/11] drm/i915: DisplayPort pixel clock check

[Mika Kahola]

It is possible the we request to have a mode that has
higher pixel clock than our HW can support. This patch
checks if requested pixel clock is lower than the one
supported by the HW. The requested mode is discarded
if we cannot support the requested pixel clock.

This patch applies to DisplayPort.

V2:
- removed computation for max DOT clock

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 44f8a32..89a150d 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -204,8 +204,12 @@ intel_dp_mode_valid(struct drm_connector *connector,
 	struct intel_dp *intel_dp = intel_attached_dp(connector);
 	struct intel_connector *intel_connector = to_intel_connector(connector);
 	struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+	struct intel_encoder *encoder = &intel_dig_port->base;
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	int target_clock = mode->clock;
 	int max_rate, mode_rate, max_lanes, max_link_clock;
+	int max_pixclk = dev_priv->max_dotclk;
 
 	if (is_edp(intel_dp) && fixed_mode) {
 		if (mode->hdisplay > fixed_mode->hdisplay)
@@ -223,7 +227,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
 	max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 	mode_rate = intel_dp_link_required(target_clock, 18);
 
-	if (mode_rate > max_rate)
+	if (mode_rate > max_rate || target_clock > max_pixclk)
 		return MODE_CLOCK_HIGH;
 
 	if (mode->clock < 10000)
-- 
1.9.1

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[PATCH v2 03/11] drm/i915: HDMI pixel clock check

[Mika Kahola]

It is possible the we request to have a mode that has
higher pixel clock than our HW can support. This patch
checks if requested pixel clock is lower than the one
supported by the HW. The requested mode is discarded
if we cannot support the requested pixel clock.

This patch applies to HDMI.

V2:
- removed computation for max dot clock

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_hdmi.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 70bad5b..b85efaa 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1191,15 +1191,22 @@ intel_hdmi_mode_valid(struct drm_connector *connector,
 {
 	struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
 	struct drm_device *dev = intel_hdmi_to_dev(hdmi);
+	struct drm_i915_private *dev_priv = to_i915(dev);
 	enum drm_mode_status status;
 	int clock;
+	int max_pixclk = dev_priv->max_dotclk;
 
 	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 		return MODE_NO_DBLESCAN;
 
 	clock = mode->clock;
-	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
+	if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
 		clock *= 2;
+		max_pixclk *= 2;
+	}
+
+	if (clock > max_pixclk)
+		return MODE_CLOCK_HIGH;
 
 	/* check if we can do 8bpc */
 	status = hdmi_port_clock_valid(hdmi, clock, true);
-- 
1.9.1

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[PATCH v2 04/11] drm/i915: LVDS pixel clock check

[Mika Kahola]

It is possible the we request to have a mode that has
higher pixel clock than our HW can support. This patch
checks if requested pixel clock is lower than the one
supported by the HW. The requested mode is discarded
if we cannot support the requested pixel clock.

This patch applies to LVDS.

V2:
- removed computation for max pixel clock

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_lvds.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index cb634f4..5648295 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -289,11 +289,15 @@ intel_lvds_mode_valid(struct drm_connector *connector,
 {
 	struct intel_connector *intel_connector = to_intel_connector(connector);
 	struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
+	struct drm_i915_private *dev_priv = to_i915(connector->dev);
+	int max_pixclk = dev_priv->max_dotclk;
 
 	if (mode->hdisplay > fixed_mode->hdisplay)
 		return MODE_PANEL;
 	if (mode->vdisplay > fixed_mode->vdisplay)
 		return MODE_PANEL;
+	if (mode->clock > max_pixclk)
+		return MODE_CLOCK_HIGH;
 
 	return MODE_OK;
 }
-- 
1.9.1

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[PATCH v2 05/11] drm/i915: SDVO pixel clock check

[Mika Kahola]

It is possible the we request to have a mode that has
higher pixel clock than our HW can support. This patch
checks if requested pixel clock is lower than the one
supported by the HW. The requested mode is discarded
if we cannot support the requested pixel clock.

This patch applies to SDVO.

V2:
- removed computation for max pixel clock

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_sdvo.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 2c435a7..753b670 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1560,6 +1560,9 @@ intel_sdvo_mode_valid(struct drm_connector *connector,
 		      struct drm_display_mode *mode)
 {
 	struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
+	struct drm_device *dev = intel_sdvo->base.base.dev;
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	int max_pixclk = dev_priv->max_dotclk;
 
 	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 		return MODE_NO_DBLESCAN;
@@ -1570,6 +1573,9 @@ intel_sdvo_mode_valid(struct drm_connector *connector,
 	if (intel_sdvo->pixel_clock_max < mode->clock)
 		return MODE_CLOCK_HIGH;
 
+	if (mode->clock > max_pixclk)
+		return MODE_CLOCK_HIGH;
+
 	if (intel_sdvo->is_lvds) {
 		if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
 			return MODE_PANEL;
-- 
1.9.1

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[PATCH v2 06/11] drm/i915: DSI pixel clock check

[Mika Kahola]

It is possible the we request to have a mode that has
higher pixel clock than our HW can support. This patch
checks if requested pixel clock is lower than the one
supported by the HW. The requested mode is discarded
if we cannot support the requested pixel clock.

This patch applies to DSI.

V2:
- removed computation for max pixel clock

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 18dd7d7..2882978 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -654,6 +654,11 @@ intel_dsi_mode_valid(struct drm_connector *connector,
 {
 	struct intel_connector *intel_connector = to_intel_connector(connector);
 	struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
+	struct intel_encoder *intel_encoder = intel_connector->encoder;
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&intel_encoder->base);
+	struct drm_device *dev = intel_dsi->base.base.dev;
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	int max_pixclk = dev_priv->max_dotclk;
 
 	DRM_DEBUG_KMS("\n");
 
@@ -669,6 +674,9 @@ intel_dsi_mode_valid(struct drm_connector *connector,
 			return MODE_PANEL;
 	}
 
+	if (mode->clock > max_pixclk)
+		return MODE_CLOCK_HIGH;
+
 	return MODE_OK;
 }
 
-- 
1.9.1

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[PATCH v2 07/11] drm/i915: CRT pixel clock check

[Mika Kahola]

It is possible the we request to have a mode that has
higher pixel clock than our HW can support. This patch
checks if requested pixel clock is lower than the one
supported by the HW. The requested mode is discarded
if we cannot support the requested pixel clock.

This patch applies to CRT.

V2:
- removed computation for max pixel clock

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_crt.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 5d78c1f..6e29bce 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -290,8 +290,10 @@ intel_crt_mode_valid(struct drm_connector *connector,
 		     struct drm_display_mode *mode)
 {
 	struct drm_device *dev = connector->dev;
-
+	struct drm_i915_private *dev_priv = to_i915(dev);
 	int max_clock = 0;
+	int max_pixclk = dev_priv->max_dotclk;
+
 	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 		return MODE_NO_DBLESCAN;
 
@@ -305,6 +307,9 @@ intel_crt_mode_valid(struct drm_connector *connector,
 	if (mode->clock > max_clock)
 		return MODE_CLOCK_HIGH;
 
+	if (mode->clock > max_pixclk)
+		return MODE_CLOCK_HIGH;
+
 	/* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
 	if (HAS_PCH_LPT(dev) &&
 	    (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2))
-- 
1.9.1

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[PATCH v2 08/11] drm/i915: TV pixel clock check

[Mika Kahola]

It is possible the we request to have a mode that has
higher pixel clock than our HW can support. This patch
checks if requested pixel clock is lower than the one
supported by the HW. The requested mode is discarded
if we cannot support the requested pixel clock.

This patch applies to TV.

V2:
- removed computation for max pixel clock

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_tv.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index 8b9d325..0990f22 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -896,7 +896,13 @@ intel_tv_mode_valid(struct drm_connector *connector,
 		    struct drm_display_mode *mode)
 {
 	struct intel_tv *intel_tv = intel_attached_tv(connector);
+	struct drm_device *dev = intel_tv->base.base.dev;
+	struct drm_i915_private *dev_priv = to_i915(dev);
 	const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv);
+	int max_pixclk = dev_priv->max_dotclk;
+
+	if (mode->clock > max_pixclk)
+		return MODE_CLOCK_HIGH;
 
 	/* Ensure TV refresh is close to desired refresh */
 	if (tv_mode && abs(tv_mode->refresh - drm_mode_vrefresh(mode) * 1000)
-- 
1.9.1

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[PATCH v2 09/11] drm/i915: DisplayPort-MST pixel clock check

[Mika Kahola]

It is possible the we request to have a mode that has
higher pixel clock than our HW can support. This patch
checks if requested pixel clock is lower than the one
supported by the HW. The requested mode is discarded
if we cannot support the requested pixel clock.

This patch applies to DisplayPort MST.

V2:
- removed computation for max pixel clock

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_dp_mst.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
index 585f0a4..5c65f5c 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -347,6 +347,15 @@ static enum drm_mode_status
 intel_dp_mst_mode_valid(struct drm_connector *connector,
 			struct drm_display_mode *mode)
 {
+	struct intel_connector *intel_connector = to_intel_connector(connector);
+	struct intel_dp *intel_dp = intel_connector->mst_port;
+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+	struct intel_encoder *encoder = &intel_dig_port->base;
+	struct drm_device *dev = encoder->base.dev;
+	struct drm_i915_private *dev_priv = to_i915(dev);
+
+	int max_pixclk = dev_priv->max_dotclk;
+
 	/* TODO - validate mode against available PBN for link */
 	if (mode->clock < 10000)
 		return MODE_CLOCK_LOW;
@@ -354,6 +363,9 @@ intel_dp_mst_mode_valid(struct drm_connector *connector,
 	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 		return MODE_H_ILLEGAL;
 
+	if (mode->clock > max_pixclk)
+		return MODE_CLOCK_HIGH;
+
 	return MODE_OK;
 }
 
-- 
1.9.1

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[PATCH v2 10/11] drm/i915: DVO pixel clock check

[Mika Kahola]

It is possible the we request to have a mode that has
higher pixel clock than our HW can support. This patch
checks if requested pixel clock is lower than the one
supported by the HW. The requested mode is discarded
if we cannot support the requested pixel clock.

This patch applies to DVO.

V2:
- removed computation for max pixel clock

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_dvo.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c
index fd5e522..7afcfa4 100644
--- a/drivers/gpu/drm/i915/intel_dvo.c
+++ b/drivers/gpu/drm/i915/intel_dvo.c
@@ -247,6 +247,8 @@ intel_dvo_mode_valid(struct drm_connector *connector,
 		     struct drm_display_mode *mode)
 {
 	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
+	struct drm_i915_private *dev_priv = intel_dvo->dev.dev_priv;
+	int max_pixclk = dev_priv->max_dotclk;
 
 	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 		return MODE_NO_DBLESCAN;
@@ -260,6 +262,9 @@ intel_dvo_mode_valid(struct drm_connector *connector,
 			return MODE_PANEL;
 	}
 
+	if (mode->clock > max_pixclk)
+		return MODE_CLOCK_HIGH;
+
 	return intel_dvo->dev.dev_ops->mode_valid(&intel_dvo->dev, mode);
 }
 
-- 
1.9.1

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[PATCH v2 11/11] drm/i915: Max DOT clock frequency to debugfs

[Mika Kahola]

Information on maximum supported DOT clock frequency to
i915_frequency_info.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 23a69307..4ba02b5 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1314,6 +1314,8 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
 		seq_puts(m, "no P-state info available\n");
 	}
 
+	seq_printf(m, "Max pixel clock frequency: %dkHz\n", dev_priv->max_dotclk);
+
 out:
 	intel_runtime_pm_put(dev_priv);
 	return ret;
-- 
1.9.1

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Re: [PATCH v2 06/11] drm/i915: DSI pixel clock check

[Chris Wilson]

On Thu, Jul 30, 2015 at 09:49:33AM +0300, Mika Kahola wrote:
> It is possible the we request to have a mode that has
> higher pixel clock than our HW can support. This patch
> checks if requested pixel clock is lower than the one
> supported by the HW. The requested mode is discarded
> if we cannot support the requested pixel clock.
> 
> This patch applies to DSI.
> 
> V2:
> - removed computation for max pixel clock
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dsi.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 18dd7d7..2882978 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -654,6 +654,11 @@ intel_dsi_mode_valid(struct drm_connector *connector,
>  {
>  	struct intel_connector *intel_connector = to_intel_connector(connector);
>  	struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
> +	struct intel_encoder *intel_encoder = intel_connector->encoder;
> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&intel_encoder->base);
> +	struct drm_device *dev = intel_dsi->base.base.dev;
> +	struct drm_i915_private *dev_priv = to_i915(dev);
> +	int max_pixclk = dev_priv->max_dotclk;

You only wanted i915, why all the extra steps?
	int max_pixclk = to_i915(connector->dev)->max_dotclk;
-Chris

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Re: [PATCH v2 03/11] drm/i915: HDMI pixel clock check

[Chris Wilson]

On Thu, Jul 30, 2015 at 09:49:30AM +0300, Mika Kahola wrote:
> It is possible the we request to have a mode that has
> higher pixel clock than our HW can support. This patch
> checks if requested pixel clock is lower than the one
> supported by the HW. The requested mode is discarded
> if we cannot support the requested pixel clock.
> 
> This patch applies to HDMI.
> 
> V2:
> - removed computation for max dot clock
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_hdmi.c | 9 ++++++++-
>  1 file changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index 70bad5b..b85efaa 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1191,15 +1191,22 @@ intel_hdmi_mode_valid(struct drm_connector *connector,
>  {
>  	struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
>  	struct drm_device *dev = intel_hdmi_to_dev(hdmi);
> +	struct drm_i915_private *dev_priv = to_i915(dev);
>  	enum drm_mode_status status;
>  	int clock;
> +	int max_pixclk = dev_priv->max_dotclk;
>  
>  	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
>  		return MODE_NO_DBLESCAN;
>  
>  	clock = mode->clock;
> -	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
> +	if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
>  		clock *= 2;
> +		max_pixclk *= 2;
> +	}
> +
> +	if (clock > max_pixclk)
> +		return MODE_CLOCK_HIGH;

Or do the test before the DBLCLK?
-Chris

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Re: [PATCH v2 01/11] drm/i915: Store max dotclock

[Chris Wilson]

On Thu, Jul 30, 2015 at 09:49:28AM +0300, Mika Kahola wrote:
> Store max dotclock into dev_priv structure so we are able
> to filter out the modes that are not supported by our
> platforms.
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h      |  1 +
>  drivers/gpu/drm/i915/intel_display.c | 20 ++++++++++++++++++++
>  2 files changed, 21 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 04aa34a..1f69211b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1777,6 +1777,7 @@ struct drm_i915_private {
>  	unsigned int fsb_freq, mem_freq, is_ddr3;
>  	unsigned int skl_boot_cdclk;
>  	unsigned int cdclk_freq, max_cdclk_freq;
> +	unsigned int max_dotclk;
>  	unsigned int hpll_freq;
>  
>  	/**
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 43b0f17..9031261 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5259,6 +5259,24 @@ static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
>  			modeset_put_power_domains(dev_priv, put_domains[i]);
>  }
>  
> +static int intel_update_max_dotclk(struct drm_device *dev)

You don't update max dotclck, you are computing it. The caller is the
one storing it dev_priv->max_dotclk (and so is the one actually doing
the update).

> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;

So why did you pass in dev if we never use it?

> +	int max_cdclk_freq = dev_priv->max_cdclk_freq;
> +	int max_dotclk_freq;
> +
> +	if (IS_BROADWELL(dev) || IS_CHERRYVIEW(dev))

We already have dev_priv, so please stop doing dev->dev_priv over and
over again.

> +		max_dotclk_freq = DIV_ROUND_UP(max_cdclk_freq * 100, 95);
> +	else if (IS_VALLEYVIEW(dev))
> +		max_dotclk_freq = DIV_ROUND_UP(max_cdclk_freq * 100, 90);
> +	else if (IS_GEN2(dev) || IS_GEN3(dev))

If you reverse this pair and do

else if (INTEL_INFO(dev)->gen > 3)
	max_dotclk_freq = max_cdclk_freq;
else
	max_dotclk_freq = DIV_ROUND_UP(2 * max_cdclk_freq * 100, 90);

Then the chain is mostly ordered in most-recent to oldest, always
helpful for the next person.

Is this correct for gen9+?
-Chris

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Re: [PATCH v2 01/11] drm/i915: Store max dotclock

[Mika Kahola]

On Thu, 2015-07-30 at 08:00 +0100, Chris Wilson wrote:
> On Thu, Jul 30, 2015 at 09:49:28AM +0300, Mika Kahola wrote:
> > Store max dotclock into dev_priv structure so we are able
> > to filter out the modes that are not supported by our
> > platforms.
> > 
> > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_drv.h      |  1 +
> >  drivers/gpu/drm/i915/intel_display.c | 20 ++++++++++++++++++++
> >  2 files changed, 21 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 04aa34a..1f69211b 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1777,6 +1777,7 @@ struct drm_i915_private {
> >  	unsigned int fsb_freq, mem_freq, is_ddr3;
> >  	unsigned int skl_boot_cdclk;
> >  	unsigned int cdclk_freq, max_cdclk_freq;
> > +	unsigned int max_dotclk;
> >  	unsigned int hpll_freq;
> >  
> >  	/**
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 43b0f17..9031261 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -5259,6 +5259,24 @@ static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
> >  			modeset_put_power_domains(dev_priv, put_domains[i]);
> >  }
> >  
> > +static int intel_update_max_dotclk(struct drm_device *dev)
> 
> You don't update max dotclck, you are computing it. The caller is the
> one storing it dev_priv->max_dotclk (and so is the one actually doing
> the update).
> 
True. I'll fix the poor naming of that routine.

> > +{
> > +	struct drm_i915_private *dev_priv = dev->dev_private;
> 
> So why did you pass in dev if we never use it?
> 
> > +	int max_cdclk_freq = dev_priv->max_cdclk_freq;
> > +	int max_dotclk_freq;
> > +
> > +	if (IS_BROADWELL(dev) || IS_CHERRYVIEW(dev))
> 
> We already have dev_priv, so please stop doing dev->dev_priv over and
> over again.
> 
Yeah, that's pretty much unnecessary, so removing this one for the next
series of patches.

> > +		max_dotclk_freq = DIV_ROUND_UP(max_cdclk_freq * 100, 95);
> > +	else if (IS_VALLEYVIEW(dev))
> > +		max_dotclk_freq = DIV_ROUND_UP(max_cdclk_freq * 100, 90);
> > +	else if (IS_GEN2(dev) || IS_GEN3(dev))
> 
> If you reverse this pair and do
> 
> else if (INTEL_INFO(dev)->gen > 3)
> 	max_dotclk_freq = max_cdclk_freq;
> else
> 	max_dotclk_freq = DIV_ROUND_UP(2 * max_cdclk_freq * 100, 90);
> 
> Then the chain is mostly ordered in most-recent to oldest, always
> helpful for the next person.
> 
I'll apply this change as well on the next patch series. 

> Is this correct for gen9+?
This is something I need to double check. My current understanding is
that we should be able to support dot clock up to cd clock frequency
from HSW+ onwards. Actually, I did missed the Ville's comment to limit
dot clock to 90% for older platforms so I need to add this to the next
series as well.

Thanks again for valuable comments.

Cheers,
Mika 

> -Chris
> 


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Re: [PATCH v2 03/11] drm/i915: HDMI pixel clock check

[Mika Kahola]

On Thu, 2015-07-30 at 07:54 +0100, Chris Wilson wrote:
> On Thu, Jul 30, 2015 at 09:49:30AM +0300, Mika Kahola wrote:
> > It is possible the we request to have a mode that has
> > higher pixel clock than our HW can support. This patch
> > checks if requested pixel clock is lower than the one
> > supported by the HW. The requested mode is discarded
> > if we cannot support the requested pixel clock.
> > 
> > This patch applies to HDMI.
> > 
> > V2:
> > - removed computation for max dot clock
> > 
> > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_hdmi.c | 9 ++++++++-
> >  1 file changed, 8 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> > index 70bad5b..b85efaa 100644
> > --- a/drivers/gpu/drm/i915/intel_hdmi.c
> > +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> > @@ -1191,15 +1191,22 @@ intel_hdmi_mode_valid(struct drm_connector *connector,
> >  {
> >  	struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
> >  	struct drm_device *dev = intel_hdmi_to_dev(hdmi);
> > +	struct drm_i915_private *dev_priv = to_i915(dev);
> >  	enum drm_mode_status status;
> >  	int clock;
> > +	int max_pixclk = dev_priv->max_dotclk;
> >  
> >  	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
> >  		return MODE_NO_DBLESCAN;
> >  
> >  	clock = mode->clock;
> > -	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
> > +	if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
> >  		clock *= 2;
> > +		max_pixclk *= 2;
> > +	}
> > +
> > +	if (clock > max_pixclk)
> > +		return MODE_CLOCK_HIGH;
> 
> Or do the test before the DBLCLK?
Yes, I could move the test before DBLCLK.

-Mika-

> -Chris
> 


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Re: [PATCH v2 06/11] drm/i915: DSI pixel clock check

[Mika Kahola]

On Thu, 2015-07-30 at 07:52 +0100, Chris Wilson wrote:
> On Thu, Jul 30, 2015 at 09:49:33AM +0300, Mika Kahola wrote:
> > It is possible the we request to have a mode that has
> > higher pixel clock than our HW can support. This patch
> > checks if requested pixel clock is lower than the one
> > supported by the HW. The requested mode is discarded
> > if we cannot support the requested pixel clock.
> > 
> > This patch applies to DSI.
> > 
> > V2:
> > - removed computation for max pixel clock
> > 
> > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_dsi.c | 8 ++++++++
> >  1 file changed, 8 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> > index 18dd7d7..2882978 100644
> > --- a/drivers/gpu/drm/i915/intel_dsi.c
> > +++ b/drivers/gpu/drm/i915/intel_dsi.c
> > @@ -654,6 +654,11 @@ intel_dsi_mode_valid(struct drm_connector *connector,
> >  {
> >  	struct intel_connector *intel_connector = to_intel_connector(connector);
> >  	struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
> > +	struct intel_encoder *intel_encoder = intel_connector->encoder;
> > +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&intel_encoder->base);
> > +	struct drm_device *dev = intel_dsi->base.base.dev;
> > +	struct drm_i915_private *dev_priv = to_i915(dev);
> > +	int max_pixclk = dev_priv->max_dotclk;
> 
> You only wanted i915, why all the extra steps?
> 	int max_pixclk = to_i915(connector->dev)->max_dotclk;
There's really no need for all these steps. All I need to extract is the
max_dotclk and I could do that shorter. This is also applicable for
other patches in the series.

-Mika-

> -Chris
> 


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