* [PATCH] drm/i915/Gen9+: optional IPC enablement
@ 2016-04-02 0:44 Dongwon Kim
2016-04-02 1:16 ` kbuild test robot
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: Dongwon Kim @ 2016-04-02 0:44 UTC (permalink / raw)
To: intel-gfx, imre.deak, matthew.d.roper; +Cc: Dongwon Kim
With IPC(Isochronous Priority Control) enabled,
display sends requests based on the priority of each
request. To enable it, a i915 param, i915.enable_ipc
should be set to 1.
Signed-off-by: Dongwon Kim <dongwon.kim@intel.com>
---
drivers/gpu/drm/i915/i915_params.c | 5 +++++
drivers/gpu/drm/i915/i915_params.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 5 +++++
4 files changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index 1779f02..611a83b 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -58,6 +58,7 @@ struct i915_params i915 __read_mostly = {
.guc_log_level = -1,
.enable_dp_mst = true,
.inject_load_failure = 0,
+ .enable_ipc = 0,
};
module_param_named(modeset, i915.modeset, int, 0400);
@@ -210,3 +211,7 @@ MODULE_PARM_DESC(enable_dp_mst,
module_param_named_unsafe(inject_load_failure, i915.inject_load_failure, uint, 0400);
MODULE_PARM_DESC(inject_load_failure,
"Force an error after a number of failure check points (0:disabled (default), N:force failure at the Nth failure check point)");
+
+module_param_named_unsafe(enable_ipc, i915.enable_ipc, int, 0400);
+MODULE_PARM_DESC(enable_ipc,
+ "Enable Isochronous Priority Control (1=enabled, 0=disabled [default]");
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index 02bc278..3b3fa1b 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -61,6 +61,7 @@ struct i915_params {
bool verbose_state_checks;
bool nuclear_pageflip;
bool enable_dp_mst;
+ bool enable_ipc;
};
extern struct i915_params i915 __read_mostly;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 12f5103..0b638c5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5995,6 +5995,7 @@ enum skl_disp_power_wells {
#define DISP_FBC_WM_DIS (1<<15)
#define DISP_ARB_CTL2 _MMIO(0x45004)
#define DISP_DATA_PARTITION_5_6 (1<<6)
+#define DISP_ENABLE_IPC (1<<3)
#define DBUF_CTL _MMIO(0x45008)
#define DBUF_POWER_REQUEST (1<<31)
#define DBUF_POWER_STATE (1<<30)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9bc9c25..9c696c0 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3682,6 +3682,11 @@ static void skl_update_wm(struct drm_crtc *crtc)
skl_write_wm_values(dev_priv, results);
skl_flush_wm_values(dev_priv, results);
+ /* optional IPC enablement */
+ if (i915.enable_ipc)
+ I915_WRITE(DISP_ARB_CTL2,
+ I915_READ(DISP_ARB_CTL2) | DISP_ENABLE_IPC);
+
/* store the new configuration */
dev_priv->wm.skl_hw = *results;
}
--
1.9.1
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^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH] drm/i915/Gen9+: optional IPC enablement
2016-04-02 0:44 [PATCH] drm/i915/Gen9+: optional IPC enablement Dongwon Kim
@ 2016-04-02 1:16 ` kbuild test robot
2016-04-02 7:58 ` ✗ Fi.CI.BAT: failure for " Patchwork
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: kbuild test robot @ 2016-04-02 1:16 UTC (permalink / raw)
Cc: intel-gfx, kbuild-all, Dongwon Kim
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Hi Dongwon,
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on next-20160401]
[cannot apply to v4.6-rc1]
[if your patch is applied to the wrong git tree, please drop us a note to help improving the system]
url: https://github.com/0day-ci/linux/commits/Dongwon-Kim/drm-i915-Gen9-optional-IPC-enablement/20160402-084819
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-s1-201613 (attached as .config)
reproduce:
# save the attached .config to linux build tree
make ARCH=i386
All warnings (new ones prefixed by >>):
In file included from include/linux/module.h:18:0,
from include/drm/drm_vma_manager.h:29,
from include/drm/drmP.h:75,
from drivers/gpu/drm/i915/i915_drv.h:36,
from drivers/gpu/drm/i915/i915_params.c:26:
drivers/gpu/drm/i915/i915_params.c: In function '__check_enable_ipc':
include/linux/moduleparam.h:344:67: warning: return from incompatible pointer type [-Wincompatible-pointer-types]
static inline type __always_unused *__check_##name(void) { return(p); }
^
include/linux/moduleparam.h:364:34: note: in expansion of macro '__param_check'
#define param_check_int(name, p) __param_check(name, p, int)
^
include/linux/moduleparam.h:154:2: note: in expansion of macro 'param_check_int'
param_check_##type(name, &(value)); \
^
>> drivers/gpu/drm/i915/i915_params.c:215:1: note: in expansion of macro 'module_param_named_unsafe'
module_param_named_unsafe(enable_ipc, i915.enable_ipc, int, 0400);
^
vim +/module_param_named_unsafe +215 drivers/gpu/drm/i915/i915_params.c
199 "2=default swing(400mV))");
200
201 module_param_named_unsafe(enable_guc_submission, i915.enable_guc_submission, bool, 0400);
202 MODULE_PARM_DESC(enable_guc_submission, "Enable GuC submission (default:false)");
203
204 module_param_named(guc_log_level, i915.guc_log_level, int, 0400);
205 MODULE_PARM_DESC(guc_log_level,
206 "GuC firmware logging level (-1:disabled (default), 0-3:enabled)");
207
208 module_param_named_unsafe(enable_dp_mst, i915.enable_dp_mst, bool, 0600);
209 MODULE_PARM_DESC(enable_dp_mst,
210 "Enable multi-stream transport (MST) for new DisplayPort sinks. (default: true)");
211 module_param_named_unsafe(inject_load_failure, i915.inject_load_failure, uint, 0400);
212 MODULE_PARM_DESC(inject_load_failure,
213 "Force an error after a number of failure check points (0:disabled (default), N:force failure at the Nth failure check point)");
214
> 215 module_param_named_unsafe(enable_ipc, i915.enable_ipc, int, 0400);
216 MODULE_PARM_DESC(enable_ipc,
217 "Enable Isochronous Priority Control (1=enabled, 0=disabled [default]");
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
[-- Attachment #2: .config.gz --]
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[-- Attachment #3: Type: text/plain, Size: 160 bytes --]
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread* ✗ Fi.CI.BAT: failure for drm/i915/Gen9+: optional IPC enablement
2016-04-02 0:44 [PATCH] drm/i915/Gen9+: optional IPC enablement Dongwon Kim
2016-04-02 1:16 ` kbuild test robot
@ 2016-04-02 7:58 ` Patchwork
2016-04-04 17:57 ` [PATCH v2] " Dongwon Kim
2016-04-05 7:26 ` ✓ Fi.CI.BAT: success for drm/i915/Gen9+: optional IPC enablement (rev2) Patchwork
3 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2016-04-02 7:58 UTC (permalink / raw)
To: Dongwon Kim; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/Gen9+: optional IPC enablement
URL : https://patchwork.freedesktop.org/series/5203/
State : failure
== Summary ==
Series 5203v1 drm/i915/Gen9+: optional IPC enablement
http://patchwork.freedesktop.org/api/1.0/series/5203/revisions/1/mbox/
Test gem_exec_suspend:
Subgroup basic-s3:
incomplete -> PASS (hsw-gt2)
Test kms_flip:
Subgroup basic-flip-vs-wf_vblank:
fail -> PASS (snb-x220t)
pass -> FAIL (hsw-gt2)
fail -> PASS (ilk-hp8440p) UNSTABLE
bdw-nuci7 total:196 pass:184 dwarn:0 dfail:0 fail:0 skip:12
bdw-ultra total:196 pass:175 dwarn:0 dfail:0 fail:0 skip:21
bsw-nuc-2 total:196 pass:159 dwarn:0 dfail:0 fail:0 skip:37
byt-nuc total:196 pass:161 dwarn:0 dfail:0 fail:0 skip:35
hsw-brixbox total:196 pass:174 dwarn:0 dfail:0 fail:0 skip:22
hsw-gt2 total:196 pass:178 dwarn:0 dfail:0 fail:1 skip:17
ilk-hp8440p total:196 pass:132 dwarn:0 dfail:0 fail:0 skip:64
ivb-t430s total:196 pass:171 dwarn:0 dfail:0 fail:0 skip:25
snb-dellxps total:196 pass:162 dwarn:0 dfail:0 fail:0 skip:34
snb-x220t total:196 pass:162 dwarn:0 dfail:0 fail:1 skip:33
Results at /archive/results/CI_IGT_test/Patchwork_1781/
ce3f49e2a53a54308ed171613c2567f04fab8228 drm-intel-nightly: 2016y-04m-01d-20h-30m-13s UTC integration manifest
0353316f2b0e289deacb20fae0643b827b9123e4 drm/i915/Gen9+: optional IPC enablement
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread* [PATCH v2] drm/i915/Gen9+: optional IPC enablement
2016-04-02 0:44 [PATCH] drm/i915/Gen9+: optional IPC enablement Dongwon Kim
2016-04-02 1:16 ` kbuild test robot
2016-04-02 7:58 ` ✗ Fi.CI.BAT: failure for " Patchwork
@ 2016-04-04 17:57 ` Dongwon Kim
2016-04-05 7:26 ` ✓ Fi.CI.BAT: success for drm/i915/Gen9+: optional IPC enablement (rev2) Patchwork
3 siblings, 0 replies; 5+ messages in thread
From: Dongwon Kim @ 2016-04-04 17:57 UTC (permalink / raw)
To: intel-gfx, imre.deak, matthew.d.roper; +Cc: Dongwon Kim
With IPC(Isochronous Priority Control) enabled,
display sends requests based on the priority of each
request. To enable it, a i915 param, i915.enable_ipc
should be set to 1.
v2: corrected matched type of enable_ipc in
module_param_named_unsafe macro
Signed-off-by: Dongwon Kim <dongwon.kim@intel.com>
---
drivers/gpu/drm/i915/i915_params.c | 5 +++++
drivers/gpu/drm/i915/i915_params.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 5 +++++
4 files changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index 1779f02..4d5ac80 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -58,6 +58,7 @@ struct i915_params i915 __read_mostly = {
.guc_log_level = -1,
.enable_dp_mst = true,
.inject_load_failure = 0,
+ .enable_ipc = 0,
};
module_param_named(modeset, i915.modeset, int, 0400);
@@ -210,3 +211,7 @@ MODULE_PARM_DESC(enable_dp_mst,
module_param_named_unsafe(inject_load_failure, i915.inject_load_failure, uint, 0400);
MODULE_PARM_DESC(inject_load_failure,
"Force an error after a number of failure check points (0:disabled (default), N:force failure at the Nth failure check point)");
+
+module_param_named_unsafe(enable_ipc, i915.enable_ipc, bool, 0400);
+MODULE_PARM_DESC(enable_ipc,
+ "Enable Isochronous Priority Control (1=enabled, 0=disabled [default]");
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index 02bc278..3b3fa1b 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -61,6 +61,7 @@ struct i915_params {
bool verbose_state_checks;
bool nuclear_pageflip;
bool enable_dp_mst;
+ bool enable_ipc;
};
extern struct i915_params i915 __read_mostly;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 12f5103..0b638c5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5995,6 +5995,7 @@ enum skl_disp_power_wells {
#define DISP_FBC_WM_DIS (1<<15)
#define DISP_ARB_CTL2 _MMIO(0x45004)
#define DISP_DATA_PARTITION_5_6 (1<<6)
+#define DISP_ENABLE_IPC (1<<3)
#define DBUF_CTL _MMIO(0x45008)
#define DBUF_POWER_REQUEST (1<<31)
#define DBUF_POWER_STATE (1<<30)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9bc9c25..9c696c0 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3682,6 +3682,11 @@ static void skl_update_wm(struct drm_crtc *crtc)
skl_write_wm_values(dev_priv, results);
skl_flush_wm_values(dev_priv, results);
+ /* optional IPC enablement */
+ if (i915.enable_ipc)
+ I915_WRITE(DISP_ARB_CTL2,
+ I915_READ(DISP_ARB_CTL2) | DISP_ENABLE_IPC);
+
/* store the new configuration */
dev_priv->wm.skl_hw = *results;
}
--
1.9.1
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 5+ messages in thread* ✓ Fi.CI.BAT: success for drm/i915/Gen9+: optional IPC enablement (rev2)
2016-04-02 0:44 [PATCH] drm/i915/Gen9+: optional IPC enablement Dongwon Kim
` (2 preceding siblings ...)
2016-04-04 17:57 ` [PATCH v2] " Dongwon Kim
@ 2016-04-05 7:26 ` Patchwork
3 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2016-04-05 7:26 UTC (permalink / raw)
To: Dongwon Kim; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/Gen9+: optional IPC enablement (rev2)
URL : https://patchwork.freedesktop.org/series/5203/
State : success
== Summary ==
Series 5203v2 drm/i915/Gen9+: optional IPC enablement
http://patchwork.freedesktop.org/api/1.0/series/5203/revisions/2/mbox/
Test kms_force_connector_basic:
Subgroup prune-stale-modes:
skip -> PASS (ilk-hp8440p)
bdw-nuci7 total:196 pass:184 dwarn:0 dfail:0 fail:0 skip:12
bdw-ultra total:196 pass:175 dwarn:0 dfail:0 fail:0 skip:21
bsw-nuc-2 total:196 pass:159 dwarn:0 dfail:0 fail:0 skip:37
byt-nuc total:196 pass:161 dwarn:0 dfail:0 fail:0 skip:35
hsw-brixbox total:196 pass:174 dwarn:0 dfail:0 fail:0 skip:22
hsw-gt2 total:16 pass:14 dwarn:0 dfail:0 fail:0 skip:1
ilk-hp8440p total:196 pass:132 dwarn:0 dfail:0 fail:0 skip:64
ivb-t430s total:196 pass:171 dwarn:0 dfail:0 fail:0 skip:25
skl-i7k-2 total:196 pass:173 dwarn:0 dfail:0 fail:0 skip:23
snb-dellxps total:196 pass:162 dwarn:0 dfail:0 fail:0 skip:34
snb-x220t total:196 pass:162 dwarn:0 dfail:0 fail:1 skip:33
Results at /archive/results/CI_IGT_test/Patchwork_1795/
aedfaaef290af9c8df7d9f4adf22cbe21704d091 drm-intel-nightly: 2016y-04m-04d-13h-09m-54s UTC integration manifest
d20c9777a31b1e396102766eb749541314e2ad57 drm/i915/Gen9+: optional IPC enablement
_______________________________________________
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^ permalink raw reply [flat|nested] 5+ messages in thread
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2016-04-02 0:44 [PATCH] drm/i915/Gen9+: optional IPC enablement Dongwon Kim
2016-04-02 1:16 ` kbuild test robot
2016-04-02 7:58 ` ✗ Fi.CI.BAT: failure for " Patchwork
2016-04-04 17:57 ` [PATCH v2] " Dongwon Kim
2016-04-05 7:26 ` ✓ Fi.CI.BAT: success for drm/i915/Gen9+: optional IPC enablement (rev2) Patchwork
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