[PATCH i-g-t 1/2] lib/i915_pciids.h: Update to latest version wich includes GLK ids

[PATCH i-g-t 1/2] lib/i915_pciids.h: Update to latest version wich includes GLK ids

[Ander Conselvan de Oliveira]

Copy the include/drm/i915_pciids.h file from following kernel commit,
which includes Geminilake PCI IDs.

commit 8363e3c3947d0e22955f94a6a87e4f17ce5087b4
Author: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Date:   Thu Nov 10 17:23:08 2016 +0200

    drm/i915/glk: Add Geminilake PCI IDs

Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
 lib/i915_pciids.h         | 42 ++++++++++++++++++------------------------
 lib/intel_device_info.c   | 27 +++------------------------
 overlay/igfx.c            |  9 +++------
 tests/gen7_forcewake_mt.c |  3 +--
 4 files changed, 25 insertions(+), 56 deletions(-)

diff --git a/lib/i915_pciids.h b/lib/i915_pciids.h
index 33466bf..540be9f 100644
--- a/lib/i915_pciids.h
+++ b/lib/i915_pciids.h
@@ -134,7 +134,7 @@
 #define INTEL_IVB_Q_IDS(info) \
 	INTEL_QUANTA_VGA_DEVICE(info) /* Quanta transcode */
 
-#define INTEL_HSW_D_IDS(info) \
+#define INTEL_HSW_IDS(info) \
 	INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \
 	INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \
 	INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \
@@ -179,9 +179,7 @@
 	INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \
 	INTEL_VGA_DEVICE(0x0D0E, info), /* CRW GT1 reserved */ \
 	INTEL_VGA_DEVICE(0x0D1E, info), /* CRW GT2 reserved */ \
-	INTEL_VGA_DEVICE(0x0D2E, info)  /* CRW GT3 reserved */ \
-
-#define INTEL_HSW_M_IDS(info) \
+	INTEL_VGA_DEVICE(0x0D2E, info),  /* CRW GT3 reserved */ \
 	INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \
 	INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \
 	INTEL_VGA_DEVICE(0x0426, info), /* GT2 mobile */ \
@@ -198,17 +196,15 @@
 	INTEL_VGA_DEVICE(0x0D16, info), /* CRW GT2 mobile */ \
 	INTEL_VGA_DEVICE(0x0D26, info)  /* CRW GT3 mobile */
 
-#define INTEL_VLV_M_IDS(info) \
+#define INTEL_VLV_IDS(info) \
 	INTEL_VGA_DEVICE(0x0f30, info), \
 	INTEL_VGA_DEVICE(0x0f31, info), \
 	INTEL_VGA_DEVICE(0x0f32, info), \
 	INTEL_VGA_DEVICE(0x0f33, info), \
-	INTEL_VGA_DEVICE(0x0157, info)
-
-#define INTEL_VLV_D_IDS(info) \
+	INTEL_VGA_DEVICE(0x0157, info), \
 	INTEL_VGA_DEVICE(0x0155, info)
 
-#define INTEL_BDW_GT12M_IDS(info)  \
+#define INTEL_BDW_GT12_IDS(info)  \
 	INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \
 	INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \
 	INTEL_VGA_DEVICE(0x160B, info), /* GT1 Iris */ \
@@ -216,21 +212,17 @@
 	INTEL_VGA_DEVICE(0x1612, info), /* GT2 Halo */ \
 	INTEL_VGA_DEVICE(0x1616, info), /* GT2 ULT */ \
 	INTEL_VGA_DEVICE(0x161B, info), /* GT2 ULT */ \
-	INTEL_VGA_DEVICE(0x161E, info)  /* GT2 ULX */
-
-#define INTEL_BDW_GT12D_IDS(info) \
+	INTEL_VGA_DEVICE(0x161E, info),  /* GT2 ULX */ \
 	INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \
 	INTEL_VGA_DEVICE(0x160D, info), /* GT1 Workstation */ \
 	INTEL_VGA_DEVICE(0x161A, info), /* GT2 Server */ \
 	INTEL_VGA_DEVICE(0x161D, info)  /* GT2 Workstation */
 
-#define INTEL_BDW_GT3M_IDS(info) \
+#define INTEL_BDW_GT3_IDS(info) \
 	INTEL_VGA_DEVICE(0x1622, info), /* ULT */ \
 	INTEL_VGA_DEVICE(0x1626, info), /* ULT */ \
 	INTEL_VGA_DEVICE(0x162B, info), /* Iris */ \
-	INTEL_VGA_DEVICE(0x162E, info)  /* ULX */
-
-#define INTEL_BDW_GT3D_IDS(info) \
+	INTEL_VGA_DEVICE(0x162E, info),  /* ULX */\
 	INTEL_VGA_DEVICE(0x162A, info), /* Server */ \
 	INTEL_VGA_DEVICE(0x162D, info)  /* Workstation */
 
@@ -244,14 +236,12 @@
 	INTEL_VGA_DEVICE(0x163A, info), /* Server */ \
 	INTEL_VGA_DEVICE(0x163D, info)  /* Workstation */
 
-#define INTEL_BDW_M_IDS(info) \
-	INTEL_BDW_GT12M_IDS(info), \
-	INTEL_BDW_GT3M_IDS(info), \
-	INTEL_BDW_RSVDM_IDS(info)
-
-#define INTEL_BDW_D_IDS(info) \
-	INTEL_BDW_GT12D_IDS(info), \
-	INTEL_BDW_GT3D_IDS(info), \
+#define INTEL_BDW_IDS(info) \
+	INTEL_BDW_GT12_IDS(info), \
+	INTEL_BDW_GT3_IDS(info), \
+	INTEL_BDW_RSVDM_IDS(info), \
+	INTEL_BDW_GT12_IDS(info), \
+	INTEL_BDW_GT3_IDS(info), \
 	INTEL_BDW_RSVDD_IDS(info)
 
 #define INTEL_CHV_IDS(info) \
@@ -302,6 +292,10 @@
 	INTEL_VGA_DEVICE(0x5A84, info), /* APL HD Graphics 505 */ \
 	INTEL_VGA_DEVICE(0x5A85, info)  /* APL HD Graphics 500 */
 
+#define INTEL_GLK_IDS(info) \
+	INTEL_VGA_DEVICE(0x3184, info), \
+	INTEL_VGA_DEVICE(0x3185, info)
+
 #define INTEL_KBL_GT1_IDS(info)	\
 	INTEL_VGA_DEVICE(0x5913, info), /* ULT GT1.5 */ \
 	INTEL_VGA_DEVICE(0x5915, info), /* ULX GT1.5 */ \
diff --git a/lib/intel_device_info.c b/lib/intel_device_info.c
index 5aab684..5805b5e 100644
--- a/lib/intel_device_info.c
+++ b/lib/intel_device_info.c
@@ -138,36 +138,18 @@ static const struct intel_device_info intel_valleyview_info = {
 	.is_valleyview = true,
 	.codename = "valleyview"
 };
-static const struct intel_device_info intel_valleyview_m_info = {
-	.gen = BIT(6),
-	.is_mobile = true,
-	.is_valleyview = true,
-	.codename = "valleyview"
-};
 
 static const struct intel_device_info intel_haswell_info = {
 	.gen = BIT(6),
 	.is_haswell = true,
 	.codename = "haswell"
 };
-static const struct intel_device_info intel_haswell_m_info = {
-	.gen = BIT(6),
-	.is_mobile = true,
-	.is_haswell = true,
-	.codename = "haswell"
-};
 
 static const struct intel_device_info intel_broadwell_info = {
 	.gen = BIT(7),
 	.is_broadwell = true,
 	.codename = "broadwell"
 };
-static const struct intel_device_info intel_broadwell_m_info = {
-	.gen = BIT(7),
-	.is_mobile = true,
-	.is_broadwell = true,
-	.codename = "broadwell"
-};
 
 static const struct intel_device_info intel_cherryview_info = {
 	.gen = BIT(7),
@@ -222,14 +204,11 @@ static const struct pci_id_match intel_device_match[] = {
 	INTEL_IVB_D_IDS(&intel_ivybridge_info),
 	INTEL_IVB_M_IDS(&intel_ivybridge_m_info),
 
-	INTEL_HSW_D_IDS(&intel_haswell_info),
-	INTEL_HSW_M_IDS(&intel_haswell_m_info),
+	INTEL_HSW_IDS(&intel_haswell_info),
 
-	INTEL_VLV_D_IDS(&intel_valleyview_info),
-	INTEL_VLV_M_IDS(&intel_valleyview_m_info),
+	INTEL_VLV_IDS(&intel_valleyview_info),
 
-	INTEL_BDW_D_IDS(&intel_broadwell_info),
-	INTEL_BDW_M_IDS(&intel_broadwell_m_info),
+	INTEL_BDW_IDS(&intel_broadwell_info),
 
 	INTEL_CHV_IDS(&intel_cherryview_info),
 
diff --git a/overlay/igfx.c b/overlay/igfx.c
index 4a9181c..6d82bc8 100644
--- a/overlay/igfx.c
+++ b/overlay/igfx.c
@@ -145,14 +145,11 @@ static const struct pci_id_match match[] = {
 	INTEL_IVB_D_IDS(&ivybridge_info),
 	INTEL_IVB_M_IDS(&ivybridge_info),
 
-	INTEL_HSW_D_IDS(&haswell_info),
-	INTEL_HSW_M_IDS(&haswell_info),
+	INTEL_HSW_IDS(&haswell_info),
 
-	INTEL_VLV_D_IDS(&valleyview_info),
-	INTEL_VLV_M_IDS(&valleyview_info),
+	INTEL_VLV_IDS(&valleyview_info),
 
-	INTEL_BDW_D_IDS(&broadwell_info),
-	INTEL_BDW_M_IDS(&broadwell_info),
+	INTEL_BDW_IDS(&broadwell_info),
 
 	INTEL_CHV_IDS(&cherryview_info),
 
diff --git a/tests/gen7_forcewake_mt.c b/tests/gen7_forcewake_mt.c
index dea1e8a..07320ef 100644
--- a/tests/gen7_forcewake_mt.c
+++ b/tests/gen7_forcewake_mt.c
@@ -53,8 +53,7 @@ static const struct pci_id_match match[] = {
 	INTEL_IVB_D_IDS(NULL),
 	INTEL_IVB_M_IDS(NULL),
 
-	INTEL_HSW_D_IDS(NULL),
-	INTEL_HSW_M_IDS(NULL),
+	INTEL_HSW_IDS(NULL),
 
 	{ 0, 0, 0 },
 };
-- 
2.5.5

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[PATCH i-g-t 2/2] lib/intel_chipset: Add geminilake platform definition

[Ander Conselvan de Oliveira]

Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
 lib/intel_chipset.h     | 2 ++
 lib/intel_device_info.c | 8 ++++++++
 2 files changed, 10 insertions(+)

diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
index 3c1260b..259b45f 100644
--- a/lib/intel_chipset.h
+++ b/lib/intel_chipset.h
@@ -63,6 +63,7 @@ struct intel_device_info {
 	bool is_skylake : 1;
 	bool is_broxton : 1;
 	bool is_kabylake : 1;
+	bool is_geminilake : 1;
 	const char *codename;
 };
 
@@ -156,6 +157,7 @@ void intel_check_pch(void);
 #define IS_KABYLAKE(devid)	(intel_get_device_info(devid)->is_kabylake)
 #define IS_SKYLAKE(devid)	(intel_get_device_info(devid)->is_skylake)
 #define IS_BROXTON(devid)	(intel_get_device_info(devid)->is_broxton)
+#define IS_GEMINILAKE(devid)	(intel_get_device_info(devid)->is_geminilake)
 
 #define IS_GEN(devid, x)	(intel_get_device_info(devid)->gen & (1u << ((x)-1)))
 #define AT_LEAST_GEN(devid, x)	(intel_get_device_info(devid)->gen & -(1u << ((x)-1)))
diff --git a/lib/intel_device_info.c b/lib/intel_device_info.c
index 5805b5e..db4f383 100644
--- a/lib/intel_device_info.c
+++ b/lib/intel_device_info.c
@@ -175,6 +175,12 @@ static const struct intel_device_info intel_kabylake_info = {
 	.codename = "kabylake"
 };
 
+static const struct intel_device_info intel_geminilake_info = {
+	.gen = BIT(8),
+	.is_geminilake = true,
+	.codename = "geminilake"
+};
+
 static const struct pci_id_match intel_device_match[] = {
 	INTEL_I830_IDS(&intel_i830_info),
 	INTEL_I845G_IDS(&intel_i845_info),
@@ -218,6 +224,8 @@ static const struct pci_id_match intel_device_match[] = {
 
 	INTEL_KBL_IDS(&intel_kabylake_info),
 
+	INTEL_GLK_IDS(&intel_geminilake_info),
+
 	INTEL_VGA_DEVICE(PCI_MATCH_ANY, &intel_generic_info),
 };
 
-- 
2.5.5

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Re: [PATCH i-g-t 1/2] lib/i915_pciids.h: Update to latest version wich includes GLK ids

[Ander Conselvan De Oliveira]

Hi Petri,

I'm not sure what are the i-g-t rules regarding R-b tags nowadays. Does this require one or can I push it?

Thanks,
Ander

On Tue, 2016-12-20 at 14:33 +0200, Ander Conselvan de Oliveira wrote:
> Copy the include/drm/i915_pciids.h file from following kernel commit,
> which includes Geminilake PCI IDs.
> 
> commit 8363e3c3947d0e22955f94a6a87e4f17ce5087b4
> Author: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> Date:   Thu Nov 10 17:23:08 2016 +0200
> 
>     drm/i915/glk: Add Geminilake PCI IDs
> 
> Signed-off-by: Ander Conselvan de Oliveira 
> ---
>  lib/i915_pciids.h         | 42 ++++++++++++++++++------------------------
>  lib/intel_device_info.c   | 27 +++------------------------
>  overlay/igfx.c            |  9 +++------
>  tests/gen7_forcewake_mt.c |  3 +--
>  4 files changed, 25 insertions(+), 56 deletions(-)
> 
> diff --git a/lib/i915_pciids.h b/lib/i915_pciids.h
> index 33466bf..540be9f 100644
> --- a/lib/i915_pciids.h
> +++ b/lib/i915_pciids.h
> @@ -134,7 +134,7 @@
>  #define INTEL_IVB_Q_IDS(info) \
>  	INTEL_QUANTA_VGA_DEVICE(info) /* Quanta transcode */
>  
> -#define INTEL_HSW_D_IDS(info) \
> +#define INTEL_HSW_IDS(info) \
>  	INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \
>  	INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \
>  	INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \
> @@ -179,9 +179,7 @@
>  	INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \
>  	INTEL_VGA_DEVICE(0x0D0E, info), /* CRW GT1 reserved */ \
>  	INTEL_VGA_DEVICE(0x0D1E, info), /* CRW GT2 reserved */ \
> -	INTEL_VGA_DEVICE(0x0D2E, info)  /* CRW GT3 reserved */ \
> -
> -#define INTEL_HSW_M_IDS(info) \
> +	INTEL_VGA_DEVICE(0x0D2E, info),  /* CRW GT3 reserved */ \
>  	INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \
>  	INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \
>  	INTEL_VGA_DEVICE(0x0426, info), /* GT2 mobile */ \
> @@ -198,17 +196,15 @@
>  	INTEL_VGA_DEVICE(0x0D16, info), /* CRW GT2 mobile */ \
>  	INTEL_VGA_DEVICE(0x0D26, info)  /* CRW GT3 mobile */
>  
> -#define INTEL_VLV_M_IDS(info) \
> +#define INTEL_VLV_IDS(info) \
>  	INTEL_VGA_DEVICE(0x0f30, info), \
>  	INTEL_VGA_DEVICE(0x0f31, info), \
>  	INTEL_VGA_DEVICE(0x0f32, info), \
>  	INTEL_VGA_DEVICE(0x0f33, info), \
> -	INTEL_VGA_DEVICE(0x0157, info)
> -
> -#define INTEL_VLV_D_IDS(info) \
> +	INTEL_VGA_DEVICE(0x0157, info), \
>  	INTEL_VGA_DEVICE(0x0155, info)
>  
> -#define INTEL_BDW_GT12M_IDS(info)  \
> +#define INTEL_BDW_GT12_IDS(info)  \
>  	INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \
>  	INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \
>  	INTEL_VGA_DEVICE(0x160B, info), /* GT1 Iris */ \
> @@ -216,21 +212,17 @@
>  	INTEL_VGA_DEVICE(0x1612, info), /* GT2 Halo */ \
>  	INTEL_VGA_DEVICE(0x1616, info), /* GT2 ULT */ \
>  	INTEL_VGA_DEVICE(0x161B, info), /* GT2 ULT */ \
> -	INTEL_VGA_DEVICE(0x161E, info)  /* GT2 ULX */
> -
> -#define INTEL_BDW_GT12D_IDS(info) \
> +	INTEL_VGA_DEVICE(0x161E, info),  /* GT2 ULX */ \
>  	INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \
>  	INTEL_VGA_DEVICE(0x160D, info), /* GT1 Workstation */ \
>  	INTEL_VGA_DEVICE(0x161A, info), /* GT2 Server */ \
>  	INTEL_VGA_DEVICE(0x161D, info)  /* GT2 Workstation */
>  
> -#define INTEL_BDW_GT3M_IDS(info) \
> +#define INTEL_BDW_GT3_IDS(info) \
>  	INTEL_VGA_DEVICE(0x1622, info), /* ULT */ \
>  	INTEL_VGA_DEVICE(0x1626, info), /* ULT */ \
>  	INTEL_VGA_DEVICE(0x162B, info), /* Iris */ \
> -	INTEL_VGA_DEVICE(0x162E, info)  /* ULX */
> -
> -#define INTEL_BDW_GT3D_IDS(info) \
> +	INTEL_VGA_DEVICE(0x162E, info),  /* ULX */\
>  	INTEL_VGA_DEVICE(0x162A, info), /* Server */ \
>  	INTEL_VGA_DEVICE(0x162D, info)  /* Workstation */
>  
> @@ -244,14 +236,12 @@
>  	INTEL_VGA_DEVICE(0x163A, info), /* Server */ \
>  	INTEL_VGA_DEVICE(0x163D, info)  /* Workstation */
>  
> -#define INTEL_BDW_M_IDS(info) \
> -	INTEL_BDW_GT12M_IDS(info), \
> -	INTEL_BDW_GT3M_IDS(info), \
> -	INTEL_BDW_RSVDM_IDS(info)
> -
> -#define INTEL_BDW_D_IDS(info) \
> -	INTEL_BDW_GT12D_IDS(info), \
> -	INTEL_BDW_GT3D_IDS(info), \
> +#define INTEL_BDW_IDS(info) \
> +	INTEL_BDW_GT12_IDS(info), \
> +	INTEL_BDW_GT3_IDS(info), \
> +	INTEL_BDW_RSVDM_IDS(info), \
> +	INTEL_BDW_GT12_IDS(info), \
> +	INTEL_BDW_GT3_IDS(info), \
>  	INTEL_BDW_RSVDD_IDS(info)
>  
>  #define INTEL_CHV_IDS(info) \
> @@ -302,6 +292,10 @@
>  	INTEL_VGA_DEVICE(0x5A84, info), /* APL HD Graphics 505 */ \
>  	INTEL_VGA_DEVICE(0x5A85, info)  /* APL HD Graphics 500 */
>  
> +#define INTEL_GLK_IDS(info) \
> +	INTEL_VGA_DEVICE(0x3184, info), \
> +	INTEL_VGA_DEVICE(0x3185, info)
> +
>  #define INTEL_KBL_GT1_IDS(info)	\
>  	INTEL_VGA_DEVICE(0x5913, info), /* ULT GT1.5 */ \
>  	INTEL_VGA_DEVICE(0x5915, info), /* ULX GT1.5 */ \
> diff --git a/lib/intel_device_info.c b/lib/intel_device_info.c
> index 5aab684..5805b5e 100644
> --- a/lib/intel_device_info.c
> +++ b/lib/intel_device_info.c
> @@ -138,36 +138,18 @@ static const struct intel_device_info intel_valleyview_info = {
>  	.is_valleyview = true,
>  	.codename = "valleyview"
>  };
> -static const struct intel_device_info intel_valleyview_m_info = {
> -	.gen = BIT(6),
> -	.is_mobile = true,
> -	.is_valleyview = true,
> -	.codename = "valleyview"
> -};
>  
>  static const struct intel_device_info intel_haswell_info = {
>  	.gen = BIT(6),
>  	.is_haswell = true,
>  	.codename = "haswell"
>  };
> -static const struct intel_device_info intel_haswell_m_info = {
> -	.gen = BIT(6),
> -	.is_mobile = true,
> -	.is_haswell = true,
> -	.codename = "haswell"
> -};
>  
>  static const struct intel_device_info intel_broadwell_info = {
>  	.gen = BIT(7),
>  	.is_broadwell = true,
>  	.codename = "broadwell"
>  };
> -static const struct intel_device_info intel_broadwell_m_info = {
> -	.gen = BIT(7),
> -	.is_mobile = true,
> -	.is_broadwell = true,
> -	.codename = "broadwell"
> -};
>  
>  static const struct intel_device_info intel_cherryview_info = {
>  	.gen = BIT(7),
> @@ -222,14 +204,11 @@ static const struct pci_id_match intel_device_match[] = {
>  	INTEL_IVB_D_IDS(&intel_ivybridge_info),
>  	INTEL_IVB_M_IDS(&intel_ivybridge_m_info),
>  
> -	INTEL_HSW_D_IDS(&intel_haswell_info),
> -	INTEL_HSW_M_IDS(&intel_haswell_m_info),
> +	INTEL_HSW_IDS(&intel_haswell_info),
>  
> -	INTEL_VLV_D_IDS(&intel_valleyview_info),
> -	INTEL_VLV_M_IDS(&intel_valleyview_m_info),
> +	INTEL_VLV_IDS(&intel_valleyview_info),
>  
> -	INTEL_BDW_D_IDS(&intel_broadwell_info),
> -	INTEL_BDW_M_IDS(&intel_broadwell_m_info),
> +	INTEL_BDW_IDS(&intel_broadwell_info),
>  
>  	INTEL_CHV_IDS(&intel_cherryview_info),
>  
> diff --git a/overlay/igfx.c b/overlay/igfx.c
> index 4a9181c..6d82bc8 100644
> --- a/overlay/igfx.c
> +++ b/overlay/igfx.c
> @@ -145,14 +145,11 @@ static const struct pci_id_match match[] = {
>  	INTEL_IVB_D_IDS(&ivybridge_info),
>  	INTEL_IVB_M_IDS(&ivybridge_info),
>  
> -	INTEL_HSW_D_IDS(&haswell_info),
> -	INTEL_HSW_M_IDS(&haswell_info),
> +	INTEL_HSW_IDS(&haswell_info),
>  
> -	INTEL_VLV_D_IDS(&valleyview_info),
> -	INTEL_VLV_M_IDS(&valleyview_info),
> +	INTEL_VLV_IDS(&valleyview_info),
>  
> -	INTEL_BDW_D_IDS(&broadwell_info),
> -	INTEL_BDW_M_IDS(&broadwell_info),
> +	INTEL_BDW_IDS(&broadwell_info),
>  
>  	INTEL_CHV_IDS(&cherryview_info),
>  
> diff --git a/tests/gen7_forcewake_mt.c b/tests/gen7_forcewake_mt.c
> index dea1e8a..07320ef 100644
> --- a/tests/gen7_forcewake_mt.c
> +++ b/tests/gen7_forcewake_mt.c
> @@ -53,8 +53,7 @@ static const struct pci_id_match match[] = {
>  	INTEL_IVB_D_IDS(NULL),
>  	INTEL_IVB_M_IDS(NULL),
>  
> -	INTEL_HSW_D_IDS(NULL),
> -	INTEL_HSW_M_IDS(NULL),
> +	INTEL_HSW_IDS(NULL),
>  
>  	{ 0, 0, 0 },
>  };
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Re: [PATCH i-g-t 1/2] lib/i915_pciids.h: Update to latest version wich includes GLK ids

[Petri Latvala]

On Mon, Jan 02, 2017 at 04:33:03PM +0200, Ander Conselvan De Oliveira wrote:
> Hi Petri,
> 
> I'm not sure what are the i-g-t rules regarding R-b tags nowadays. Does this require one or can I push it?

The series is
Reviewed-by: Petri Latvala <petri.latvala@intel.com>

Some of the comments got misaligned but that's also present in the kernel.

R-b/A-b for all commits is preferred, for the record.


--
Petri Latvala



> 
> Thanks,
> Ander
> 
> On Tue, 2016-12-20 at 14:33 +0200, Ander Conselvan de Oliveira wrote:
> > Copy the include/drm/i915_pciids.h file from following kernel commit,
> > which includes Geminilake PCI IDs.
> > 
> > commit 8363e3c3947d0e22955f94a6a87e4f17ce5087b4
> > Author: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> > Date:   Thu Nov 10 17:23:08 2016 +0200
> > 
> >     drm/i915/glk: Add Geminilake PCI IDs
> > 
> > Signed-off-by: Ander Conselvan de Oliveira 
> > ---
> >  lib/i915_pciids.h         | 42 ++++++++++++++++++------------------------
> >  lib/intel_device_info.c   | 27 +++------------------------
> >  overlay/igfx.c            |  9 +++------
> >  tests/gen7_forcewake_mt.c |  3 +--
> >  4 files changed, 25 insertions(+), 56 deletions(-)
> > 
> > diff --git a/lib/i915_pciids.h b/lib/i915_pciids.h
> > index 33466bf..540be9f 100644
> > --- a/lib/i915_pciids.h
> > +++ b/lib/i915_pciids.h
> > @@ -134,7 +134,7 @@
> >  #define INTEL_IVB_Q_IDS(info) \
> >  	INTEL_QUANTA_VGA_DEVICE(info) /* Quanta transcode */
> >  
> > -#define INTEL_HSW_D_IDS(info) \
> > +#define INTEL_HSW_IDS(info) \
> >  	INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \
> >  	INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \
> >  	INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \
> > @@ -179,9 +179,7 @@
> >  	INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \
> >  	INTEL_VGA_DEVICE(0x0D0E, info), /* CRW GT1 reserved */ \
> >  	INTEL_VGA_DEVICE(0x0D1E, info), /* CRW GT2 reserved */ \
> > -	INTEL_VGA_DEVICE(0x0D2E, info)  /* CRW GT3 reserved */ \
> > -
> > -#define INTEL_HSW_M_IDS(info) \
> > +	INTEL_VGA_DEVICE(0x0D2E, info),  /* CRW GT3 reserved */ \
> >  	INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \
> >  	INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \
> >  	INTEL_VGA_DEVICE(0x0426, info), /* GT2 mobile */ \
> > @@ -198,17 +196,15 @@
> >  	INTEL_VGA_DEVICE(0x0D16, info), /* CRW GT2 mobile */ \
> >  	INTEL_VGA_DEVICE(0x0D26, info)  /* CRW GT3 mobile */
> >  
> > -#define INTEL_VLV_M_IDS(info) \
> > +#define INTEL_VLV_IDS(info) \
> >  	INTEL_VGA_DEVICE(0x0f30, info), \
> >  	INTEL_VGA_DEVICE(0x0f31, info), \
> >  	INTEL_VGA_DEVICE(0x0f32, info), \
> >  	INTEL_VGA_DEVICE(0x0f33, info), \
> > -	INTEL_VGA_DEVICE(0x0157, info)
> > -
> > -#define INTEL_VLV_D_IDS(info) \
> > +	INTEL_VGA_DEVICE(0x0157, info), \
> >  	INTEL_VGA_DEVICE(0x0155, info)
> >  
> > -#define INTEL_BDW_GT12M_IDS(info)  \
> > +#define INTEL_BDW_GT12_IDS(info)  \
> >  	INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \
> >  	INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \
> >  	INTEL_VGA_DEVICE(0x160B, info), /* GT1 Iris */ \
> > @@ -216,21 +212,17 @@
> >  	INTEL_VGA_DEVICE(0x1612, info), /* GT2 Halo */ \
> >  	INTEL_VGA_DEVICE(0x1616, info), /* GT2 ULT */ \
> >  	INTEL_VGA_DEVICE(0x161B, info), /* GT2 ULT */ \
> > -	INTEL_VGA_DEVICE(0x161E, info)  /* GT2 ULX */
> > -
> > -#define INTEL_BDW_GT12D_IDS(info) \
> > +	INTEL_VGA_DEVICE(0x161E, info),  /* GT2 ULX */ \
> >  	INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \
> >  	INTEL_VGA_DEVICE(0x160D, info), /* GT1 Workstation */ \
> >  	INTEL_VGA_DEVICE(0x161A, info), /* GT2 Server */ \
> >  	INTEL_VGA_DEVICE(0x161D, info)  /* GT2 Workstation */
> >  
> > -#define INTEL_BDW_GT3M_IDS(info) \
> > +#define INTEL_BDW_GT3_IDS(info) \
> >  	INTEL_VGA_DEVICE(0x1622, info), /* ULT */ \
> >  	INTEL_VGA_DEVICE(0x1626, info), /* ULT */ \
> >  	INTEL_VGA_DEVICE(0x162B, info), /* Iris */ \
> > -	INTEL_VGA_DEVICE(0x162E, info)  /* ULX */
> > -
> > -#define INTEL_BDW_GT3D_IDS(info) \
> > +	INTEL_VGA_DEVICE(0x162E, info),  /* ULX */\
> >  	INTEL_VGA_DEVICE(0x162A, info), /* Server */ \
> >  	INTEL_VGA_DEVICE(0x162D, info)  /* Workstation */
> >  
> > @@ -244,14 +236,12 @@
> >  	INTEL_VGA_DEVICE(0x163A, info), /* Server */ \
> >  	INTEL_VGA_DEVICE(0x163D, info)  /* Workstation */
> >  
> > -#define INTEL_BDW_M_IDS(info) \
> > -	INTEL_BDW_GT12M_IDS(info), \
> > -	INTEL_BDW_GT3M_IDS(info), \
> > -	INTEL_BDW_RSVDM_IDS(info)
> > -
> > -#define INTEL_BDW_D_IDS(info) \
> > -	INTEL_BDW_GT12D_IDS(info), \
> > -	INTEL_BDW_GT3D_IDS(info), \
> > +#define INTEL_BDW_IDS(info) \
> > +	INTEL_BDW_GT12_IDS(info), \
> > +	INTEL_BDW_GT3_IDS(info), \
> > +	INTEL_BDW_RSVDM_IDS(info), \
> > +	INTEL_BDW_GT12_IDS(info), \
> > +	INTEL_BDW_GT3_IDS(info), \
> >  	INTEL_BDW_RSVDD_IDS(info)
> >  
> >  #define INTEL_CHV_IDS(info) \
> > @@ -302,6 +292,10 @@
> >  	INTEL_VGA_DEVICE(0x5A84, info), /* APL HD Graphics 505 */ \
> >  	INTEL_VGA_DEVICE(0x5A85, info)  /* APL HD Graphics 500 */
> >  
> > +#define INTEL_GLK_IDS(info) \
> > +	INTEL_VGA_DEVICE(0x3184, info), \
> > +	INTEL_VGA_DEVICE(0x3185, info)
> > +
> >  #define INTEL_KBL_GT1_IDS(info)	\
> >  	INTEL_VGA_DEVICE(0x5913, info), /* ULT GT1.5 */ \
> >  	INTEL_VGA_DEVICE(0x5915, info), /* ULX GT1.5 */ \
> > diff --git a/lib/intel_device_info.c b/lib/intel_device_info.c
> > index 5aab684..5805b5e 100644
> > --- a/lib/intel_device_info.c
> > +++ b/lib/intel_device_info.c
> > @@ -138,36 +138,18 @@ static const struct intel_device_info intel_valleyview_info = {
> >  	.is_valleyview = true,
> >  	.codename = "valleyview"
> >  };
> > -static const struct intel_device_info intel_valleyview_m_info = {
> > -	.gen = BIT(6),
> > -	.is_mobile = true,
> > -	.is_valleyview = true,
> > -	.codename = "valleyview"
> > -};
> >  
> >  static const struct intel_device_info intel_haswell_info = {
> >  	.gen = BIT(6),
> >  	.is_haswell = true,
> >  	.codename = "haswell"
> >  };
> > -static const struct intel_device_info intel_haswell_m_info = {
> > -	.gen = BIT(6),
> > -	.is_mobile = true,
> > -	.is_haswell = true,
> > -	.codename = "haswell"
> > -};
> >  
> >  static const struct intel_device_info intel_broadwell_info = {
> >  	.gen = BIT(7),
> >  	.is_broadwell = true,
> >  	.codename = "broadwell"
> >  };
> > -static const struct intel_device_info intel_broadwell_m_info = {
> > -	.gen = BIT(7),
> > -	.is_mobile = true,
> > -	.is_broadwell = true,
> > -	.codename = "broadwell"
> > -};
> >  
> >  static const struct intel_device_info intel_cherryview_info = {
> >  	.gen = BIT(7),
> > @@ -222,14 +204,11 @@ static const struct pci_id_match intel_device_match[] = {
> >  	INTEL_IVB_D_IDS(&intel_ivybridge_info),
> >  	INTEL_IVB_M_IDS(&intel_ivybridge_m_info),
> >  
> > -	INTEL_HSW_D_IDS(&intel_haswell_info),
> > -	INTEL_HSW_M_IDS(&intel_haswell_m_info),
> > +	INTEL_HSW_IDS(&intel_haswell_info),
> >  
> > -	INTEL_VLV_D_IDS(&intel_valleyview_info),
> > -	INTEL_VLV_M_IDS(&intel_valleyview_m_info),
> > +	INTEL_VLV_IDS(&intel_valleyview_info),
> >  
> > -	INTEL_BDW_D_IDS(&intel_broadwell_info),
> > -	INTEL_BDW_M_IDS(&intel_broadwell_m_info),
> > +	INTEL_BDW_IDS(&intel_broadwell_info),
> >  
> >  	INTEL_CHV_IDS(&intel_cherryview_info),
> >  
> > diff --git a/overlay/igfx.c b/overlay/igfx.c
> > index 4a9181c..6d82bc8 100644
> > --- a/overlay/igfx.c
> > +++ b/overlay/igfx.c
> > @@ -145,14 +145,11 @@ static const struct pci_id_match match[] = {
> >  	INTEL_IVB_D_IDS(&ivybridge_info),
> >  	INTEL_IVB_M_IDS(&ivybridge_info),
> >  
> > -	INTEL_HSW_D_IDS(&haswell_info),
> > -	INTEL_HSW_M_IDS(&haswell_info),
> > +	INTEL_HSW_IDS(&haswell_info),
> >  
> > -	INTEL_VLV_D_IDS(&valleyview_info),
> > -	INTEL_VLV_M_IDS(&valleyview_info),
> > +	INTEL_VLV_IDS(&valleyview_info),
> >  
> > -	INTEL_BDW_D_IDS(&broadwell_info),
> > -	INTEL_BDW_M_IDS(&broadwell_info),
> > +	INTEL_BDW_IDS(&broadwell_info),
> >  
> >  	INTEL_CHV_IDS(&cherryview_info),
> >  
> > diff --git a/tests/gen7_forcewake_mt.c b/tests/gen7_forcewake_mt.c
> > index dea1e8a..07320ef 100644
> > --- a/tests/gen7_forcewake_mt.c
> > +++ b/tests/gen7_forcewake_mt.c
> > @@ -53,8 +53,7 @@ static const struct pci_id_match match[] = {
> >  	INTEL_IVB_D_IDS(NULL),
> >  	INTEL_IVB_M_IDS(NULL),
> >  
> > -	INTEL_HSW_D_IDS(NULL),
> > -	INTEL_HSW_M_IDS(NULL),
> > +	INTEL_HSW_IDS(NULL),
> >  
> >  	{ 0, 0, 0 },
> >  };
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