* [PATCH 1/2] drm/i915: Tidy the tail of i915_tiling_ok()
@ 2017-02-03 11:50 Chris Wilson
2017-02-03 11:50 ` [PATCH 2/2] drm/i915: Allow large objects to be tiled on gen2/3 Chris Wilson
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Chris Wilson @ 2017-02-03 11:50 UTC (permalink / raw)
To: intel-gfx
The current tail breaks the pattern of if (check) return false, which
can catch the reader out. If we move the gen2/3 power-of-two test into
the earlier gen2/3 branch, we can eliminate the contrary tail.
Suggested-by: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
---
drivers/gpu/drm/i915/i915_gem_tiling.c | 10 ++++------
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index a80f362d2ac1..62148396c796 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -158,6 +158,9 @@ i915_tiling_ok(struct drm_i915_gem_object *obj,
if (stride > 8192)
return false;
+ if (!is_power_of_2(stride))
+ return false;
+
if (IS_GEN3(i915)) {
if (obj->base.size > I830_FENCE_MAX_SIZE_VAL << 20)
return false;
@@ -176,12 +179,7 @@ i915_tiling_ok(struct drm_i915_gem_object *obj,
if (!stride || !IS_ALIGNED(stride, tile_width))
return false;
- /* 965+ just needs multiples of tile width */
- if (INTEL_GEN(i915) >= 4)
- return true;
-
- /* Pre-965 needs power of two tile widths */
- return is_power_of_2(stride);
+ return true;
}
static bool i915_vma_fence_prepare(struct i915_vma *vma,
--
2.11.0
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^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/2] drm/i915: Allow large objects to be tiled on gen2/3
2017-02-03 11:50 [PATCH 1/2] drm/i915: Tidy the tail of i915_tiling_ok() Chris Wilson
@ 2017-02-03 11:50 ` Chris Wilson
2017-02-03 13:03 ` Joonas Lahtinen
2017-02-03 14:27 ` ✗ Fi.CI.BAT: warning for series starting with [1/2] drm/i915: Tidy the tail of i915_tiling_ok() Patchwork
2017-02-03 15:05 ` [PATCH 1/2] " Tvrtko Ursulin
2 siblings, 1 reply; 6+ messages in thread
From: Chris Wilson @ 2017-02-03 11:50 UTC (permalink / raw)
To: intel-gfx
We now have partial VMA support to break large objects into fence sized
regions and no longer have to restrict tiling to small objects on gen2/3
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
drivers/gpu/drm/i915/i915_gem_tiling.c | 8 --------
1 file changed, 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index 62148396c796..01b883abf57a 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -160,14 +160,6 @@ i915_tiling_ok(struct drm_i915_gem_object *obj,
if (!is_power_of_2(stride))
return false;
-
- if (IS_GEN3(i915)) {
- if (obj->base.size > I830_FENCE_MAX_SIZE_VAL << 20)
- return false;
- } else {
- if (obj->base.size > I830_FENCE_MAX_SIZE_VAL << 19)
- return false;
- }
}
if (IS_GEN2(i915) ||
--
2.11.0
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^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] drm/i915: Allow large objects to be tiled on gen2/3
2017-02-03 11:50 ` [PATCH 2/2] drm/i915: Allow large objects to be tiled on gen2/3 Chris Wilson
@ 2017-02-03 13:03 ` Joonas Lahtinen
2017-02-03 17:59 ` Chris Wilson
0 siblings, 1 reply; 6+ messages in thread
From: Joonas Lahtinen @ 2017-02-03 13:03 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On pe, 2017-02-03 at 11:50 +0000, Chris Wilson wrote:
> We now have partial VMA support to break large objects into fence sized
> regions and no longer have to restrict tiling to small objects on gen2/3
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Hmm, there really isn't any single commit for Fixes, and it's not a
regression, so fine as is.
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Regards, Joonas
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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^ permalink raw reply [flat|nested] 6+ messages in thread
* ✗ Fi.CI.BAT: warning for series starting with [1/2] drm/i915: Tidy the tail of i915_tiling_ok()
2017-02-03 11:50 [PATCH 1/2] drm/i915: Tidy the tail of i915_tiling_ok() Chris Wilson
2017-02-03 11:50 ` [PATCH 2/2] drm/i915: Allow large objects to be tiled on gen2/3 Chris Wilson
@ 2017-02-03 14:27 ` Patchwork
2017-02-03 15:05 ` [PATCH 1/2] " Tvrtko Ursulin
2 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2017-02-03 14:27 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915: Tidy the tail of i915_tiling_ok()
URL : https://patchwork.freedesktop.org/series/19052/
State : warning
== Summary ==
Series 19052v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/19052/revisions/1/mbox/
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass -> DMESG-WARN (fi-snb-2600)
fi-bdw-5557u total:247 pass:233 dwarn:0 dfail:0 fail:0 skip:14
fi-bsw-n3050 total:247 pass:208 dwarn:0 dfail:0 fail:0 skip:39
fi-bxt-j4205 total:247 pass:225 dwarn:0 dfail:0 fail:0 skip:22
fi-bxt-t5700 total:78 pass:65 dwarn:0 dfail:0 fail:0 skip:12
fi-byt-j1900 total:247 pass:220 dwarn:0 dfail:0 fail:0 skip:27
fi-byt-n2820 total:247 pass:216 dwarn:0 dfail:0 fail:0 skip:31
fi-hsw-4770 total:247 pass:228 dwarn:0 dfail:0 fail:0 skip:19
fi-hsw-4770r total:247 pass:228 dwarn:0 dfail:0 fail:0 skip:19
fi-ilk-650 total:14 pass:13 dwarn:0 dfail:0 fail:0 skip:0
fi-ivb-3520m total:247 pass:226 dwarn:0 dfail:0 fail:0 skip:21
fi-ivb-3770 total:247 pass:226 dwarn:0 dfail:0 fail:0 skip:21
fi-kbl-7500u total:247 pass:224 dwarn:0 dfail:0 fail:2 skip:21
fi-skl-6260u total:247 pass:234 dwarn:0 dfail:0 fail:0 skip:13
fi-skl-6700hq total:247 pass:227 dwarn:0 dfail:0 fail:0 skip:20
fi-skl-6700k total:247 pass:222 dwarn:4 dfail:0 fail:0 skip:21
fi-snb-2520m total:247 pass:216 dwarn:0 dfail:0 fail:0 skip:31
fi-snb-2600 total:247 pass:214 dwarn:1 dfail:0 fail:0 skip:32
e7f4379a8f59bebb1bdefe0584e128dfdd27a86a drm-tip: 2017y-02m-03d-13h-03m-49s UTC integration manifest
6853a50 drm/i915: Allow large objects to be tiled on gen2/3
9db9278 drm/i915: Tidy the tail of i915_tiling_ok()
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3690/
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] drm/i915: Tidy the tail of i915_tiling_ok()
2017-02-03 11:50 [PATCH 1/2] drm/i915: Tidy the tail of i915_tiling_ok() Chris Wilson
2017-02-03 11:50 ` [PATCH 2/2] drm/i915: Allow large objects to be tiled on gen2/3 Chris Wilson
2017-02-03 14:27 ` ✗ Fi.CI.BAT: warning for series starting with [1/2] drm/i915: Tidy the tail of i915_tiling_ok() Patchwork
@ 2017-02-03 15:05 ` Tvrtko Ursulin
2 siblings, 0 replies; 6+ messages in thread
From: Tvrtko Ursulin @ 2017-02-03 15:05 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On 03/02/2017 11:50, Chris Wilson wrote:
> The current tail breaks the pattern of if (check) return false, which
> can catch the reader out. If we move the gen2/3 power-of-two test into
> the earlier gen2/3 branch, we can eliminate the contrary tail.
>
> Suggested-by: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_gem_tiling.c | 10 ++++------
> 1 file changed, 4 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
> index a80f362d2ac1..62148396c796 100644
> --- a/drivers/gpu/drm/i915/i915_gem_tiling.c
> +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
> @@ -158,6 +158,9 @@ i915_tiling_ok(struct drm_i915_gem_object *obj,
> if (stride > 8192)
> return false;
>
> + if (!is_power_of_2(stride))
> + return false;
> +
> if (IS_GEN3(i915)) {
> if (obj->base.size > I830_FENCE_MAX_SIZE_VAL << 20)
> return false;
> @@ -176,12 +179,7 @@ i915_tiling_ok(struct drm_i915_gem_object *obj,
> if (!stride || !IS_ALIGNED(stride, tile_width))
> return false;
>
> - /* 965+ just needs multiples of tile width */
> - if (INTEL_GEN(i915) >= 4)
> - return true;
> -
> - /* Pre-965 needs power of two tile widths */
> - return is_power_of_2(stride);
> + return true;
> }
>
> static bool i915_vma_fence_prepare(struct i915_vma *vma,
>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Regards,
Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] drm/i915: Allow large objects to be tiled on gen2/3
2017-02-03 13:03 ` Joonas Lahtinen
@ 2017-02-03 17:59 ` Chris Wilson
0 siblings, 0 replies; 6+ messages in thread
From: Chris Wilson @ 2017-02-03 17:59 UTC (permalink / raw)
To: Joonas Lahtinen; +Cc: intel-gfx
On Fri, Feb 03, 2017 at 03:03:10PM +0200, Joonas Lahtinen wrote:
> On pe, 2017-02-03 at 11:50 +0000, Chris Wilson wrote:
> > We now have partial VMA support to break large objects into fence sized
> > regions and no longer have to restrict tiling to small objects on gen2/3
> >
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>
> Hmm, there really isn't any single commit for Fixes, and it's not a
> regression, so fine as is.
>
> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
I ran it through gem_mmap_gtt on Pineview and it seemed happy with the
large (> GTT) tiled objects.
Pushed,
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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2017-02-03 11:50 [PATCH 1/2] drm/i915: Tidy the tail of i915_tiling_ok() Chris Wilson
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2017-02-03 13:03 ` Joonas Lahtinen
2017-02-03 17:59 ` Chris Wilson
2017-02-03 14:27 ` ✗ Fi.CI.BAT: warning for series starting with [1/2] drm/i915: Tidy the tail of i915_tiling_ok() Patchwork
2017-02-03 15:05 ` [PATCH 1/2] " Tvrtko Ursulin
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