* [PATCH] drm/i915/skl: Do not write the replay bit of the ring mode register for Gen 9
@ 2017-02-17 23:43 Kelvin Gardiner
2017-02-18 0:22 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-02-20 22:34 ` [PATCH] " Ceraolo Spurio, Daniele
0 siblings, 2 replies; 4+ messages in thread
From: Kelvin Gardiner @ 2017-02-17 23:43 UTC (permalink / raw)
To: intel-gfx
The reply bit of the ring mode register is only valid on Gen 8.
Therefore do not write this for Gen 9.
Signed-off-by: Kelvin Gardiner <kelvin.gardiner@intel.com>
---
drivers/gpu/drm/i915/intel_lrc.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index ee431d3..fa15377 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1259,9 +1259,15 @@ static int gen8_init_common_ring(struct intel_engine_cs *engine)
intel_engine_init_hangcheck(engine);
I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
- I915_WRITE(RING_MODE_GEN7(engine),
- _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
- _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
+
+ if (INTEL_GEN(dev_priv) >= 9)
+ I915_WRITE(RING_MODE_GEN7(engine),
+ _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
+ else
+ I915_WRITE(RING_MODE_GEN7(engine),
+ _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
+ _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
+
I915_WRITE(RING_HWS_PGA(engine->mmio_base),
engine->status_page.ggtt_offset);
POSTING_READ(RING_HWS_PGA(engine->mmio_base));
--
1.9.1
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^ permalink raw reply related [flat|nested] 4+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/skl: Do not write the replay bit of the ring mode register for Gen 9
2017-02-17 23:43 [PATCH] drm/i915/skl: Do not write the replay bit of the ring mode register for Gen 9 Kelvin Gardiner
@ 2017-02-18 0:22 ` Patchwork
2017-02-20 22:34 ` [PATCH] " Ceraolo Spurio, Daniele
1 sibling, 0 replies; 4+ messages in thread
From: Patchwork @ 2017-02-18 0:22 UTC (permalink / raw)
To: Kelvin Gardiner; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/skl: Do not write the replay bit of the ring mode register for Gen 9
URL : https://patchwork.freedesktop.org/series/19875/
State : success
== Summary ==
Series 19875v1 drm/i915/skl: Do not write the replay bit of the ring mode register for Gen 9
https://patchwork.freedesktop.org/api/1.0/series/19875/revisions/1/mbox/
fi-bdw-5557u total:252 pass:241 dwarn:0 dfail:0 fail:0 skip:11
fi-bsw-n3050 total:252 pass:213 dwarn:0 dfail:0 fail:0 skip:39
fi-bxt-j4205 total:252 pass:233 dwarn:0 dfail:0 fail:0 skip:19
fi-bxt-t5700 total:83 pass:70 dwarn:0 dfail:0 fail:0 skip:12
fi-byt-j1900 total:252 pass:225 dwarn:0 dfail:0 fail:0 skip:27
fi-byt-n2820 total:252 pass:221 dwarn:0 dfail:0 fail:0 skip:31
fi-hsw-4770 total:252 pass:236 dwarn:0 dfail:0 fail:0 skip:16
fi-hsw-4770r total:252 pass:236 dwarn:0 dfail:0 fail:0 skip:16
fi-ilk-650 total:252 pass:202 dwarn:0 dfail:0 fail:0 skip:50
fi-ivb-3520m total:252 pass:234 dwarn:0 dfail:0 fail:0 skip:18
fi-ivb-3770 total:252 pass:234 dwarn:0 dfail:0 fail:0 skip:18
fi-kbl-7500u total:252 pass:234 dwarn:0 dfail:0 fail:0 skip:18
fi-skl-6260u total:252 pass:242 dwarn:0 dfail:0 fail:0 skip:10
fi-skl-6700hq total:252 pass:235 dwarn:0 dfail:0 fail:0 skip:17
fi-skl-6700k total:252 pass:230 dwarn:4 dfail:0 fail:0 skip:18
fi-skl-6770hq total:252 pass:242 dwarn:0 dfail:0 fail:0 skip:10
fi-snb-2520m total:252 pass:224 dwarn:0 dfail:0 fail:0 skip:28
fi-snb-2600 total:252 pass:223 dwarn:0 dfail:0 fail:0 skip:29
d13370a042e9d05329bcac34eb43c64e4f6704e0 drm-tip: 2017y-02m-17d-21h-23m-28s UTC integration manifest
8dcc17e drm/i915/skl: Do not write the replay bit of the ring mode register for Gen 9
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3892/
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^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] drm/i915/skl: Do not write the replay bit of the ring mode register for Gen 9
2017-02-17 23:43 [PATCH] drm/i915/skl: Do not write the replay bit of the ring mode register for Gen 9 Kelvin Gardiner
2017-02-18 0:22 ` ✓ Fi.CI.BAT: success for " Patchwork
@ 2017-02-20 22:34 ` Ceraolo Spurio, Daniele
2017-02-22 11:21 ` Joonas Lahtinen
1 sibling, 1 reply; 4+ messages in thread
From: Ceraolo Spurio, Daniele @ 2017-02-20 22:34 UTC (permalink / raw)
To: Kelvin Gardiner, intel-gfx
On 2/17/2017 3:43 PM, Kelvin Gardiner wrote:
> The reply bit of the ring mode register is only valid on Gen 8.
s/reply/replay. Also, from the specs it looks like this bit is reserved
in Gen8 production steppings, so we should be able to drop it entirely.
Thanks,
Daniele
> Therefore do not write this for Gen 9.
>
> Signed-off-by: Kelvin Gardiner <kelvin.gardiner@intel.com>
> ---
> drivers/gpu/drm/i915/intel_lrc.c | 12 +++++++++---
> 1 file changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index ee431d3..fa15377 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1259,9 +1259,15 @@ static int gen8_init_common_ring(struct intel_engine_cs *engine)
> intel_engine_init_hangcheck(engine);
>
> I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
> - I915_WRITE(RING_MODE_GEN7(engine),
> - _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
> - _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
> +
> + if (INTEL_GEN(dev_priv) >= 9)
> + I915_WRITE(RING_MODE_GEN7(engine),
> + _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
> + else
> + I915_WRITE(RING_MODE_GEN7(engine),
> + _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
> + _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
> +
> I915_WRITE(RING_HWS_PGA(engine->mmio_base),
> engine->status_page.ggtt_offset);
> POSTING_READ(RING_HWS_PGA(engine->mmio_base));
>
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^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] drm/i915/skl: Do not write the replay bit of the ring mode register for Gen 9
2017-02-20 22:34 ` [PATCH] " Ceraolo Spurio, Daniele
@ 2017-02-22 11:21 ` Joonas Lahtinen
0 siblings, 0 replies; 4+ messages in thread
From: Joonas Lahtinen @ 2017-02-22 11:21 UTC (permalink / raw)
To: Ceraolo Spurio, Daniele, Kelvin Gardiner, intel-gfx
On ma, 2017-02-20 at 14:34 -0800, Ceraolo Spurio, Daniele wrote:
>
> On 2/17/2017 3:43 PM, Kelvin Gardiner wrote:
> >
> > The reply bit of the ring mode register is only valid on Gen 8.
>
> s/reply/replay. Also, from the specs it looks like this bit is reserved
> in Gen8 production steppings, so we should be able to drop it entirely.
>
> Thanks,
> Daniele
Yeah, should be removed completely.
Regards, Joonas
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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^ permalink raw reply [flat|nested] 4+ messages in thread
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2017-02-17 23:43 [PATCH] drm/i915/skl: Do not write the replay bit of the ring mode register for Gen 9 Kelvin Gardiner
2017-02-18 0:22 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-02-20 22:34 ` [PATCH] " Ceraolo Spurio, Daniele
2017-02-22 11:21 ` Joonas Lahtinen
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