From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 2/6] drm/i915/cnp: Add PCI ID for Cannonpoint LP PCH
Date: Fri, 2 Jun 2017 13:06:40 -0700 [thread overview]
Message-ID: <1496434004-29812-2-git-send-email-rodrigo.vivi@intel.com> (raw)
In-Reply-To: <1496434004-29812-1-git-send-email-rodrigo.vivi@intel.com>
From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
The first two bytes of PCI ID for CNP_LP PCH are the same as that of
SPT_LP. We should really be looking at the first 9 bits instead of the
first 8 to identify platforms, although this seems to have not caused any
problems on earlier platforms. Introduce a 9 bit extended mask for SPT and
CNP while not touching the code for any of the other platforms.
v2: (Rodrigo) Make platform agnostic and fix commit message.
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 8 +++++++-
drivers/gpu/drm/i915/i915_drv.h | 4 ++++
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9e4c13e..90b646c 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -170,6 +170,9 @@ static void intel_detect_pch(struct drm_i915_private *dev_priv)
while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
if (pch->vendor == PCI_VENDOR_ID_INTEL) {
unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
+ unsigned short id_ext = pch->device &
+ INTEL_PCH_DEVICE_ID_MASK_EXT;
+
dev_priv->pch_id = id;
if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
@@ -206,7 +209,7 @@ static void intel_detect_pch(struct drm_i915_private *dev_priv)
DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
WARN_ON(!IS_SKYLAKE(dev_priv) &&
!IS_KABYLAKE(dev_priv));
- } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
+ } else if (id_ext == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_SPT;
DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
WARN_ON(!IS_SKYLAKE(dev_priv) &&
@@ -219,6 +222,9 @@ static void intel_detect_pch(struct drm_i915_private *dev_priv)
} else if (id == INTEL_PCH_CNP_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_CNP;
DRM_DEBUG_KMS("Found CannonPoint PCH\n");
+ } else if (id_ext == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE) {
+ dev_priv->pch_type = PCH_CNP;
+ DRM_DEBUG_KMS("Found CannonPoint LP PCH\n");
} else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
(id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0b82604..c31c0cf 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2959,6 +2959,7 @@ static inline struct scatterlist *__sg_next(struct scatterlist *sg)
#define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu)
#define INTEL_PCH_DEVICE_ID_MASK 0xff00
+#define INTEL_PCH_DEVICE_ID_MASK_EXT 0xff80
#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
@@ -2968,12 +2969,15 @@ static inline struct scatterlist *__sg_next(struct scatterlist *sg)
#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
#define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA200
#define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300
+#define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE 0x9D80
#define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
#define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
#define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
#define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
#define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
+#define HAS_PCH_CNP_LP(dev_priv) \
+ ((dev_priv)->pch_id == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE)
#define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
#define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
#define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
--
1.9.1
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next prev parent reply other threads:[~2017-06-02 20:06 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-02 20:06 [PATCH 1/6] drm/i915/cnp: Introduce Cannonpoint PCH Rodrigo Vivi
2017-06-02 20:06 ` Rodrigo Vivi [this message]
2017-06-02 20:06 ` [PATCH 3/6] drm/i915/cnp: Get/set proper Raw clock frequency on CNP Rodrigo Vivi
2017-06-02 20:06 ` [PATCH 4/6] drm/i915/cnp: Backlight support for CNP Rodrigo Vivi
2017-06-02 20:06 ` [PATCH 5/6] drm/i915/cnp: add CNP gmbus support Rodrigo Vivi
2017-06-02 20:06 ` [PATCH 6/6] drm/i915/cnp: Panel Power sequence changes for CNP PCH Rodrigo Vivi
2017-06-03 3:15 ` Rodrigo Vivi
2017-06-02 20:21 ` ✓ Fi.CI.BAT: success for series starting with [1/6] drm/i915/cnp: Introduce Cannonpoint PCH Patchwork
-- strict thread matches above, loose matches on Subject: below --
2017-06-01 22:33 [PATCH 1/6] " Rodrigo Vivi
2017-06-01 22:33 ` [PATCH 2/6] drm/i915/cnp: Add PCI ID for Cannonpoint LP PCH Rodrigo Vivi
2017-06-01 0:23 [PATCH 1/6] drm/i915/cnp: Introduce Cannonpoint PCH Rodrigo Vivi
2017-06-01 0:23 ` [PATCH 2/6] drm/i915/cnp: Add PCI ID for Cannonpoint LP PCH Rodrigo Vivi
2017-05-30 22:11 [PATCH 1/6] drm/i915/cnp: Introduce Cannonpoint PCH Rodrigo Vivi
2017-05-30 22:11 ` [PATCH 2/6] drm/i915/cnp: Add PCI ID for Cannonpoint LP PCH Rodrigo Vivi
2017-05-30 21:53 [PATCH 1/6] drm/i915/cnp: Introduce Cannonpoint PCH Rodrigo Vivi
2017-05-30 21:53 ` [PATCH 2/6] drm/i915/cnp: Add PCI ID for Cannonpoint LP PCH Rodrigo Vivi
2017-05-09 19:16 [PATCH 0/6] Cannonpoint Enabling Patches Anusha Srivatsa
2017-05-09 19:16 ` [PATCH 2/6] drm/i915/cnp: Add PCI ID for Cannonpoint LP PCH Anusha Srivatsa
2017-05-08 23:44 [PATCH 0/6] Cannonpoint Enabling Patches Anusha Srivatsa
2017-05-08 23:45 ` [PATCH 2/6] drm/i915/cnp: Add PCI ID for Cannonpoint LP PCH Anusha Srivatsa
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