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From: Sagar Arun Kamble <sagar.a.kamble@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 05/10] drm/i915: Name i915_runtime_pm structure in dev_priv as "rpm"
Date: Wed,  4 Oct 2017 19:37:20 +0530	[thread overview]
Message-ID: <1507126045-24526-6-git-send-email-sagar.a.kamble@intel.com> (raw)
In-Reply-To: <1507126045-24526-1-git-send-email-sagar.a.kamble@intel.com>

Will be using pm for state containing RPS/RC6 state in the next patch.

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c         |  8 ++++----
 drivers/gpu/drm/i915/i915_drv.h         |  2 +-
 drivers/gpu/drm/i915/i915_gpu_error.c   |  4 ++--
 drivers/gpu/drm/i915/i915_irq.c         |  8 ++++----
 drivers/gpu/drm/i915/intel_drv.h        | 10 +++++-----
 drivers/gpu/drm/i915/intel_pm.c         |  4 ++--
 drivers/gpu/drm/i915/intel_runtime_pm.c | 10 +++++-----
 7 files changed, 23 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 7056bb2..db05a6d 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2523,12 +2523,12 @@ static int intel_runtime_suspend(struct device *kdev)
 	intel_uncore_suspend(dev_priv);
 
 	enable_rpm_wakeref_asserts(dev_priv);
-	WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
+	WARN_ON_ONCE(atomic_read(&dev_priv->rpm.wakeref_count));
 
 	if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
 		DRM_ERROR("Unclaimed access detected prior to suspending\n");
 
-	dev_priv->pm.suspended = true;
+	dev_priv->rpm.suspended = true;
 
 	/*
 	 * FIXME: We really should find a document that references the arguments
@@ -2574,11 +2574,11 @@ static int intel_runtime_resume(struct device *kdev)
 
 	DRM_DEBUG_KMS("Resuming device\n");
 
-	WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
+	WARN_ON_ONCE(atomic_read(&dev_priv->rpm.wakeref_count));
 	disable_rpm_wakeref_asserts(dev_priv);
 
 	intel_opregion_notify_adapter(dev_priv, PCI_D0);
-	dev_priv->pm.suspended = false;
+	dev_priv->rpm.suspended = false;
 	if (intel_uncore_unclaimed_mmio(dev_priv))
 		DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b7cba89..8afb528 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2519,7 +2519,7 @@ struct drm_i915_private {
 		bool distrust_bios_wm;
 	} wm;
 
-	struct i915_runtime_pm pm;
+	struct i915_runtime_pm rpm;
 
 	struct {
 		bool initialized;
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index c14552a..2e25b21 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1672,8 +1672,8 @@ static void i915_capture_gen_state(struct drm_i915_private *dev_priv,
 				   struct i915_gpu_state *error)
 {
 	error->awake = dev_priv->gt.awake;
-	error->wakelock = atomic_read(&dev_priv->pm.wakeref_count);
-	error->suspended = dev_priv->pm.suspended;
+	error->wakelock = atomic_read(&dev_priv->rpm.wakeref_count);
+	error->suspended = dev_priv->rpm.suspended;
 
 	error->iommu = -1;
 #ifdef CONFIG_INTEL_IOMMU
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 0b756213..9cbc68f 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -4166,7 +4166,7 @@ int intel_irq_install(struct drm_i915_private *dev_priv)
 	 * interrupts as enabled _before_ actually enabling them to avoid
 	 * special cases in our ordering checks.
 	 */
-	dev_priv->pm.irqs_enabled = true;
+	dev_priv->rpm.irqs_enabled = true;
 
 	return drm_irq_install(&dev_priv->drm, dev_priv->drm.pdev->irq);
 }
@@ -4182,7 +4182,7 @@ void intel_irq_uninstall(struct drm_i915_private *dev_priv)
 {
 	drm_irq_uninstall(&dev_priv->drm);
 	intel_hpd_cancel_work(dev_priv);
-	dev_priv->pm.irqs_enabled = false;
+	dev_priv->rpm.irqs_enabled = false;
 }
 
 /**
@@ -4195,7 +4195,7 @@ void intel_irq_uninstall(struct drm_i915_private *dev_priv)
 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
 {
 	dev_priv->drm.driver->irq_uninstall(&dev_priv->drm);
-	dev_priv->pm.irqs_enabled = false;
+	dev_priv->rpm.irqs_enabled = false;
 	synchronize_irq(dev_priv->drm.irq);
 }
 
@@ -4208,7 +4208,7 @@ void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
  */
 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
 {
-	dev_priv->pm.irqs_enabled = true;
+	dev_priv->rpm.irqs_enabled = true;
 	dev_priv->drm.driver->irq_preinstall(&dev_priv->drm);
 	dev_priv->drm.driver->irq_postinstall(&dev_priv->drm);
 }
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 0cab667..b5bfddd 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1254,7 +1254,7 @@ static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
 	 * We only use drm_irq_uninstall() at unload and VT switch, so
 	 * this is the only thing we need to check.
 	 */
-	return dev_priv->pm.irqs_enabled;
+	return dev_priv->rpm.irqs_enabled;
 }
 
 int intel_get_crtc_scanline(struct intel_crtc *crtc);
@@ -1790,7 +1790,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
 static inline void
 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
 {
-	WARN_ONCE(dev_priv->pm.suspended,
+	WARN_ONCE(dev_priv->rpm.suspended,
 		  "Device suspended during HW access\n");
 }
 
@@ -1798,7 +1798,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
 {
 	assert_rpm_device_not_suspended(dev_priv);
-	WARN_ONCE(!atomic_read(&dev_priv->pm.wakeref_count),
+	WARN_ONCE(!atomic_read(&dev_priv->rpm.wakeref_count),
 		  "RPM wakelock ref not held during HW access");
 }
 
@@ -1823,7 +1823,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
 static inline void
 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
 {
-	atomic_inc(&dev_priv->pm.wakeref_count);
+	atomic_inc(&dev_priv->rpm.wakeref_count);
 }
 
 /**
@@ -1840,7 +1840,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
 static inline void
 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
 {
-	atomic_dec(&dev_priv->pm.wakeref_count);
+	atomic_dec(&dev_priv->rpm.wakeref_count);
 }
 
 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d99025a..feb38ee 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -9347,8 +9347,8 @@ void intel_pm_setup(struct drm_i915_private *dev_priv)
 			  __intel_autoenable_gt_powersave);
 	atomic_set(&dev_priv->rps.num_waiters, 0);
 
-	dev_priv->pm.suspended = false;
-	atomic_set(&dev_priv->pm.wakeref_count, 0);
+	dev_priv->rpm.suspended = false;
+	atomic_set(&dev_priv->rpm.wakeref_count, 0);
 }
 
 static u64 vlv_residency_raw(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 7933d1b..84c947a 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -187,7 +187,7 @@ bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 	struct i915_power_well *power_well;
 	bool is_enabled;
 
-	if (dev_priv->pm.suspended)
+	if (dev_priv->rpm.suspended)
 		return false;
 
 	is_enabled = true;
@@ -3125,7 +3125,7 @@ void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
 	ret = pm_runtime_get_sync(kdev);
 	WARN_ONCE(ret < 0, "pm_runtime_get_sync() failed: %d\n", ret);
 
-	atomic_inc(&dev_priv->pm.wakeref_count);
+	atomic_inc(&dev_priv->rpm.wakeref_count);
 	assert_rpm_wakelock_held(dev_priv);
 }
 
@@ -3159,7 +3159,7 @@ bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv)
 			return false;
 	}
 
-	atomic_inc(&dev_priv->pm.wakeref_count);
+	atomic_inc(&dev_priv->rpm.wakeref_count);
 	assert_rpm_wakelock_held(dev_priv);
 
 	return true;
@@ -3190,7 +3190,7 @@ void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
 	assert_rpm_wakelock_held(dev_priv);
 	pm_runtime_get_noresume(kdev);
 
-	atomic_inc(&dev_priv->pm.wakeref_count);
+	atomic_inc(&dev_priv->rpm.wakeref_count);
 }
 
 /**
@@ -3207,7 +3207,7 @@ void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
 	struct device *kdev = &pdev->dev;
 
 	assert_rpm_wakelock_held(dev_priv);
-	atomic_dec(&dev_priv->pm.wakeref_count);
+	atomic_dec(&dev_priv->rpm.wakeref_count);
 
 	pm_runtime_mark_last_busy(kdev);
 	pm_runtime_put_autosuspend(kdev);
-- 
1.9.1

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  parent reply	other threads:[~2017-10-04 14:04 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-10-04 14:07 [PATCH 00/10] drm/i915: Separate RC6, RPS, Ring Frequency management Sagar Arun Kamble
2017-10-04 14:07 ` [PATCH 01/10] drm/i915: Separate RPS and RC6 handling for gen6+ Sagar Arun Kamble
2017-10-05 17:36   ` Chris Wilson
2017-10-04 14:07 ` [PATCH 02/10] drm/i915: Separate RPS and RC6 handling for BDW Sagar Arun Kamble
2017-10-05 17:39   ` Chris Wilson
2017-10-04 14:07 ` [PATCH 03/10] drm/i915: Separate RPS and RC6 handling for VLV Sagar Arun Kamble
2017-10-05 17:42   ` Chris Wilson
2017-10-04 14:07 ` [PATCH 04/10] drm/i915: Separate RPS and RC6 handling for CHV Sagar Arun Kamble
2017-10-05 17:42   ` Chris Wilson
2017-10-04 14:07 ` Sagar Arun Kamble [this message]
2017-10-05 17:44   ` [PATCH 05/10] drm/i915: Name i915_runtime_pm structure in dev_priv as "rpm" Chris Wilson
2017-10-05 17:46     ` Chris Wilson
2017-10-04 14:07 ` [PATCH 06/10] drm/i915: Name structure in dev_priv that contains RPS/RC6 state as "pm" Sagar Arun Kamble
2017-10-05 17:47   ` Chris Wilson
2017-10-04 14:07 ` [PATCH 07/10] drm/i915: Rename intel_enable_rc6 to intel_rc6_enabled Sagar Arun Kamble
2017-10-05 17:49   ` Chris Wilson
2017-10-04 14:07 ` [PATCH 08/10] drm/i915: Create generic function to setup ring frequency table Sagar Arun Kamble
2017-10-04 17:04   ` Chris Wilson
2017-10-04 17:46     ` Sagar Arun Kamble
2017-10-04 14:07 ` [PATCH 09/10] drm/i915: Create generic functions to control RC6, RPS Sagar Arun Kamble
2017-10-05 17:54   ` Chris Wilson
2017-10-06 11:31     ` Sagar Arun Kamble
2017-10-04 14:07 ` [PATCH 10/10] drm/i915: Introduce separate status variable for RC6 and Ring frequency setup Sagar Arun Kamble
2017-10-04 17:06   ` Chris Wilson
2017-10-04 18:41     ` Sagar Arun Kamble
2017-10-04 15:26 ` ✓ Fi.CI.BAT: success for drm/i915: Separate RC6, RPS, Ring Frequency management Patchwork
2017-10-04 17:07 ` [PATCH 00/10] " Chris Wilson
2017-10-04 17:14 ` ✓ Fi.CI.IGT: success for " Patchwork

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