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From: Vidya Srinivas <vidya.srinivas@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 08/15] drm/i915/skl+: nv12 workaround disable WM level 1-7
Date: Thu, 4 Jan 2018 10:44:28 +0000 (UTC)
Date: Sun,  7 Jan 2018 15:29:12 +0530	[thread overview]
Message-ID: <1515319159-30543-9-git-send-email-vidya.srinivas@intel.com> (raw)
In-Reply-To: <1515319159-30543-1-git-send-email-vidya.srinivas@intel.com>

From: Mahesh Kumar <mahesh1.kumar@intel.com>

Display Workaround #0826 (SKL:ALL BXT:ALL) & #1059(CNL:A)
Hardware sometimes fails to wake memory from pkg C states fetching the
last few lines of planar YUV 420 (NV12) planes. This causes
intermittent underflow and corruption.
WA: Disable package C states or do not enable latency levels 1 through 7
(WM1 - WM7) on NV12 planes.

Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d75fd3b..90aa216 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4610,6 +4610,17 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
 		}
 	}
 
+	/*
+	 * Display WA #826 (SKL:ALL, BXT:ALL) & #1059 (CNL:A)
+	 * disable wm level 1-7 on NV12 planes
+	 */
+	if (wp->is_nv12 && level && (IS_SKYLAKE(dev_priv) ||
+			IS_BROXTON(dev_priv) ||
+			IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0))) {
+		result->plane_en = false;
+		return 0;
+	}
+
 	result->plane_res_b = res_blocks;
 	result->plane_res_l = res_lines;
 	result->plane_en = true;
-- 
2.7.4

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  parent reply	other threads:[~2018-01-04 10:46 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-01-04 10:44 [PATCH 00/15] Adding NV12 support Vidya Srinivas
2018-01-04 10:44 ` [PATCH 01/15] drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values Vidya Srinivas
2018-01-04 10:44 ` [PATCH 03/15] drm/i915/skl+: add NV12 in skl_format_to_fourcc Vidya Srinivas
2018-01-04 10:44 ` [PATCH 02/15] drm/i915/skl+: refactore WM calculation for NV12 Vidya Srinivas
2018-01-04 16:19   ` Maarten Lankhorst
2018-01-04 10:44 ` [PATCH 06/15] drm/i915/skl+: pass skl_wm_level struct to wm compute func Vidya Srinivas
2018-01-04 10:44 ` [PATCH 05/15] drm/i915/skl+: NV12 related changes for WM Vidya Srinivas
2018-01-04 10:44 ` [PATCH 04/15] drm/i915/skl+: support varification of DDB HW state for NV12 Vidya Srinivas
2018-01-05 12:16   ` Maarten Lankhorst
2018-01-04 10:44 ` [PATCH 07/15] drm/i915/skl+: make sure higher latency level has higher wm value Vidya Srinivas
2018-01-04 10:44 ` [PATCH 11/15] drm/i915: Update format_is_yuv() to include NV12 Vidya Srinivas
2018-01-04 10:44 ` [PATCH 09/15] drm/i915/skl: split skl_compute_ddb function Vidya Srinivas
2018-01-04 10:44 ` Vidya Srinivas [this message]
2018-01-08 12:07   ` [PATCH 08/15] drm/i915/skl+: nv12 workaround disable WM level 1-7 Maarten Lankhorst
2018-01-04 10:44 ` [PATCH 12/15] drm/i915: Upscale scaler max scale for NV12 Vidya Srinivas
2018-01-04 10:44 ` [PATCH 13/15] drm/i915: Add NV12 as supported format for primary plane Vidya Srinivas
2018-01-08 12:31   ` Maarten Lankhorst
2018-01-04 10:44 ` [PATCH 10/15] drm/i915: Set scaler mode for NV12 Vidya Srinivas
2018-01-04 10:44 ` [PATCH 14/15] drm/i915: Add NV12 as supported format for sprite plane Vidya Srinivas
2018-01-08 12:33   ` Maarten Lankhorst
2018-01-09  2:19     ` Srinivas, Vidya
2018-01-09 10:02       ` Maarten Lankhorst
2018-01-09 10:06         ` Srinivas, Vidya
2018-01-11  9:57         ` Srinivas, Vidya
2018-01-04 10:44 ` [PATCH 15/15] drm/i915: Add NV12 support to intel_framebuffer_init Vidya Srinivas
2018-01-04 11:12 ` ✓ Fi.CI.BAT: success for Adding NV12 support (rev4) Patchwork
  -- strict thread matches above, loose matches on Subject: below --
2018-01-15  3:18 [PATCH 00/15] Adding NV12 support Vidya Srinivas
2018-01-15  3:18 ` [PATCH 08/15] drm/i915/skl+: nv12 workaround disable WM level 1-7 Vidya Srinivas

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