From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
To: Tarun Vyas <tarun.vyas@intel.com>, intel-gfx@lists.freedesktop.org
Cc: rodrigo.vivi@intel.com
Subject: Re: [PATCH v3] drm/i915: Wait for PSR exit before checking for vblank evasion
Date: Thu, 21 Jun 2018 18:52:41 -0700 [thread overview]
Message-ID: <1529632361.12516.73.camel@intel.com> (raw)
In-Reply-To: <20180622010322.92851-2-tarun.vyas@intel.com>
On Thu, 2018-06-21 at 18:03 -0700, Tarun Vyas wrote:
> The PIPEDSL freezes on PSR entry and if PSR hasn't fully exited, then
> the pipe_update_start call schedules itself out to check back later.
>
> On ChromeOS-4.4 kernel, which is fairly up-to-date w.r.t drm/i915 but
> lags w.r.t core kernel code, hot plugging an external display
> triggers
> tons of "potential atomic update errors" in the dmesg, on *pipe A*. A
> closer analysis reveals that we try to read the scanline 3 times and
> eventually timeout, b/c PSR hasn't exited fully leading to a PIPEDSL
> stuck @ 1599. This issue is not seen on upstream kernels, b/c for
> *some*
> reason we loop inside intel_pipe_update start for ~2+ msec which in
> this
> case is more than enough to exit PSR fully, hence an *unstuck*
> PIPEDSL
> counter, hence no error. On the other hand, the ChromeOS kernel
> spends
> ~1.1 msec looping inside intel_pipe_update_start and hence errors out
> b/c the source is still in PSR.
>
> Regardless, we should wait for PSR exit (if PSR is disabled, we incur
> a ~1-2 usec penalty) before reading the PIPEDSL, b/c if we haven't
> fully exited PSR, then checking for vblank evasion isn't actually
> applicable.
>
> Signed-off-by: Tarun Vyas <tarun.vyas@intel.com>
> ---
> drivers/gpu/drm/i915/intel_sprite.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> b/drivers/gpu/drm/i915/intel_sprite.c
> index 344c0e709b19..34754771d7a7 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -107,14 +107,16 @@ void intel_pipe_update_start(const struct
> intel_crtc_state *new_crtc_state)
> VBLANK_EVASION
> _TIME_US);
> max = vblank_start - 1;
>
> - local_irq_disable();
> -
> if (min <= 0 || max <= 0)
> return;
>
> if (WARN_ON(drm_crtc_vblank_get(&crtc->base)))
> return;
>
> + psr_wait_for_idle_lockless(dev_priv);
Document the implicit requirement that we enable vblank interrupts
before waiting for PSR idle. Looks good to me, I'll wait for others to
chime in.
The hope is https://bugs.freedesktop.org/show_bug.cgi?id=106678 gets
fixed with this patch.
> +
> + local_irq_disable();
> +
> crtc->debug.min_vbl = min;
> crtc->debug.max_vbl = max;
> trace_i915_pipe_update_start(crtc);
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next prev parent reply other threads:[~2018-06-22 1:26 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-06-22 1:03 [PATCH] drm/i915/psr: Lockless version of psr_wait_for_idle Tarun Vyas
2018-06-22 1:03 ` [PATCH v3] drm/i915: Wait for PSR exit before checking for vblank evasion Tarun Vyas
2018-06-22 1:52 ` Dhinakaran Pandiyan [this message]
2018-06-22 3:02 ` kbuild test robot
2018-06-22 1:27 ` ✗ Fi.CI.BAT: failure for drm/i915/psr: Lockless version of psr_wait_for_idle (rev2) Patchwork
2018-06-22 1:49 ` [PATCH] drm/i915/psr: Lockless version of psr_wait_for_idle Dhinakaran Pandiyan
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