* [PATCH v4 1/2] drm/i915/skl: Rework MOCS tables to keep common part in a define
@ 2018-11-05 13:50 Tomasz Lis
2018-11-05 13:50 ` [PATCH v4 2/2] drm/i915/icl: Define MOCS table for Icelake Tomasz Lis
` (2 more replies)
0 siblings, 3 replies; 8+ messages in thread
From: Tomasz Lis @ 2018-11-05 13:50 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
The MOCS tables are going to be very similar across platforms.
To reduce the amount of copied code, this patch rips the common part and
puts it into a definition valid for all gen9 platforms.
Signed-off-by: Tomasz Lis <tomasz.lis@intel.com>
Suggested-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/intel_mocs.c | 61 ++++++++++++++-------------------------
1 file changed, 22 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
index 77e9871..76aed59 100644
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -96,26 +96,29 @@ struct drm_i915_mocs_table {
* may only be updated incrementally by adding entries at the
* end.
*/
-static const struct drm_i915_mocs_entry skylake_mocs_table[] = {
- [I915_MOCS_UNCACHED] = {
- /* 0x00000009 */
- .control_value = LE_CACHEABILITY(LE_UC) |
- LE_TGT_CACHE(LE_TC_LLC_ELLC) |
- LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
- LE_PFM(0) | LE_SCF(0),
- /* 0x0010 */
- .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
- },
- [I915_MOCS_PTE] = {
- /* 0x00000038 */
- .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
- LE_TGT_CACHE(LE_TC_LLC_ELLC) |
- LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
- LE_PFM(0) | LE_SCF(0),
- /* 0x0030 */
- .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+#define GEN9_MOCS_TABLE \
+ [I915_MOCS_UNCACHED] = { \
+ /* 0x00000009 */ \
+ .control_value = LE_CACHEABILITY(LE_UC) | \
+ LE_TGT_CACHE(LE_TC_LLC_ELLC) | \
+ LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | \
+ LE_PFM(0) | LE_SCF(0), \
+ /* 0x0010 */ \
+ .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), \
+ }, \
+ [I915_MOCS_PTE] = { \
+ /* 0x00000038 */ \
+ .control_value = LE_CACHEABILITY(LE_PAGETABLE) | \
+ LE_TGT_CACHE(LE_TC_LLC_ELLC) | \
+ LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | \
+ LE_PFM(0) | LE_SCF(0), \
+ /* 0x0030 */ \
+ .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), \
},
+
+static const struct drm_i915_mocs_entry skylake_mocs_table[] = {
+ GEN9_MOCS_TABLE
[I915_MOCS_CACHED] = {
/* 0x0000003b */
.control_value = LE_CACHEABILITY(LE_WB) |
@@ -129,33 +132,13 @@ static const struct drm_i915_mocs_entry skylake_mocs_table[] = {
/* NOTE: the LE_TGT_CACHE is not used on Broxton */
static const struct drm_i915_mocs_entry broxton_mocs_table[] = {
- [I915_MOCS_UNCACHED] = {
- /* 0x00000009 */
- .control_value = LE_CACHEABILITY(LE_UC) |
- LE_TGT_CACHE(LE_TC_LLC_ELLC) |
- LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
- LE_PFM(0) | LE_SCF(0),
-
- /* 0x0010 */
- .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
- },
- [I915_MOCS_PTE] = {
- /* 0x00000038 */
- .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
- LE_TGT_CACHE(LE_TC_LLC_ELLC) |
- LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
- LE_PFM(0) | LE_SCF(0),
-
- /* 0x0030 */
- .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
- },
+ GEN9_MOCS_TABLE
[I915_MOCS_CACHED] = {
/* 0x00000039 */
.control_value = LE_CACHEABILITY(LE_UC) |
LE_TGT_CACHE(LE_TC_LLC_ELLC) |
LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
LE_PFM(0) | LE_SCF(0),
-
/* 0x0030 */
.l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
},
--
2.7.4
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^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v4 2/2] drm/i915/icl: Define MOCS table for Icelake
2018-11-05 13:50 [PATCH v4 1/2] drm/i915/skl: Rework MOCS tables to keep common part in a define Tomasz Lis
@ 2018-11-05 13:50 ` Tomasz Lis
2018-11-06 2:29 ` Daniele Ceraolo Spurio
2018-11-06 10:47 ` Joonas Lahtinen
2018-11-05 14:16 ` ✓ Fi.CI.BAT: success for series starting with [v4,1/2] drm/i915/skl: Rework MOCS tables to keep common part in a define Patchwork
2018-11-05 15:30 ` ✓ Fi.CI.IGT: " Patchwork
2 siblings, 2 replies; 8+ messages in thread
From: Tomasz Lis @ 2018-11-05 13:50 UTC (permalink / raw)
To: intel-gfx
Cc: Adam Cetnerowski, Piotr Rozenfeld, Lucas De Marchi, Anuj Phogat,
Mika Kuoppala
The table has been unified across OSes to minimize virtualization overhead.
The MOCS table is now published as part of bspec, and versioned. Entries
are supposed to never be modified, but new ones can be added. Adding
entries increases table version. The patch includes version 1 entries.
Meaning of each entry is now explained in bspec, and user mode clients
are expected to know what each entry means. The 3 entries used for previous
platforms are still compatible with their legacy definitions, but that is
not guaranteed to be true for future platforms.
v2: Fixed SCC values, improved commit comment (Daniele)
v3: Improved MOCS table comment (Daniele)
v4: Moved new entries below gen9 ones. Put common entries into
definition to be used in multiple arrays. (Lucas)
BSpec: 34007
BSpec: 560
Signed-off-by: Tomasz Lis <tomasz.lis@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> (v3)
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: Zhi A Wang <zhi.a.wang@intel.com>
Cc: Anuj Phogat <anuj.phogat@intel.com>
Cc: Adam Cetnerowski <adam.cetnerowski@intel.com>
Cc: Piotr Rozenfeld <piotr.rozenfeld@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/intel_mocs.c | 249 +++++++++++++++++++++++++++++++++++---
1 file changed, 235 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
index 76aed59..2a1e5f0 100644
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -44,6 +44,8 @@ struct drm_i915_mocs_table {
#define LE_SCC(value) ((value) << 8)
#define LE_PFM(value) ((value) << 11)
#define LE_SCF(value) ((value) << 14)
+#define LE_CoS(value) ((value) << 15)
+#define LE_SSE(value) ((value) << 17)
/* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */
#define L3_ESC(value) ((value) << 0)
@@ -80,21 +82,21 @@ struct drm_i915_mocs_table {
* LNCFCMOCS0 - LNCFCMOCS32 registers.
*
* These tables are intended to be kept reasonably consistent across
- * platforms. However some of the fields are not applicable to all of
- * them.
+ * HW platforms, and for ICL+, be identical across OSes. To achieve
+ * that, for Icelake and above, list of entries is published as part
+ * of bspec.
*
* Entries not part of the following tables are undefined as far as
- * userspace is concerned and shouldn't be relied upon. For the time
- * being they will be implicitly initialized to the strictest caching
- * configuration (uncached) to guarantee forwards compatibility with
- * userspace programs written against more recent kernels providing
- * additional MOCS entries.
+ * userspace is concerned and shouldn't be relied upon.
*
- * NOTE: These tables MUST start with being uncached and the length
- * MUST be less than 63 as the last two registers are reserved
- * by the hardware. These tables are part of the kernel ABI and
- * may only be updated incrementally by adding entries at the
- * end.
+ * The last two entries are reserved by the hardware. For ICL+ they
+ * should be initialized according to bspec and never used, for older
+ * platforms they should never be written to.
+ *
+ * NOTE: These tables are part of bspec and defined as part of hardware
+ * interface for ICL+. For older platforms, they are part of kernel
+ * ABI. It is expected that existing entries will remain constant
+ * and the tables will only be updated by adding new entries.
*/
#define GEN9_MOCS_TABLE \
@@ -144,6 +146,222 @@ static const struct drm_i915_mocs_entry broxton_mocs_table[] = {
},
};
+#define GEN11_MOCS_TABLE \
+ [0] = { \
+ /* Base - Uncached (Deprecated) */ \
+ .control_value = LE_CACHEABILITY(LE_UC) | \
+ LE_TGT_CACHE(LE_TC_LLC) | \
+ LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | \
+ LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
+ .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), \
+ }, \
+ [1] = { \
+ /* Base - L3 + LeCC:PAT (Deprecated) */ \
+ .control_value = LE_CACHEABILITY(LE_PAGETABLE) | \
+ LE_TGT_CACHE(LE_TC_LLC) | \
+ LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | \
+ LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
+ .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), \
+ }, \
+ [2] = { \
+ /* Base - L3 + LLC */ \
+ .control_value = LE_CACHEABILITY(LE_WB) | \
+ LE_TGT_CACHE(LE_TC_LLC) | \
+ LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | \
+ LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
+ .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), \
+ }, \
+ [3] = { \
+ /* Base - Uncached */ \
+ .control_value = LE_CACHEABILITY(LE_UC) | \
+ LE_TGT_CACHE(LE_TC_LLC) | \
+ LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | \
+ LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
+ .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), \
+ }, \
+ [4] = { \
+ /* Base - L3 */ \
+ .control_value = LE_CACHEABILITY(LE_UC) | \
+ LE_TGT_CACHE(LE_TC_LLC) | \
+ LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | \
+ LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
+ .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), \
+ }, \
+ [5] = { \
+ /* Base - LLC */ \
+ .control_value = LE_CACHEABILITY(LE_WB) | \
+ LE_TGT_CACHE(LE_TC_LLC) | \
+ LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | \
+ LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
+ .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), \
+ }, \
+ [6] = { \
+ /* Age 0 - LLC */ \
+ .control_value = LE_CACHEABILITY(LE_WB) | \
+ LE_TGT_CACHE(LE_TC_LLC) | \
+ LE_LRUM(1) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | \
+ LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
+ .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), \
+ }, \
+ [7] = { \
+ /* Age 0 - L3 + LLC */ \
+ .control_value = LE_CACHEABILITY(LE_WB) | \
+ LE_TGT_CACHE(LE_TC_LLC) | \
+ LE_LRUM(1) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | \
+ LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
+ .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), \
+ }, \
+ [8] = { \
+ /* Age: Don't Chg. - LLC */ \
+ .control_value = LE_CACHEABILITY(LE_WB) | \
+ LE_TGT_CACHE(LE_TC_LLC) | \
+ LE_LRUM(2) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | \
+ LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
+ .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), \
+ }, \
+ [9] = { \
+ /* Age: Don't Chg. - L3 + LLC */ \
+ .control_value = LE_CACHEABILITY(LE_WB) | \
+ LE_TGT_CACHE(LE_TC_LLC) | \
+ LE_LRUM(2) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | \
+ LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
+ .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), \
+ }, \
+ [10] = { \
+ /* No AOM - LLC */ \
+ .control_value = LE_CACHEABILITY(LE_WB) | \
+ LE_TGT_CACHE(LE_TC_LLC) | \
+ LE_LRUM(3) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) | \
+ LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
+ .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), \
+ }, \
+ [11] = { \
+ /* No AOM - L3 + LLC */ \
+ .control_value = LE_CACHEABILITY(LE_WB) | \
+ LE_TGT_CACHE(LE_TC_LLC) | \
+ LE_LRUM(3) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) | \
+ LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
+ .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), \
+ }, \
+ [12] = { \
+ /* No AOM; Age 0 - LLC */ \
+ .control_value = LE_CACHEABILITY(LE_WB) | \
+ LE_TGT_CACHE(LE_TC_LLC) | \
+ LE_LRUM(1) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) | \
+ LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
+ .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), \
+ }, \
+ [13] = { \
+ /* No AOM; Age 0 - L3 + LLC */ \
+ .control_value = LE_CACHEABILITY(LE_WB) | \
+ LE_TGT_CACHE(LE_TC_LLC) | \
+ LE_LRUM(1) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) | \
+ LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
+ .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), \
+ }, \
+ [14] = { \
+ /* No AOM; Age:DC - LLC */ \
+ .control_value = LE_CACHEABILITY(LE_WB) | \
+ LE_TGT_CACHE(LE_TC_LLC) | \
+ LE_LRUM(2) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) | \
+ LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
+ .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), \
+ }, \
+ [15] = { \
+ /* No AOM; Age:DC - L3 + LLC */ \
+ .control_value = LE_CACHEABILITY(LE_WB) | \
+ LE_TGT_CACHE(LE_TC_LLC) | \
+ LE_LRUM(2) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) | \
+ LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
+ .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), \
+ }, \
+ [18] = { \
+ /* Self-Snoop - L3 + LLC */ \
+ .control_value = LE_CACHEABILITY(LE_WB) | \
+ LE_TGT_CACHE(LE_TC_LLC) | \
+ LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | \
+ LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(3), \
+ .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), \
+ }, \
+ [19] = { \
+ /* Skip Caching - L3 + LLC(12.5%) */ \
+ .control_value = LE_CACHEABILITY(LE_WB) | \
+ LE_TGT_CACHE(LE_TC_LLC) | \
+ LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(7) | \
+ LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
+ .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), \
+ }, \
+ [20] = { \
+ /* Skip Caching - L3 + LLC(25%) */ \
+ .control_value = LE_CACHEABILITY(LE_WB) | \
+ LE_TGT_CACHE(LE_TC_LLC) | \
+ LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(3) | \
+ LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
+ .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), \
+ }, \
+ [21] = { \
+ /* Skip Caching - L3 + LLC(50%) */ \
+ .control_value = LE_CACHEABILITY(LE_WB) | \
+ LE_TGT_CACHE(LE_TC_LLC) | \
+ LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(1) | \
+ LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
+ .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), \
+ }, \
+ [22] = { \
+ /* Skip Caching - L3 + LLC(75%) */ \
+ .control_value = LE_CACHEABILITY(LE_WB) | \
+ LE_TGT_CACHE(LE_TC_LLC) | \
+ LE_LRUM(3) | LE_AOM(0) | LE_RSC(1) | LE_SCC(3) | \
+ LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
+ .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), \
+ }, \
+ [23] = { \
+ /* Skip Caching - L3 + LLC(87.5%) */ \
+ .control_value = LE_CACHEABILITY(LE_WB) | \
+ LE_TGT_CACHE(LE_TC_LLC) | \
+ LE_LRUM(3) | LE_AOM(0) | LE_RSC(1) | LE_SCC(7) | \
+ LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
+ .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), \
+ }, \
+ [62] = { \
+ /* HW Reserved - SW program but never use */ \
+ .control_value = LE_CACHEABILITY(LE_WB) | \
+ LE_TGT_CACHE(LE_TC_LLC) | \
+ LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | \
+ LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
+ .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), \
+ }, \
+ [63] = { \
+ /* HW Reserved - SW program but never use */ \
+ .control_value = LE_CACHEABILITY(LE_WB) | \
+ LE_TGT_CACHE(LE_TC_LLC) | \
+ LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | \
+ LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
+ .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), \
+ },
+
+static const struct drm_i915_mocs_entry icelake_mocs_table[] = {
+ GEN11_MOCS_TABLE
+ [16] = {
+ /* Reserved - For future use */
+ .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
+ LE_TGT_CACHE(LE_TC_PAGETABLE) |
+ LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+ LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+ .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_DIRECT),
+ },
+ [17] = {
+ /* Reserved - For future use */
+ .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
+ LE_TGT_CACHE(LE_TC_PAGETABLE) |
+ LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+ LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+ .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_DIRECT),
+ },
+};
+
/**
* get_mocs_settings()
* @dev_priv: i915 device.
@@ -161,8 +379,11 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv,
{
bool result = false;
- if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv) ||
- IS_ICELAKE(dev_priv)) {
+ if (IS_ICELAKE(dev_priv)) {
+ table->size = ARRAY_SIZE(icelake_mocs_table);
+ table->table = icelake_mocs_table;
+ result = true;
+ } else if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
table->size = ARRAY_SIZE(skylake_mocs_table);
table->table = skylake_mocs_table;
result = true;
--
2.7.4
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^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v4 2/2] drm/i915/icl: Define MOCS table for Icelake
2018-11-05 13:50 ` [PATCH v4 2/2] drm/i915/icl: Define MOCS table for Icelake Tomasz Lis
@ 2018-11-06 2:29 ` Daniele Ceraolo Spurio
2018-11-06 10:47 ` Joonas Lahtinen
1 sibling, 0 replies; 8+ messages in thread
From: Daniele Ceraolo Spurio @ 2018-11-06 2:29 UTC (permalink / raw)
To: Tomasz Lis, intel-gfx
Cc: Adam Cetnerowski, Lucas De Marchi, Anuj Phogat, Piotr Rozenfeld,
Mika Kuoppala
On 05/11/2018 05:50, Tomasz Lis wrote:
> The table has been unified across OSes to minimize virtualization overhead.
>
> The MOCS table is now published as part of bspec, and versioned. Entries
> are supposed to never be modified, but new ones can be added. Adding
> entries increases table version. The patch includes version 1 entries.
>
> Meaning of each entry is now explained in bspec, and user mode clients
> are expected to know what each entry means. The 3 entries used for previous
> platforms are still compatible with their legacy definitions, but that is
> not guaranteed to be true for future platforms.
>
> v2: Fixed SCC values, improved commit comment (Daniele)
> v3: Improved MOCS table comment (Daniele)
> v4: Moved new entries below gen9 ones. Put common entries into
> definition to be used in multiple arrays. (Lucas)
>
> BSpec: 34007
> BSpec: 560
> Signed-off-by: Tomasz Lis <tomasz.lis@intel.com>
> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> (v3)
The table is the same as v3 and I'm ok with the new approach, so my r-b
stands.
Thanks,
Daniele
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
> Cc: Zhi A Wang <zhi.a.wang@intel.com>
> Cc: Anuj Phogat <anuj.phogat@intel.com>
> Cc: Adam Cetnerowski <adam.cetnerowski@intel.com>
> Cc: Piotr Rozenfeld <piotr.rozenfeld@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/intel_mocs.c | 249 +++++++++++++++++++++++++++++++++++---
> 1 file changed, 235 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
> index 76aed59..2a1e5f0 100644
> --- a/drivers/gpu/drm/i915/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/intel_mocs.c
> @@ -44,6 +44,8 @@ struct drm_i915_mocs_table {
> #define LE_SCC(value) ((value) << 8)
> #define LE_PFM(value) ((value) << 11)
> #define LE_SCF(value) ((value) << 14)
> +#define LE_CoS(value) ((value) << 15)
> +#define LE_SSE(value) ((value) << 17)
>
> /* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */
> #define L3_ESC(value) ((value) << 0)
> @@ -80,21 +82,21 @@ struct drm_i915_mocs_table {
> * LNCFCMOCS0 - LNCFCMOCS32 registers.
> *
> * These tables are intended to be kept reasonably consistent across
> - * platforms. However some of the fields are not applicable to all of
> - * them.
> + * HW platforms, and for ICL+, be identical across OSes. To achieve
> + * that, for Icelake and above, list of entries is published as part
> + * of bspec.
> *
> * Entries not part of the following tables are undefined as far as
> - * userspace is concerned and shouldn't be relied upon. For the time
> - * being they will be implicitly initialized to the strictest caching
> - * configuration (uncached) to guarantee forwards compatibility with
> - * userspace programs written against more recent kernels providing
> - * additional MOCS entries.
> + * userspace is concerned and shouldn't be relied upon.
> *
> - * NOTE: These tables MUST start with being uncached and the length
> - * MUST be less than 63 as the last two registers are reserved
> - * by the hardware. These tables are part of the kernel ABI and
> - * may only be updated incrementally by adding entries at the
> - * end.
> + * The last two entries are reserved by the hardware. For ICL+ they
> + * should be initialized according to bspec and never used, for older
> + * platforms they should never be written to.
> + *
> + * NOTE: These tables are part of bspec and defined as part of hardware
> + * interface for ICL+. For older platforms, they are part of kernel
> + * ABI. It is expected that existing entries will remain constant
> + * and the tables will only be updated by adding new entries.
> */
>
> #define GEN9_MOCS_TABLE \
> @@ -144,6 +146,222 @@ static const struct drm_i915_mocs_entry broxton_mocs_table[] = {
> },
> };
>
> +#define GEN11_MOCS_TABLE \
> + [0] = { \
> + /* Base - Uncached (Deprecated) */ \
> + .control_value = LE_CACHEABILITY(LE_UC) | \
> + LE_TGT_CACHE(LE_TC_LLC) | \
> + LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | \
> + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
> + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), \
> + }, \
> + [1] = { \
> + /* Base - L3 + LeCC:PAT (Deprecated) */ \
> + .control_value = LE_CACHEABILITY(LE_PAGETABLE) | \
> + LE_TGT_CACHE(LE_TC_LLC) | \
> + LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | \
> + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
> + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), \
> + }, \
> + [2] = { \
> + /* Base - L3 + LLC */ \
> + .control_value = LE_CACHEABILITY(LE_WB) | \
> + LE_TGT_CACHE(LE_TC_LLC) | \
> + LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | \
> + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
> + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), \
> + }, \
> + [3] = { \
> + /* Base - Uncached */ \
> + .control_value = LE_CACHEABILITY(LE_UC) | \
> + LE_TGT_CACHE(LE_TC_LLC) | \
> + LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | \
> + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
> + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), \
> + }, \
> + [4] = { \
> + /* Base - L3 */ \
> + .control_value = LE_CACHEABILITY(LE_UC) | \
> + LE_TGT_CACHE(LE_TC_LLC) | \
> + LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | \
> + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
> + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), \
> + }, \
> + [5] = { \
> + /* Base - LLC */ \
> + .control_value = LE_CACHEABILITY(LE_WB) | \
> + LE_TGT_CACHE(LE_TC_LLC) | \
> + LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | \
> + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
> + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), \
> + }, \
> + [6] = { \
> + /* Age 0 - LLC */ \
> + .control_value = LE_CACHEABILITY(LE_WB) | \
> + LE_TGT_CACHE(LE_TC_LLC) | \
> + LE_LRUM(1) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | \
> + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
> + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), \
> + }, \
> + [7] = { \
> + /* Age 0 - L3 + LLC */ \
> + .control_value = LE_CACHEABILITY(LE_WB) | \
> + LE_TGT_CACHE(LE_TC_LLC) | \
> + LE_LRUM(1) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | \
> + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
> + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), \
> + }, \
> + [8] = { \
> + /* Age: Don't Chg. - LLC */ \
> + .control_value = LE_CACHEABILITY(LE_WB) | \
> + LE_TGT_CACHE(LE_TC_LLC) | \
> + LE_LRUM(2) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | \
> + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
> + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), \
> + }, \
> + [9] = { \
> + /* Age: Don't Chg. - L3 + LLC */ \
> + .control_value = LE_CACHEABILITY(LE_WB) | \
> + LE_TGT_CACHE(LE_TC_LLC) | \
> + LE_LRUM(2) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | \
> + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
> + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), \
> + }, \
> + [10] = { \
> + /* No AOM - LLC */ \
> + .control_value = LE_CACHEABILITY(LE_WB) | \
> + LE_TGT_CACHE(LE_TC_LLC) | \
> + LE_LRUM(3) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) | \
> + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
> + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), \
> + }, \
> + [11] = { \
> + /* No AOM - L3 + LLC */ \
> + .control_value = LE_CACHEABILITY(LE_WB) | \
> + LE_TGT_CACHE(LE_TC_LLC) | \
> + LE_LRUM(3) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) | \
> + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
> + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), \
> + }, \
> + [12] = { \
> + /* No AOM; Age 0 - LLC */ \
> + .control_value = LE_CACHEABILITY(LE_WB) | \
> + LE_TGT_CACHE(LE_TC_LLC) | \
> + LE_LRUM(1) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) | \
> + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
> + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), \
> + }, \
> + [13] = { \
> + /* No AOM; Age 0 - L3 + LLC */ \
> + .control_value = LE_CACHEABILITY(LE_WB) | \
> + LE_TGT_CACHE(LE_TC_LLC) | \
> + LE_LRUM(1) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) | \
> + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
> + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), \
> + }, \
> + [14] = { \
> + /* No AOM; Age:DC - LLC */ \
> + .control_value = LE_CACHEABILITY(LE_WB) | \
> + LE_TGT_CACHE(LE_TC_LLC) | \
> + LE_LRUM(2) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) | \
> + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
> + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), \
> + }, \
> + [15] = { \
> + /* No AOM; Age:DC - L3 + LLC */ \
> + .control_value = LE_CACHEABILITY(LE_WB) | \
> + LE_TGT_CACHE(LE_TC_LLC) | \
> + LE_LRUM(2) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) | \
> + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
> + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), \
> + }, \
> + [18] = { \
> + /* Self-Snoop - L3 + LLC */ \
> + .control_value = LE_CACHEABILITY(LE_WB) | \
> + LE_TGT_CACHE(LE_TC_LLC) | \
> + LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | \
> + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(3), \
> + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), \
> + }, \
> + [19] = { \
> + /* Skip Caching - L3 + LLC(12.5%) */ \
> + .control_value = LE_CACHEABILITY(LE_WB) | \
> + LE_TGT_CACHE(LE_TC_LLC) | \
> + LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(7) | \
> + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
> + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), \
> + }, \
> + [20] = { \
> + /* Skip Caching - L3 + LLC(25%) */ \
> + .control_value = LE_CACHEABILITY(LE_WB) | \
> + LE_TGT_CACHE(LE_TC_LLC) | \
> + LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(3) | \
> + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
> + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), \
> + }, \
> + [21] = { \
> + /* Skip Caching - L3 + LLC(50%) */ \
> + .control_value = LE_CACHEABILITY(LE_WB) | \
> + LE_TGT_CACHE(LE_TC_LLC) | \
> + LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(1) | \
> + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
> + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), \
> + }, \
> + [22] = { \
> + /* Skip Caching - L3 + LLC(75%) */ \
> + .control_value = LE_CACHEABILITY(LE_WB) | \
> + LE_TGT_CACHE(LE_TC_LLC) | \
> + LE_LRUM(3) | LE_AOM(0) | LE_RSC(1) | LE_SCC(3) | \
> + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
> + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), \
> + }, \
> + [23] = { \
> + /* Skip Caching - L3 + LLC(87.5%) */ \
> + .control_value = LE_CACHEABILITY(LE_WB) | \
> + LE_TGT_CACHE(LE_TC_LLC) | \
> + LE_LRUM(3) | LE_AOM(0) | LE_RSC(1) | LE_SCC(7) | \
> + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
> + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), \
> + }, \
> + [62] = { \
> + /* HW Reserved - SW program but never use */ \
> + .control_value = LE_CACHEABILITY(LE_WB) | \
> + LE_TGT_CACHE(LE_TC_LLC) | \
> + LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | \
> + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
> + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), \
> + }, \
> + [63] = { \
> + /* HW Reserved - SW program but never use */ \
> + .control_value = LE_CACHEABILITY(LE_WB) | \
> + LE_TGT_CACHE(LE_TC_LLC) | \
> + LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | \
> + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
> + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), \
> + },
> +
> +static const struct drm_i915_mocs_entry icelake_mocs_table[] = {
> + GEN11_MOCS_TABLE
> + [16] = {
> + /* Reserved - For future use */
> + .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
> + LE_TGT_CACHE(LE_TC_PAGETABLE) |
> + LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_DIRECT),
> + },
> + [17] = {
> + /* Reserved - For future use */
> + .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
> + LE_TGT_CACHE(LE_TC_PAGETABLE) |
> + LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_DIRECT),
> + },
> +};
> +
> /**
> * get_mocs_settings()
> * @dev_priv: i915 device.
> @@ -161,8 +379,11 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv,
> {
> bool result = false;
>
> - if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv) ||
> - IS_ICELAKE(dev_priv)) {
> + if (IS_ICELAKE(dev_priv)) {
> + table->size = ARRAY_SIZE(icelake_mocs_table);
> + table->table = icelake_mocs_table;
> + result = true;
> + } else if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
> table->size = ARRAY_SIZE(skylake_mocs_table);
> table->table = skylake_mocs_table;
> result = true;
>
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^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH v4 2/2] drm/i915/icl: Define MOCS table for Icelake
2018-11-05 13:50 ` [PATCH v4 2/2] drm/i915/icl: Define MOCS table for Icelake Tomasz Lis
2018-11-06 2:29 ` Daniele Ceraolo Spurio
@ 2018-11-06 10:47 ` Joonas Lahtinen
1 sibling, 0 replies; 8+ messages in thread
From: Joonas Lahtinen @ 2018-11-06 10:47 UTC (permalink / raw)
To: Tomasz Lis, intel-gfx
Cc: Adam Cetnerowski, Piotr Rozenfeld, Lucas De Marchi, Anuj Phogat,
Mika Kuoppala
Quoting Tomasz Lis (2018-11-05 15:50:21)
> +++ b/drivers/gpu/drm/i915/intel_mocs.c
> @@ -44,6 +44,8 @@ struct drm_i915_mocs_table {
> #define LE_SCC(value) ((value) << 8)
> #define LE_PFM(value) ((value) << 11)
> #define LE_SCF(value) ((value) << 14)
> +#define LE_CoS(value) ((value) << 15)
Any specific reason this is not LE_COS (vs. CoS)?
> +#define LE_SSE(value) ((value) << 17)
>
> /* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */
> #define L3_ESC(value) ((value) << 0)
> @@ -80,21 +82,21 @@ struct drm_i915_mocs_table {
> * LNCFCMOCS0 - LNCFCMOCS32 registers.
> *
> * These tables are intended to be kept reasonably consistent across
> - * platforms. However some of the fields are not applicable to all of
> - * them.
> + * HW platforms, and for ICL+, be identical across OSes. To achieve
> + * that, for Icelake and above, list of entries is published as part
> + * of bspec.
> *
> * Entries not part of the following tables are undefined as far as
> - * userspace is concerned and shouldn't be relied upon. For the time
> - * being they will be implicitly initialized to the strictest caching
> - * configuration (uncached) to guarantee forwards compatibility with
> - * userspace programs written against more recent kernels providing
> - * additional MOCS entries.
> + * userspace is concerned and shouldn't be relied upon.
> *
> - * NOTE: These tables MUST start with being uncached and the length
> - * MUST be less than 63 as the last two registers are reserved
> - * by the hardware. These tables are part of the kernel ABI and
> - * may only be updated incrementally by adding entries at the
> - * end.
> + * The last two entries are reserved by the hardware. For ICL+ they
> + * should be initialized according to bspec and never used, for older
> + * platforms they should never be written to.
> + *
> + * NOTE: These tables are part of bspec and defined as part of hardware
> + * interface for ICL+. For older platforms, they are part of kernel
> + * ABI. It is expected that existing entries will remain constant
> + * and the tables will only be updated by adding new entries.
> */
>
> #define GEN9_MOCS_TABLE \
> @@ -144,6 +146,222 @@ static const struct drm_i915_mocs_entry broxton_mocs_table[] = {
> },
> };
>
> +#define GEN11_MOCS_TABLE \
#define GEN11_MOCS_ENTRIES would be more truthful, and same applies for
GEN9, of course.
> + [0] = { \
> + /* Base - Uncached (Deprecated) */ \
> + .control_value = LE_CACHEABILITY(LE_UC) | \
> + LE_TGT_CACHE(LE_TC_LLC) | \
> + LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | \
> + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
> + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), \
> + }, \
My wild assumption would be that these don't please checkpatch.
Maybe worthy fixing the indent while converting the GEN9 to defines,
too?
> + [1] = { \
> + /* Base - L3 + LeCC:PAT (Deprecated) */ \
> + .control_value = LE_CACHEABILITY(LE_PAGETABLE) | \
> + LE_TGT_CACHE(LE_TC_LLC) | \
> + LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | \
> + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
> + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), \
If these are coming off a table, would it make sense to have a dedicated
#define to make them more table-like for easier review?
.control_value = MOCS_CONTROL_VALUE(0, 0, 0, 0, 0, 0, 0, 0),
Regards, Joonas
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [v4,1/2] drm/i915/skl: Rework MOCS tables to keep common part in a define
2018-11-05 13:50 [PATCH v4 1/2] drm/i915/skl: Rework MOCS tables to keep common part in a define Tomasz Lis
2018-11-05 13:50 ` [PATCH v4 2/2] drm/i915/icl: Define MOCS table for Icelake Tomasz Lis
@ 2018-11-05 14:16 ` Patchwork
2018-11-05 15:30 ` ✓ Fi.CI.IGT: " Patchwork
2 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2018-11-05 14:16 UTC (permalink / raw)
To: Tomasz Lis; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v4,1/2] drm/i915/skl: Rework MOCS tables to keep common part in a define
URL : https://patchwork.freedesktop.org/series/52027/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5085 -> Patchwork_10725 =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_10725 need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_10725, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/52027/revisions/1/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_10725:
=== IGT changes ===
==== Warnings ====
igt@drv_selftest@live_guc:
fi-skl-iommu: PASS -> SKIP +1
== Known issues ==
Here are the changes found in Patchwork_10725 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@drv_selftest@live_hangcheck:
fi-skl-iommu: PASS -> INCOMPLETE (fdo#108602)
igt@gem_exec_suspend@basic-s3:
fi-kbl-soraka: NOTRUN -> INCOMPLETE (fdo#107556, fdo#107774, fdo#107859)
igt@kms_chamelium@dp-edid-read:
fi-kbl-7500u: PASS -> WARN (fdo#102672)
igt@kms_frontbuffer_tracking@basic:
fi-byt-clapper: PASS -> FAIL (fdo#103167)
igt@kms_pipe_crc_basic@hang-read-crc-pipe-a:
fi-skl-guc: PASS -> FAIL (fdo#103191, fdo#107362)
igt@kms_pipe_crc_basic@read-crc-pipe-a:
fi-byt-clapper: PASS -> FAIL (fdo#107362)
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
fi-blb-e6850: PASS -> INCOMPLETE (fdo#107718)
==== Possible fixes ====
igt@gem_cpu_reloc@basic:
fi-skl-6700hq: INCOMPLETE (fdo#108011) -> PASS
igt@gem_exec_suspend@basic-s3:
fi-glk-dsi: FAIL (fdo#103375) -> PASS
igt@kms_frontbuffer_tracking@basic:
fi-hsw-peppy: DMESG-WARN (fdo#102614) -> PASS
igt@kms_pipe_crc_basic@read-crc-pipe-b-frame-sequence:
fi-byt-clapper: FAIL (fdo#103191, fdo#107362) -> PASS
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
fdo#102672 https://bugs.freedesktop.org/show_bug.cgi?id=102672
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
fdo#107556 https://bugs.freedesktop.org/show_bug.cgi?id=107556
fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718
fdo#107774 https://bugs.freedesktop.org/show_bug.cgi?id=107774
fdo#107859 https://bugs.freedesktop.org/show_bug.cgi?id=107859
fdo#108011 https://bugs.freedesktop.org/show_bug.cgi?id=108011
fdo#108602 https://bugs.freedesktop.org/show_bug.cgi?id=108602
== Participating hosts (45 -> 45) ==
Additional (7): fi-kbl-soraka fi-bwr-2160 fi-ilk-650 fi-snb-2520m fi-gdg-551 fi-pnv-d510 fi-kbl-7560u
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-kbl-8809g fi-icl-u
== Build changes ==
* Linux: CI_DRM_5085 -> Patchwork_10725
CI_DRM_5085: 6ae61ee5db4af12c0b21bf39e0400ccf024187c4 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4706: 5421c73a7db3cfaa85ab24325fe6e898cbb27fb3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10725: 11eb04f01462fe2fb31600ef3d3fd1df261fd182 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
11eb04f01462 drm/i915/icl: Define MOCS table for Icelake
0e81c0cb8af6 drm/i915/skl: Rework MOCS tables to keep common part in a define
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10725/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread* ✓ Fi.CI.IGT: success for series starting with [v4,1/2] drm/i915/skl: Rework MOCS tables to keep common part in a define
2018-11-05 13:50 [PATCH v4 1/2] drm/i915/skl: Rework MOCS tables to keep common part in a define Tomasz Lis
2018-11-05 13:50 ` [PATCH v4 2/2] drm/i915/icl: Define MOCS table for Icelake Tomasz Lis
2018-11-05 14:16 ` ✓ Fi.CI.BAT: success for series starting with [v4,1/2] drm/i915/skl: Rework MOCS tables to keep common part in a define Patchwork
@ 2018-11-05 15:30 ` Patchwork
2 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2018-11-05 15:30 UTC (permalink / raw)
To: Tomasz Lis; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v4,1/2] drm/i915/skl: Rework MOCS tables to keep common part in a define
URL : https://patchwork.freedesktop.org/series/52027/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5085_full -> Patchwork_10725_full =
== Summary - SUCCESS ==
No regressions found.
== Known issues ==
Here are the changes found in Patchwork_10725_full that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@drv_suspend@shrink:
shard-snb: PASS -> INCOMPLETE (fdo#105411, fdo#106886)
shard-skl: PASS -> INCOMPLETE (fdo#106886)
igt@gem_exec_schedule@pi-ringfull-render:
shard-skl: NOTRUN -> FAIL (fdo#103158)
igt@kms_busy@extended-modeset-hang-newfb-render-a:
shard-skl: NOTRUN -> DMESG-WARN (fdo#107956) +3
igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
shard-kbl: PASS -> DMESG-WARN (fdo#107956)
igt@kms_busy@extended-pageflip-hang-newfb-render-a:
shard-apl: PASS -> DMESG-WARN (fdo#107956)
igt@kms_chv_cursor_fail@pipe-c-256x256-top-edge:
shard-skl: PASS -> FAIL (fdo#104671)
igt@kms_cursor_crc@cursor-256x256-dpms:
shard-glk: PASS -> FAIL (fdo#103232) +3
igt@kms_cursor_crc@cursor-256x256-random:
shard-apl: PASS -> FAIL (fdo#103232)
igt@kms_cursor_crc@cursor-64x64-suspend:
shard-apl: PASS -> FAIL (fdo#103191, fdo#103232)
igt@kms_cursor_legacy@cursorb-vs-flipb-toggle:
shard-glk: PASS -> DMESG-WARN (fdo#105763, fdo#106538)
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-wc:
shard-glk: PASS -> FAIL (fdo#103167) +1
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu:
shard-apl: PASS -> FAIL (fdo#103167)
igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
shard-skl: NOTRUN -> FAIL (fdo#108145) +4
igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
shard-skl: PASS -> FAIL (fdo#107815)
igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
shard-glk: PASS -> FAIL (fdo#103166) +4
igt@kms_plane_multiple@atomic-pipe-c-tiling-yf:
shard-apl: PASS -> FAIL (fdo#103166) +3
igt@kms_properties@connector-properties-atomic:
shard-skl: NOTRUN -> FAIL (fdo#108642)
igt@kms_setmode@basic:
shard-skl: NOTRUN -> FAIL (fdo#99912)
shard-kbl: PASS -> FAIL (fdo#99912)
==== Possible fixes ====
igt@kms_cursor_crc@cursor-128x42-onscreen:
shard-glk: FAIL (fdo#103232) -> PASS +1
igt@kms_cursor_crc@cursor-64x21-onscreen:
shard-apl: FAIL (fdo#103232) -> PASS
igt@kms_cursor_crc@cursor-64x64-offscreen:
shard-skl: FAIL (fdo#103232) -> PASS +1
igt@kms_draw_crc@draw-method-xrgb2101010-pwrite-ytiled:
shard-skl: FAIL (fdo#103184) -> PASS
igt@kms_draw_crc@draw-method-xrgb8888-pwrite-untiled:
shard-skl: FAIL (fdo#108472) -> PASS
igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-cpu:
shard-skl: FAIL (fdo#105682) -> PASS
igt@kms_frontbuffer_tracking@fbc-1p-rte:
shard-glk: FAIL (fdo#105682, fdo#103167) -> PASS
igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff:
shard-glk: FAIL (fdo#103167) -> PASS +5
igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-wc:
shard-skl: FAIL (fdo#105682, fdo#103167) -> PASS
igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
shard-skl: FAIL (fdo#108145, fdo#107815) -> PASS
igt@kms_plane_multiple@atomic-pipe-a-tiling-x:
shard-apl: FAIL (fdo#103166) -> PASS +3
shard-glk: FAIL (fdo#103166) -> PASS
igt@perf@oa-exponents:
shard-glk: FAIL (fdo#105483) -> PASS
igt@prime_vgem@basic-fence-flip:
shard-apl: FAIL (fdo#104008) -> PASS
fdo#103158 https://bugs.freedesktop.org/show_bug.cgi?id=103158
fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103184 https://bugs.freedesktop.org/show_bug.cgi?id=103184
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232
fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008
fdo#104671 https://bugs.freedesktop.org/show_bug.cgi?id=104671
fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411
fdo#105483 https://bugs.freedesktop.org/show_bug.cgi?id=105483
fdo#105682 https://bugs.freedesktop.org/show_bug.cgi?id=105682
fdo#105763 https://bugs.freedesktop.org/show_bug.cgi?id=105763
fdo#106538 https://bugs.freedesktop.org/show_bug.cgi?id=106538
fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886
fdo#107815 https://bugs.freedesktop.org/show_bug.cgi?id=107815
fdo#107956 https://bugs.freedesktop.org/show_bug.cgi?id=107956
fdo#108145 https://bugs.freedesktop.org/show_bug.cgi?id=108145
fdo#108472 https://bugs.freedesktop.org/show_bug.cgi?id=108472
fdo#108642 https://bugs.freedesktop.org/show_bug.cgi?id=108642
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
== Participating hosts (6 -> 6) ==
No changes in participating hosts
== Build changes ==
* Linux: CI_DRM_5085 -> Patchwork_10725
CI_DRM_5085: 6ae61ee5db4af12c0b21bf39e0400ccf024187c4 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4706: 5421c73a7db3cfaa85ab24325fe6e898cbb27fb3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10725: 11eb04f01462fe2fb31600ef3d3fd1df261fd182 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10725/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v1] drm/i915/icl: Define MOCS table for Icelake
@ 2018-10-19 15:19 Tomasz Lis
2018-10-26 15:32 ` [PATCH v4 1/2] drm/i915/skl: Rework MOCS tables to keep common part in a define Tomasz Lis
0 siblings, 1 reply; 8+ messages in thread
From: Tomasz Lis @ 2018-10-19 15:19 UTC (permalink / raw)
To: intel-gfx; +Cc: Mika Kuoppala
The table has been unified across OSes to minimize virtualization overhead.
The MOCS table is now versioned; the patch includes version 1 entries.
BSpec: 34007
BSpec: 560
Signed-off-by: Tomasz Lis <tomasz.lis@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
---
drivers/gpu/drm/i915/intel_mocs.c | 246 +++++++++++++++++++++++++++++++++++++-
1 file changed, 244 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
index 77e9871..b76d6db 100644
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -44,6 +44,8 @@ struct drm_i915_mocs_table {
#define LE_SCC(value) ((value) << 8)
#define LE_PFM(value) ((value) << 11)
#define LE_SCF(value) ((value) << 14)
+#define LE_CoS(value) ((value) << 15)
+#define LE_SSE(value) ((value) << 17)
/* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */
#define L3_ESC(value) ((value) << 0)
@@ -96,6 +98,243 @@ struct drm_i915_mocs_table {
* may only be updated incrementally by adding entries at the
* end.
*/
+static const struct drm_i915_mocs_entry icelake_mocs_table[] = {
+ [0] = {
+ /* Base - Uncached (Deprecated) */
+ .control_value = LE_CACHEABILITY(LE_UC) |
+ LE_TGT_CACHE(LE_TC_LLC) |
+ LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+ LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+ .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
+ },
+ [1] = {
+ /* Base - L3 + LeCC:PAT (Deprecated) */
+ .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
+ LE_TGT_CACHE(LE_TC_LLC) |
+ LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+ LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+ .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+ },
+ [2] = {
+ /* Base - L3 + LLC */
+ .control_value = LE_CACHEABILITY(LE_WB) |
+ LE_TGT_CACHE(LE_TC_LLC) |
+ LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+ LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+ .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+ },
+ [3] = {
+ /* Base - Uncached */
+ .control_value = LE_CACHEABILITY(LE_UC) |
+ LE_TGT_CACHE(LE_TC_LLC) |
+ LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+ LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+ .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
+ },
+ [4] = {
+ /* Base - L3 */
+ .control_value = LE_CACHEABILITY(LE_UC) |
+ LE_TGT_CACHE(LE_TC_LLC) |
+ LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+ LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+ .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+ },
+ [5] = {
+ /* Base - LLC */
+ .control_value = LE_CACHEABILITY(LE_WB) |
+ LE_TGT_CACHE(LE_TC_LLC) |
+ LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+ LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+ .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
+ },
+ [6] = {
+ /* Age 0 - LLC */
+ .control_value = LE_CACHEABILITY(LE_WB) |
+ LE_TGT_CACHE(LE_TC_LLC) |
+ LE_LRUM(1) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+ LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+ .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
+ },
+ [7] = {
+ /* Age 0 - L3 + LLC */
+ .control_value = LE_CACHEABILITY(LE_WB) |
+ LE_TGT_CACHE(LE_TC_LLC) |
+ LE_LRUM(1) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+ LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+ .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+ },
+ [8] = {
+ /* Age: Don't Chg. - LLC */
+ .control_value = LE_CACHEABILITY(LE_WB) |
+ LE_TGT_CACHE(LE_TC_LLC) |
+ LE_LRUM(2) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+ LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+ .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
+ },
+ [9] = {
+ /* Age: Don't Chg. - L3 + LLC */
+ .control_value = LE_CACHEABILITY(LE_WB) |
+ LE_TGT_CACHE(LE_TC_LLC) |
+ LE_LRUM(2) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+ LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+ .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+ },
+ [10] = {
+ /* No AOM - LLC */
+ .control_value = LE_CACHEABILITY(LE_WB) |
+ LE_TGT_CACHE(LE_TC_LLC) |
+ LE_LRUM(3) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) |
+ LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+ .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
+ },
+ [11] = {
+ /* No AOM - L3 + LLC */
+ .control_value = LE_CACHEABILITY(LE_WB) |
+ LE_TGT_CACHE(LE_TC_LLC) |
+ LE_LRUM(3) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) |
+ LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+ .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+ },
+ [12] = {
+ /* No AOM; Age 0 - LLC */
+ .control_value = LE_CACHEABILITY(LE_WB) |
+ LE_TGT_CACHE(LE_TC_LLC) |
+ LE_LRUM(1) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) |
+ LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+ .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
+ },
+ [13] = {
+ /* No AOM; Age 0 - L3 + LLC */
+ .control_value = LE_CACHEABILITY(LE_WB) |
+ LE_TGT_CACHE(LE_TC_LLC) |
+ LE_LRUM(1) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) |
+ LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+ .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+ },
+ [14] = {
+ /* No AOM; Age:DC - LLC */
+ .control_value = LE_CACHEABILITY(LE_WB) |
+ LE_TGT_CACHE(LE_TC_LLC) |
+ LE_LRUM(2) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) |
+ LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+ .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
+ },
+ [15] = {
+ /* No AOM; Age:DC - L3 + LLC */
+ .control_value = LE_CACHEABILITY(LE_WB) |
+ LE_TGT_CACHE(LE_TC_LLC) |
+ LE_LRUM(2) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) |
+ LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+ .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+ },
+ [16] = {
+ /* Reserved - For future use */
+ .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
+ LE_TGT_CACHE(LE_TC_PAGETABLE) |
+ LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+ LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+ .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_DIRECT),
+ },
+ [17] = {
+ /* Reserved - For future use */
+ .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
+ LE_TGT_CACHE(LE_TC_PAGETABLE) |
+ LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+ LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+ .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_DIRECT),
+ },
+ [18] = {
+ /* Self-Snoop - L3 + LLC */
+ .control_value = LE_CACHEABILITY(LE_WB) |
+ LE_TGT_CACHE(LE_TC_LLC) |
+ LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+ LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(3),
+
+ .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+ },
+ [19] = {
+ /* Skip Caching - L3 + LLC(12.5%) */
+ .control_value = LE_CACHEABILITY(LE_WB) |
+ LE_TGT_CACHE(LE_TC_LLC) |
+ LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+ LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+ .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+ },
+ [20] = {
+ /* Skip Caching - L3 + LLC(25%) */
+ .control_value = LE_CACHEABILITY(LE_WB) |
+ LE_TGT_CACHE(LE_TC_LLC) |
+ LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+ LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+ .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+ },
+ [21] = {
+ /* Skip Caching - L3 + LLC(50%) */
+ .control_value = LE_CACHEABILITY(LE_WB) |
+ LE_TGT_CACHE(LE_TC_LLC) |
+ LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+ LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+ .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+ },
+ [22] = {
+ /* Skip Caching - L3 + LLC(75%) */
+ .control_value = LE_CACHEABILITY(LE_WB) |
+ LE_TGT_CACHE(LE_TC_LLC) |
+ LE_LRUM(3) | LE_AOM(0) | LE_RSC(1) | LE_SCC(0) |
+ LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+ .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+ },
+ [23] = {
+ /* Skip Caching - L3 + LLC(87.5%) */
+ .control_value = LE_CACHEABILITY(LE_WB) |
+ LE_TGT_CACHE(LE_TC_LLC) |
+ LE_LRUM(3) | LE_AOM(0) | LE_RSC(1) | LE_SCC(0) |
+ LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+ .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+ },
+ [62] = {
+ /* HW Reserved - SW program but never use */
+ .control_value = LE_CACHEABILITY(LE_WB) |
+ LE_TGT_CACHE(LE_TC_LLC) |
+ LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+ LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+ .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
+ },
+ [63] = {
+ /* HW Reserved - SW program but never use */
+ .control_value = LE_CACHEABILITY(LE_WB) |
+ LE_TGT_CACHE(LE_TC_LLC) |
+ LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+ LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+ .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
+ },
+};
+
static const struct drm_i915_mocs_entry skylake_mocs_table[] = {
[I915_MOCS_UNCACHED] = {
/* 0x00000009 */
@@ -178,8 +417,11 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv,
{
bool result = false;
- if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv) ||
- IS_ICELAKE(dev_priv)) {
+ if (IS_ICELAKE(dev_priv)) {
+ table->size = ARRAY_SIZE(icelake_mocs_table);
+ table->table = icelake_mocs_table;
+ result = true;
+ } else if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
table->size = ARRAY_SIZE(skylake_mocs_table);
table->table = skylake_mocs_table;
result = true;
--
2.7.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v4 1/2] drm/i915/skl: Rework MOCS tables to keep common part in a define
2018-10-19 15:19 [PATCH v1] drm/i915/icl: Define MOCS table for Icelake Tomasz Lis
@ 2018-10-26 15:32 ` Tomasz Lis
2018-10-26 16:42 ` Lucas De Marchi
0 siblings, 1 reply; 8+ messages in thread
From: Tomasz Lis @ 2018-10-26 15:32 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
The MOCS tables are going to be very similar across platforms.
To reduce the amount of copied code, this patch rips the common part and
puts it into a definition valid for all gen9 platforms.
Signed-off-by: Tomasz Lis <tomasz.lis@intel.com>
Suggested-by: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/intel_mocs.c | 61 ++++++++++++++-------------------------
1 file changed, 22 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
index 77e9871..76aed59 100644
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -96,26 +96,29 @@ struct drm_i915_mocs_table {
* may only be updated incrementally by adding entries at the
* end.
*/
-static const struct drm_i915_mocs_entry skylake_mocs_table[] = {
- [I915_MOCS_UNCACHED] = {
- /* 0x00000009 */
- .control_value = LE_CACHEABILITY(LE_UC) |
- LE_TGT_CACHE(LE_TC_LLC_ELLC) |
- LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
- LE_PFM(0) | LE_SCF(0),
- /* 0x0010 */
- .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
- },
- [I915_MOCS_PTE] = {
- /* 0x00000038 */
- .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
- LE_TGT_CACHE(LE_TC_LLC_ELLC) |
- LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
- LE_PFM(0) | LE_SCF(0),
- /* 0x0030 */
- .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+#define GEN9_MOCS_TABLE \
+ [I915_MOCS_UNCACHED] = { \
+ /* 0x00000009 */ \
+ .control_value = LE_CACHEABILITY(LE_UC) | \
+ LE_TGT_CACHE(LE_TC_LLC_ELLC) | \
+ LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | \
+ LE_PFM(0) | LE_SCF(0), \
+ /* 0x0010 */ \
+ .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), \
+ }, \
+ [I915_MOCS_PTE] = { \
+ /* 0x00000038 */ \
+ .control_value = LE_CACHEABILITY(LE_PAGETABLE) | \
+ LE_TGT_CACHE(LE_TC_LLC_ELLC) | \
+ LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | \
+ LE_PFM(0) | LE_SCF(0), \
+ /* 0x0030 */ \
+ .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), \
},
+
+static const struct drm_i915_mocs_entry skylake_mocs_table[] = {
+ GEN9_MOCS_TABLE
[I915_MOCS_CACHED] = {
/* 0x0000003b */
.control_value = LE_CACHEABILITY(LE_WB) |
@@ -129,33 +132,13 @@ static const struct drm_i915_mocs_entry skylake_mocs_table[] = {
/* NOTE: the LE_TGT_CACHE is not used on Broxton */
static const struct drm_i915_mocs_entry broxton_mocs_table[] = {
- [I915_MOCS_UNCACHED] = {
- /* 0x00000009 */
- .control_value = LE_CACHEABILITY(LE_UC) |
- LE_TGT_CACHE(LE_TC_LLC_ELLC) |
- LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
- LE_PFM(0) | LE_SCF(0),
-
- /* 0x0010 */
- .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
- },
- [I915_MOCS_PTE] = {
- /* 0x00000038 */
- .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
- LE_TGT_CACHE(LE_TC_LLC_ELLC) |
- LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
- LE_PFM(0) | LE_SCF(0),
-
- /* 0x0030 */
- .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
- },
+ GEN9_MOCS_TABLE
[I915_MOCS_CACHED] = {
/* 0x00000039 */
.control_value = LE_CACHEABILITY(LE_UC) |
LE_TGT_CACHE(LE_TC_LLC_ELLC) |
LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
LE_PFM(0) | LE_SCF(0),
-
/* 0x0030 */
.l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
},
--
2.7.4
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v4 1/2] drm/i915/skl: Rework MOCS tables to keep common part in a define
2018-10-26 15:32 ` [PATCH v4 1/2] drm/i915/skl: Rework MOCS tables to keep common part in a define Tomasz Lis
@ 2018-10-26 16:42 ` Lucas De Marchi
0 siblings, 0 replies; 8+ messages in thread
From: Lucas De Marchi @ 2018-10-26 16:42 UTC (permalink / raw)
To: Tomasz Lis; +Cc: intel-gfx
On Fri, Oct 26, 2018 at 05:32:45PM +0200, Tomasz Lis wrote:
> The MOCS tables are going to be very similar across platforms.
>
> To reduce the amount of copied code, this patch rips the common part and
> puts it into a definition valid for all gen9 platforms.
>
> Signed-off-by: Tomasz Lis <tomasz.lis@intel.com>
> Suggested-by: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
yeah, this is what I was suggesting.
Not sure if in future this will blow out of proportion - we need to remember that each
table is 64 entries of this struct in the ro section. If this happens, then maybe we
will need to change the approach and move the idx inside the entry rather than 64-entry
arrays. I think this can be left for later if/when there's need.
Right now this improves the status quo IMO.
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
thanks
Lucas De Marchi
> ---
> drivers/gpu/drm/i915/intel_mocs.c | 61 ++++++++++++++-------------------------
> 1 file changed, 22 insertions(+), 39 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
> index 77e9871..76aed59 100644
> --- a/drivers/gpu/drm/i915/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/intel_mocs.c
> @@ -96,26 +96,29 @@ struct drm_i915_mocs_table {
> * may only be updated incrementally by adding entries at the
> * end.
> */
> -static const struct drm_i915_mocs_entry skylake_mocs_table[] = {
> - [I915_MOCS_UNCACHED] = {
> - /* 0x00000009 */
> - .control_value = LE_CACHEABILITY(LE_UC) |
> - LE_TGT_CACHE(LE_TC_LLC_ELLC) |
> - LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> - LE_PFM(0) | LE_SCF(0),
>
> - /* 0x0010 */
> - .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
> - },
> - [I915_MOCS_PTE] = {
> - /* 0x00000038 */
> - .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
> - LE_TGT_CACHE(LE_TC_LLC_ELLC) |
> - LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> - LE_PFM(0) | LE_SCF(0),
> - /* 0x0030 */
> - .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
> +#define GEN9_MOCS_TABLE \
> + [I915_MOCS_UNCACHED] = { \
> + /* 0x00000009 */ \
> + .control_value = LE_CACHEABILITY(LE_UC) | \
> + LE_TGT_CACHE(LE_TC_LLC_ELLC) | \
> + LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | \
> + LE_PFM(0) | LE_SCF(0), \
> + /* 0x0010 */ \
> + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), \
> + }, \
> + [I915_MOCS_PTE] = { \
> + /* 0x00000038 */ \
> + .control_value = LE_CACHEABILITY(LE_PAGETABLE) | \
> + LE_TGT_CACHE(LE_TC_LLC_ELLC) | \
> + LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | \
> + LE_PFM(0) | LE_SCF(0), \
> + /* 0x0030 */ \
> + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), \
> },
> +
> +static const struct drm_i915_mocs_entry skylake_mocs_table[] = {
> + GEN9_MOCS_TABLE
> [I915_MOCS_CACHED] = {
> /* 0x0000003b */
> .control_value = LE_CACHEABILITY(LE_WB) |
> @@ -129,33 +132,13 @@ static const struct drm_i915_mocs_entry skylake_mocs_table[] = {
>
> /* NOTE: the LE_TGT_CACHE is not used on Broxton */
> static const struct drm_i915_mocs_entry broxton_mocs_table[] = {
> - [I915_MOCS_UNCACHED] = {
> - /* 0x00000009 */
> - .control_value = LE_CACHEABILITY(LE_UC) |
> - LE_TGT_CACHE(LE_TC_LLC_ELLC) |
> - LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> - LE_PFM(0) | LE_SCF(0),
> -
> - /* 0x0010 */
> - .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
> - },
> - [I915_MOCS_PTE] = {
> - /* 0x00000038 */
> - .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
> - LE_TGT_CACHE(LE_TC_LLC_ELLC) |
> - LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> - LE_PFM(0) | LE_SCF(0),
> -
> - /* 0x0030 */
> - .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
> - },
> + GEN9_MOCS_TABLE
> [I915_MOCS_CACHED] = {
> /* 0x00000039 */
> .control_value = LE_CACHEABILITY(LE_UC) |
> LE_TGT_CACHE(LE_TC_LLC_ELLC) |
> LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> LE_PFM(0) | LE_SCF(0),
> -
> /* 0x0030 */
> .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
> },
> --
> 2.7.4
>
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^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2018-11-06 10:47 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
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2018-11-05 13:50 [PATCH v4 1/2] drm/i915/skl: Rework MOCS tables to keep common part in a define Tomasz Lis
2018-11-05 13:50 ` [PATCH v4 2/2] drm/i915/icl: Define MOCS table for Icelake Tomasz Lis
2018-11-06 2:29 ` Daniele Ceraolo Spurio
2018-11-06 10:47 ` Joonas Lahtinen
2018-11-05 14:16 ` ✓ Fi.CI.BAT: success for series starting with [v4,1/2] drm/i915/skl: Rework MOCS tables to keep common part in a define Patchwork
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2018-10-19 15:19 [PATCH v1] drm/i915/icl: Define MOCS table for Icelake Tomasz Lis
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