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From: Xiaolin Zhang <xiaolin.zhang@intel.com>
To: intel-gvt-dev@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
Cc: chris@chris-wilson.co.uk, zhiyuan.lv@intel.com
Subject: [Intel-gfx] [PATCH v1 07/12] drm/i915/gvt: GVTg expose pv_caps PVINFO register
Date: Sat,  5 Sep 2020 00:21:40 +0800	[thread overview]
Message-ID: <1599236505-9086-8-git-send-email-xiaolin.zhang@intel.com> (raw)
In-Reply-To: <1599236505-9086-1-git-send-email-xiaolin.zhang@intel.com>

expose pv_caps PVINFO register from GVTg to guest in order that guest can
query and control different pv capability support.

report VGT_CAPS_PV capability in pvinfo page for guest.

Signed-off-by: Xiaolin Zhang <xiaolin.zhang@intel.com>
---
 drivers/gpu/drm/i915/gvt/gvt.h      | 8 ++++++++
 drivers/gpu/drm/i915/gvt/handlers.c | 5 +++++
 drivers/gpu/drm/i915/gvt/vgpu.c     | 1 +
 3 files changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
index 9831361..31d8a2bcc 100644
--- a/drivers/gpu/drm/i915/gvt/gvt.h
+++ b/drivers/gpu/drm/i915/gvt/gvt.h
@@ -49,6 +49,7 @@
 #include "fb_decoder.h"
 #include "dmabuf.h"
 #include "page_track.h"
+#include "i915_vgpu.h"
 
 #define GVT_MAX_VGPU 8
 
@@ -212,6 +213,7 @@ struct intel_vgpu {
 	struct idr object_idr;
 
 	u32 scan_nonprivbb;
+	u32 pv_caps;
 };
 
 static inline void *intel_vgpu_vdev(struct intel_vgpu *vgpu)
@@ -531,6 +533,12 @@ static inline u64 intel_vgpu_get_bar_gpa(struct intel_vgpu *vgpu, int bar)
 			PCI_BASE_ADDRESS_MEM_MASK;
 }
 
+static inline bool intel_vgpu_enabled_pv_cap(struct intel_vgpu *vgpu,
+		enum pv_caps cap)
+{
+	return (vgpu->pv_caps & cap);
+}
+
 void intel_vgpu_clean_opregion(struct intel_vgpu *vgpu);
 int intel_vgpu_init_opregion(struct intel_vgpu *vgpu);
 int intel_vgpu_opregion_base_write_handler(struct intel_vgpu *vgpu, u32 gpa);
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index ee3648d..bfea065 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -1203,6 +1203,7 @@ static int pvinfo_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
 		break;
 	case 0x78010:	/* vgt_caps */
 	case 0x7881c:
+	case _vgtif_reg(pv_caps):
 		break;
 	default:
 		invalid_read = true;
@@ -1272,6 +1273,10 @@ static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
 	case _vgtif_reg(g2v_notify):
 		handle_g2v_notification(vgpu, data);
 		break;
+	case _vgtif_reg(pv_caps):
+		DRM_INFO("vgpu id=%d pv caps =0x%x\n", vgpu->id, data);
+		vgpu->pv_caps = data;
+		break;
 	/* add xhot and yhot to handled list to avoid error log */
 	case _vgtif_reg(cursor_x_hot):
 	case _vgtif_reg(cursor_y_hot):
diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
index 8fa9b31..4867426 100644
--- a/drivers/gpu/drm/i915/gvt/vgpu.c
+++ b/drivers/gpu/drm/i915/gvt/vgpu.c
@@ -48,6 +48,7 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu)
 	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_PPGTT;
 	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HWSP_EMULATION;
 	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HUGE_GTT;
+	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_PV;
 
 	vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) =
 		vgpu_aperture_gmadr_base(vgpu);
-- 
2.7.4

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  parent reply	other threads:[~2020-09-07  0:55 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-04 16:21 [Intel-gfx] [PATCH v1 00/12] enhanced i915 vgpu with PV feature support Xiaolin Zhang
2020-09-04 16:21 ` [Intel-gfx] [PATCH v1 01/12] drm/i915: introduced vgpu pv capability Xiaolin Zhang
2020-09-10 13:10   ` Jani Nikula
2020-09-21  5:37     ` Zhang, Xiaolin
2020-09-10 13:10   ` Jani Nikula
2020-09-21  5:24     ` Zhang, Xiaolin
2020-09-04 16:21 ` [Intel-gfx] [PATCH v1 02/12] drm/i915: vgpu shared memory setup for pv support Xiaolin Zhang
2020-09-10 13:16   ` Jani Nikula
2020-09-21  5:27     ` Zhang, Xiaolin
2020-09-04 16:21 ` [Intel-gfx] [PATCH v1 03/12] drm/i915: vgpu pv command buffer transport protocol Xiaolin Zhang
2020-09-10 13:20   ` Jani Nikula
2020-09-21  5:33     ` Zhang, Xiaolin
2020-09-04 16:21 ` [Intel-gfx] [PATCH v1 04/12] drm/i915: vgpu ppgtt page table pv support Xiaolin Zhang
2020-09-04 16:21 ` [Intel-gfx] [PATCH v1 05/12] drm/i915: vgpu ggtt " Xiaolin Zhang
2020-09-04 16:21 ` [Intel-gfx] [PATCH v1 06/12] drm/i915: vgpu workload submisison " Xiaolin Zhang
2020-09-04 16:21 ` Xiaolin Zhang [this message]
2020-09-04 16:21 ` [Intel-gfx] [PATCH v1 08/12] drm/i915/gvt: GVTg handle guest shared_page setup Xiaolin Zhang
2020-09-04 16:21 ` [Intel-gfx] [PATCH v1 09/12] drm/i915/gvt: GVTg support vgpu pv CTB protocol Xiaolin Zhang
2020-09-04 16:21 ` [Intel-gfx] [PATCH v1 10/12] drm/i915/gvt: GVTg support ppgtt pv operations Xiaolin Zhang
2020-09-04 16:21 ` [Intel-gfx] [PATCH v1 11/12] drm/i915/gvt: GVTg support ggtt " Xiaolin Zhang
2020-09-04 16:21 ` [Intel-gfx] [PATCH v1 12/12] drm/i915/gvt: GVTg support pv workload submssion Xiaolin Zhang
2020-09-07  1:12 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for enhanced i915 vgpu with PV feature support Patchwork
2020-09-07  1:13 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-09-07  1:15 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2020-09-07  1:29 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-09-07  7:24 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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