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From: "Thomas Hellström" <thomas.hellstrom@linux.intel.com>
To: Matthew Auld <matthew.auld@intel.com>,
	Joonas Lahtinen <joonas.lahtinen@linux.intel.com>,
	"Bloomfield, Jon" <jon.bloomfield@intel.com>,
	Intel Graphics Development <intel-gfx@lists.freedesktop.org>,
	Ramalingam C <ramalingam.c@intel.com>
Subject: [Intel-gfx] Small bar recovery vs compressed content on DG2
Date: Wed, 16 Mar 2022 08:25:16 +0100	[thread overview]
Message-ID: <162c1566-87c6-072f-d340-1693f6a71aea@linux.intel.com> (raw)

Hi!

Do we somehow need to clarify in the headers the semantics for this?

 From my understanding when discussing the CCS migration series with 
Ram, the kernel will never do any resolving (compressing / 
decompressing) migrations or evictions which basically implies the 
following:

*) Compressed data must have LMEM only placement, otherwise the GPU 
would read garbage if accessing from SMEM.
*) Compressed data can't be assumed to be mappable by the CPU, because 
in order to ensure that on small BAR, the placement needs to be LMEM+SMEM.
*) Neither can compressed data be part of a CAPTURE buffer, because that 
requires the data to be CPU-mappable.

Are we (and user-mode drivers) OK with these restrictions, or do we need 
to rethink?

Thanks,

Thomas



             reply	other threads:[~2022-03-16  7:25 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-03-16  7:25 Thomas Hellström [this message]
2022-03-17  8:43 ` [Intel-gfx] Small bar recovery vs compressed content on DG2 Joonas Lahtinen
2022-03-17  9:29   ` Matthew Auld
2022-03-17  9:35   ` Thomas Hellström
2022-03-17 18:21     ` Bloomfield, Jon
2022-03-18  9:48       ` Thomas Hellström
2022-03-18 16:25         ` Bloomfield, Jon
2022-03-18 18:12           ` Daniel Vetter
2022-03-21  6:53             ` Thomas Hellström
2022-03-31  9:25             ` Matthew Auld
2022-04-04  9:04               ` Thomas Hellström

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