* [Intel-gfx] [PATCH 1/7] drm/i915/hwmon: Add HWMON infrastructure
2022-08-12 17:37 [Intel-gfx] [PATCH 0/7] drm/i915: Add HWMON support Badal Nilawar
@ 2022-08-12 17:37 ` Badal Nilawar
2022-08-12 18:05 ` Guenter Roeck
2022-08-12 17:37 ` [Intel-gfx] [PATCH 2/7] drm/i915/hwmon: Add HWMON current voltage support Badal Nilawar
` (9 subsequent siblings)
10 siblings, 1 reply; 21+ messages in thread
From: Badal Nilawar @ 2022-08-12 17:37 UTC (permalink / raw)
To: intel-gfx; +Cc: linux-hwmon, linux
From: Dale B Stimson <dale.b.stimson@intel.com>
The i915 HWMON module will be used to expose voltage, power and energy
values for dGfx. Here we set up i915 hwmon infrastructure including i915
hwmon registration, basic data structures and functions.
v2:
- Create HWMON infra patch (Ashutosh)
- Fixed review comments (Jani)
- Remove "select HWMON" from i915/Kconfig (Jani)
v3: Use hwm_ prefix for static functions (Ashutosh)
Signed-off-by: Dale B Stimson <dale.b.stimson@intel.com>
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Signed-off-by: Riana Tauro <riana.tauro@intel.com>
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
---
drivers/gpu/drm/i915/Makefile | 3 +
drivers/gpu/drm/i915/i915_driver.c | 7 ++
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/i915_hwmon.c | 135 +++++++++++++++++++++++++++++
drivers/gpu/drm/i915/i915_hwmon.h | 20 +++++
5 files changed, 167 insertions(+)
create mode 100644 drivers/gpu/drm/i915/i915_hwmon.c
create mode 100644 drivers/gpu/drm/i915/i915_hwmon.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 522ef9b4aff3..2b235f747490 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -208,6 +208,9 @@ i915-y += gt/uc/intel_uc.o \
# graphics system controller (GSC) support
i915-y += gt/intel_gsc.o
+# graphics hardware monitoring (HWMON) support
+i915-$(CONFIG_HWMON) += i915_hwmon.o
+
# modesetting core code
i915-y += \
display/hsw_ips.o \
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index deb8a8b76965..949908dd7496 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -80,6 +80,7 @@
#include "i915_drm_client.h"
#include "i915_drv.h"
#include "i915_getparam.h"
+#include "i915_hwmon.h"
#include "i915_ioc32.h"
#include "i915_ioctl.h"
#include "i915_irq.h"
@@ -736,6 +737,9 @@ static void i915_driver_register(struct drm_i915_private *dev_priv)
intel_gt_driver_register(to_gt(dev_priv));
+#ifdef CONFIG_HWMON
+ i915_hwmon_register(dev_priv);
+#endif
intel_display_driver_register(dev_priv);
intel_power_domains_enable(dev_priv);
@@ -762,6 +766,9 @@ static void i915_driver_unregister(struct drm_i915_private *dev_priv)
intel_display_driver_unregister(dev_priv);
+#ifdef CONFIG_HWMON
+ i915_hwmon_unregister(dev_priv);
+#endif
intel_gt_driver_unregister(to_gt(dev_priv));
i915_perf_unregister(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 086bbe8945d6..d437d588dec9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -705,6 +705,8 @@ struct drm_i915_private {
struct i915_perf perf;
+ struct i915_hwmon *hwmon;
+
/* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
struct intel_gt gt0;
diff --git a/drivers/gpu/drm/i915/i915_hwmon.c b/drivers/gpu/drm/i915/i915_hwmon.c
new file mode 100644
index 000000000000..5b80a0f024f0
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_hwmon.c
@@ -0,0 +1,135 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#include <linux/hwmon.h>
+#include <linux/hwmon-sysfs.h>
+#include <linux/types.h>
+
+#include "i915_drv.h"
+#include "i915_hwmon.h"
+#include "intel_mchbar_regs.h"
+
+struct hwm_reg {
+};
+
+struct hwm_drvdata {
+ struct i915_hwmon *hwmon;
+ struct intel_uncore *uncore;
+ struct device *hwmon_dev;
+ char name[12];
+};
+
+struct i915_hwmon {
+ struct hwm_drvdata ddat;
+ struct mutex hwmon_lock; /* counter overflow logic and rmw */
+ struct hwm_reg rg;
+};
+
+static const struct hwmon_channel_info *hwm_info[] = {
+ NULL
+};
+
+static umode_t
+hwm_is_visible(const void *drvdata, enum hwmon_sensor_types type,
+ u32 attr, int channel)
+{
+ switch (type) {
+ default:
+ return 0;
+ }
+}
+
+static int
+hwm_read(struct device *dev, enum hwmon_sensor_types type, u32 attr,
+ int channel, long *val)
+{
+ switch (type) {
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
+static int
+hwm_write(struct device *dev, enum hwmon_sensor_types type, u32 attr,
+ int channel, long val)
+{
+ switch (type) {
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
+static const struct hwmon_ops hwm_ops = {
+ .is_visible = hwm_is_visible,
+ .read = hwm_read,
+ .write = hwm_write,
+};
+
+static const struct hwmon_chip_info hwm_chip_info = {
+ .ops = &hwm_ops,
+ .info = hwm_info,
+};
+
+static void
+hwm_get_preregistration_info(struct drm_i915_private *i915)
+{
+}
+
+void i915_hwmon_register(struct drm_i915_private *i915)
+{
+ struct device *dev = i915->drm.dev;
+ struct i915_hwmon *hwmon;
+ struct device *hwmon_dev;
+ struct hwm_drvdata *ddat;
+
+ /* hwmon is available only for dGfx */
+ if (!IS_DGFX(i915))
+ return;
+
+ hwmon = kzalloc(sizeof(*hwmon), GFP_KERNEL);
+ if (!hwmon)
+ return;
+
+ i915->hwmon = hwmon;
+ mutex_init(&hwmon->hwmon_lock);
+ ddat = &hwmon->ddat;
+
+ ddat->hwmon = hwmon;
+ ddat->uncore = &i915->uncore;
+ snprintf(ddat->name, sizeof(ddat->name), "i915");
+
+ hwm_get_preregistration_info(i915);
+
+ /* hwmon_dev points to device hwmon<i> */
+ hwmon_dev = hwmon_device_register_with_info(dev, ddat->name,
+ ddat,
+ &hwm_chip_info,
+ NULL);
+ if (IS_ERR(hwmon_dev)) {
+ mutex_destroy(&hwmon->hwmon_lock);
+ i915->hwmon = NULL;
+ kfree(hwmon);
+ return;
+ }
+
+ ddat->hwmon_dev = hwmon_dev;
+}
+
+void i915_hwmon_unregister(struct drm_i915_private *i915)
+{
+ struct i915_hwmon *hwmon;
+ struct hwm_drvdata *ddat;
+
+ hwmon = fetch_and_zero(&i915->hwmon);
+ if (!hwmon)
+ return;
+
+ ddat = &hwmon->ddat;
+ if (ddat->hwmon_dev)
+ hwmon_device_unregister(ddat->hwmon_dev);
+
+ mutex_destroy(&hwmon->hwmon_lock);
+ kfree(hwmon);
+}
diff --git a/drivers/gpu/drm/i915/i915_hwmon.h b/drivers/gpu/drm/i915/i915_hwmon.h
new file mode 100644
index 000000000000..921ae76099d3
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_hwmon.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: MIT */
+
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __I915_HWMON_H__
+#define __I915_HWMON_H__
+
+#include <linux/device.h>
+#include <linux/mutex.h>
+#include <linux/types.h>
+#include "i915_reg.h"
+
+struct drm_i915_private;
+
+void i915_hwmon_register(struct drm_i915_private *i915);
+void i915_hwmon_unregister(struct drm_i915_private *i915);
+
+#endif /* __I915_HWMON_H__ */
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [Intel-gfx] [PATCH 1/7] drm/i915/hwmon: Add HWMON infrastructure
2022-08-12 17:37 ` [Intel-gfx] [PATCH 1/7] drm/i915/hwmon: Add HWMON infrastructure Badal Nilawar
@ 2022-08-12 18:05 ` Guenter Roeck
0 siblings, 0 replies; 21+ messages in thread
From: Guenter Roeck @ 2022-08-12 18:05 UTC (permalink / raw)
To: Badal Nilawar, intel-gfx; +Cc: linux-hwmon
On 8/12/22 10:37, Badal Nilawar wrote:
> From: Dale B Stimson <dale.b.stimson@intel.com>
>
> The i915 HWMON module will be used to expose voltage, power and energy
> values for dGfx. Here we set up i915 hwmon infrastructure including i915
> hwmon registration, basic data structures and functions.
>
> v2:
> - Create HWMON infra patch (Ashutosh)
> - Fixed review comments (Jani)
> - Remove "select HWMON" from i915/Kconfig (Jani)
> v3: Use hwm_ prefix for static functions (Ashutosh)
>
> Signed-off-by: Dale B Stimson <dale.b.stimson@intel.com>
> Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
> Signed-off-by: Riana Tauro <riana.tauro@intel.com>
> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> ---
> drivers/gpu/drm/i915/Makefile | 3 +
> drivers/gpu/drm/i915/i915_driver.c | 7 ++
> drivers/gpu/drm/i915/i915_drv.h | 2 +
> drivers/gpu/drm/i915/i915_hwmon.c | 135 +++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/i915_hwmon.h | 20 +++++
> 5 files changed, 167 insertions(+)
> create mode 100644 drivers/gpu/drm/i915/i915_hwmon.c
> create mode 100644 drivers/gpu/drm/i915/i915_hwmon.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 522ef9b4aff3..2b235f747490 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -208,6 +208,9 @@ i915-y += gt/uc/intel_uc.o \
> # graphics system controller (GSC) support
> i915-y += gt/intel_gsc.o
>
> +# graphics hardware monitoring (HWMON) support
> +i915-$(CONFIG_HWMON) += i915_hwmon.o
> +
> # modesetting core code
> i915-y += \
> display/hsw_ips.o \
> diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
> index deb8a8b76965..949908dd7496 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -80,6 +80,7 @@
> #include "i915_drm_client.h"
> #include "i915_drv.h"
> #include "i915_getparam.h"
> +#include "i915_hwmon.h"
> #include "i915_ioc32.h"
> #include "i915_ioctl.h"
> #include "i915_irq.h"
> @@ -736,6 +737,9 @@ static void i915_driver_register(struct drm_i915_private *dev_priv)
>
> intel_gt_driver_register(to_gt(dev_priv));
>
> +#ifdef CONFIG_HWMON
> + i915_hwmon_register(dev_priv);
> +#endif
> intel_display_driver_register(dev_priv);
>
> intel_power_domains_enable(dev_priv);
> @@ -762,6 +766,9 @@ static void i915_driver_unregister(struct drm_i915_private *dev_priv)
>
> intel_display_driver_unregister(dev_priv);
>
> +#ifdef CONFIG_HWMON
IS_REACHABLE() might be more appropriate. Otherwise this won't be included
if HWMON=m. An alternate approach might be to have dummy functions if the
hwmon code isn't rechable to avoid conditional code, but that is really
personal preference.
> + i915_hwmon_unregister(dev_priv);
> +#endif
> intel_gt_driver_unregister(to_gt(dev_priv));
>
> i915_perf_unregister(dev_priv);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 086bbe8945d6..d437d588dec9 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -705,6 +705,8 @@ struct drm_i915_private {
>
> struct i915_perf perf;
>
> + struct i915_hwmon *hwmon;
> +
> /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
> struct intel_gt gt0;
>
> diff --git a/drivers/gpu/drm/i915/i915_hwmon.c b/drivers/gpu/drm/i915/i915_hwmon.c
> new file mode 100644
> index 000000000000..5b80a0f024f0
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/i915_hwmon.c
> @@ -0,0 +1,135 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2022 Intel Corporation
> + */
> +
> +#include <linux/hwmon.h>
> +#include <linux/hwmon-sysfs.h>
> +#include <linux/types.h>
> +
> +#include "i915_drv.h"
> +#include "i915_hwmon.h"
> +#include "intel_mchbar_regs.h"
> +
> +struct hwm_reg {
> +};
> +
> +struct hwm_drvdata {
> + struct i915_hwmon *hwmon;
> + struct intel_uncore *uncore;
> + struct device *hwmon_dev;
> + char name[12];
> +};
> +
> +struct i915_hwmon {
> + struct hwm_drvdata ddat;
> + struct mutex hwmon_lock; /* counter overflow logic and rmw */
> + struct hwm_reg rg;
> +};
> +
> +static const struct hwmon_channel_info *hwm_info[] = {
> + NULL
> +};
> +
> +static umode_t
> +hwm_is_visible(const void *drvdata, enum hwmon_sensor_types type,
> + u32 attr, int channel)
> +{
> + switch (type) {
> + default:
> + return 0;
> + }
> +}
> +
> +static int
> +hwm_read(struct device *dev, enum hwmon_sensor_types type, u32 attr,
> + int channel, long *val)
> +{
> + switch (type) {
> + default:
> + return -EOPNOTSUPP;
> + }
> +}
> +
> +static int
> +hwm_write(struct device *dev, enum hwmon_sensor_types type, u32 attr,
> + int channel, long val)
> +{
> + switch (type) {
> + default:
> + return -EOPNOTSUPP;
> + }
> +}
> +
> +static const struct hwmon_ops hwm_ops = {
> + .is_visible = hwm_is_visible,
> + .read = hwm_read,
> + .write = hwm_write,
> +};
> +
> +static const struct hwmon_chip_info hwm_chip_info = {
> + .ops = &hwm_ops,
> + .info = hwm_info,
> +};
> +
> +static void
> +hwm_get_preregistration_info(struct drm_i915_private *i915)
> +{
> +}
> +
> +void i915_hwmon_register(struct drm_i915_private *i915)
> +{
> + struct device *dev = i915->drm.dev;
> + struct i915_hwmon *hwmon;
> + struct device *hwmon_dev;
> + struct hwm_drvdata *ddat;
> +
> + /* hwmon is available only for dGfx */
> + if (!IS_DGFX(i915))
> + return;
> +
> + hwmon = kzalloc(sizeof(*hwmon), GFP_KERNEL);
> + if (!hwmon)
> + return;
> +
> + i915->hwmon = hwmon;
> + mutex_init(&hwmon->hwmon_lock);
> + ddat = &hwmon->ddat;
> +
> + ddat->hwmon = hwmon;
> + ddat->uncore = &i915->uncore;
> + snprintf(ddat->name, sizeof(ddat->name), "i915");
> +
> + hwm_get_preregistration_info(i915);
> +
> + /* hwmon_dev points to device hwmon<i> */
> + hwmon_dev = hwmon_device_register_with_info(dev, ddat->name,
> + ddat,
> + &hwm_chip_info,
> + NULL);
> + if (IS_ERR(hwmon_dev)) {
> + mutex_destroy(&hwmon->hwmon_lock);
> + i915->hwmon = NULL;
> + kfree(hwmon);
> + return;
> + }
> +
> + ddat->hwmon_dev = hwmon_dev;
> +}
> +
> +void i915_hwmon_unregister(struct drm_i915_private *i915)
> +{
> + struct i915_hwmon *hwmon;
> + struct hwm_drvdata *ddat;
> +
> + hwmon = fetch_and_zero(&i915->hwmon);
> + if (!hwmon)
> + return;
> +
> + ddat = &hwmon->ddat;
> + if (ddat->hwmon_dev)
> + hwmon_device_unregister(ddat->hwmon_dev);
> +
> + mutex_destroy(&hwmon->hwmon_lock);
> + kfree(hwmon);
> +}
> diff --git a/drivers/gpu/drm/i915/i915_hwmon.h b/drivers/gpu/drm/i915/i915_hwmon.h
> new file mode 100644
> index 000000000000..921ae76099d3
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/i915_hwmon.h
> @@ -0,0 +1,20 @@
> +/* SPDX-License-Identifier: MIT */
> +
> +/*
> + * Copyright © 2022 Intel Corporation
> + */
> +
> +#ifndef __I915_HWMON_H__
> +#define __I915_HWMON_H__
> +
> +#include <linux/device.h>
> +#include <linux/mutex.h>
> +#include <linux/types.h>
> +#include "i915_reg.h"
> +
> +struct drm_i915_private;
> +
> +void i915_hwmon_register(struct drm_i915_private *i915);
> +void i915_hwmon_unregister(struct drm_i915_private *i915);
> +
> +#endif /* __I915_HWMON_H__ */
^ permalink raw reply [flat|nested] 21+ messages in thread
* [Intel-gfx] [PATCH 2/7] drm/i915/hwmon: Add HWMON current voltage support
2022-08-12 17:37 [Intel-gfx] [PATCH 0/7] drm/i915: Add HWMON support Badal Nilawar
2022-08-12 17:37 ` [Intel-gfx] [PATCH 1/7] drm/i915/hwmon: Add HWMON infrastructure Badal Nilawar
@ 2022-08-12 17:37 ` Badal Nilawar
2022-08-12 18:05 ` Guenter Roeck
2022-08-12 17:37 ` [Intel-gfx] [PATCH 3/7] drm/i915/hwmon: Power PL1 limit and TDP setting Badal Nilawar
` (8 subsequent siblings)
10 siblings, 1 reply; 21+ messages in thread
From: Badal Nilawar @ 2022-08-12 17:37 UTC (permalink / raw)
To: intel-gfx; +Cc: linux-hwmon, linux
From: Riana Tauro <riana.tauro@intel.com>
Use i915 HWMON subsystem to display current input voltage.
v2:
- Updated date and kernel version in feature description
- Fixed review comments (Ashutosh)
v3: Use macro HWMON_CHANNEL_INFO to define hwmon channel (Guenter)
v4:
- Fixed review comments (Ashutosh)
- Use hwm_ prefix for static functions (Ashutosh)
Cc: Guenter Roeck <linux@roeck-us.net>
Cc: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Riana Tauro <riana.tauro@intel.com>
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
---
.../ABI/testing/sysfs-driver-intel-i915-hwmon | 7 +++
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 ++
drivers/gpu/drm/i915/i915_hwmon.c | 47 +++++++++++++++++++
3 files changed, 57 insertions(+)
create mode 100644 Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
diff --git a/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
new file mode 100644
index 000000000000..24c4b7477d51
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
@@ -0,0 +1,7 @@
+What: /sys/devices/.../hwmon/hwmon<i>/in0_input
+Date: June 2022
+KernelVersion: 5.19
+Contact: dri-devel@lists.freedesktop.org
+Description: RO. Current Voltage in millivolt.
+
+ Only supported for particular Intel i915 graphics platforms.
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index b3b49f6d6d1c..4604f6dbf8b6 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1498,6 +1498,9 @@
#define VLV_RENDER_C0_COUNT _MMIO(0x138118)
#define VLV_MEDIA_C0_COUNT _MMIO(0x13811c)
+#define GEN12_RPSTAT1 _MMIO(0x1381b4)
+#define GEN12_VOLTAGE_MASK REG_GENMASK(10, 0)
+
#define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4))
#define GEN11_CSME (31)
#define GEN11_GUNIT (28)
diff --git a/drivers/gpu/drm/i915/i915_hwmon.c b/drivers/gpu/drm/i915/i915_hwmon.c
index 5b80a0f024f0..1893efe796a4 100644
--- a/drivers/gpu/drm/i915/i915_hwmon.c
+++ b/drivers/gpu/drm/i915/i915_hwmon.c
@@ -10,8 +10,10 @@
#include "i915_drv.h"
#include "i915_hwmon.h"
#include "intel_mchbar_regs.h"
+#include "gt/intel_gt_regs.h"
struct hwm_reg {
+ i915_reg_t gt_perf_status;
};
struct hwm_drvdata {
@@ -28,14 +30,49 @@ struct i915_hwmon {
};
static const struct hwmon_channel_info *hwm_info[] = {
+ HWMON_CHANNEL_INFO(in, HWMON_I_INPUT),
NULL
};
+static umode_t
+hwm_in_is_visible(const struct hwm_drvdata *ddat, u32 attr)
+{
+ switch (attr) {
+ case hwmon_in_input:
+ return i915_mmio_reg_valid(ddat->hwmon->rg.gt_perf_status) ? 0444 : 0;
+ default:
+ return 0;
+ }
+}
+
+static int
+hwm_in_read(struct hwm_drvdata *ddat, u32 attr, long *val)
+{
+ struct i915_hwmon *hwmon = ddat->hwmon;
+ intel_wakeref_t wakeref;
+ u32 reg_value;
+
+ switch (attr) {
+ case hwmon_in_input:
+ with_intel_runtime_pm(ddat->uncore->rpm, wakeref)
+ reg_value = intel_uncore_read(ddat->uncore, hwmon->rg.gt_perf_status);
+ /* In units of 2.5 millivolt */
+ *val = DIV_ROUND_CLOSEST(REG_FIELD_GET(GEN12_VOLTAGE_MASK, reg_value) * 25, 10);
+ return 0;
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
static umode_t
hwm_is_visible(const void *drvdata, enum hwmon_sensor_types type,
u32 attr, int channel)
{
+ struct hwm_drvdata *ddat = (struct hwm_drvdata *)drvdata;
+
switch (type) {
+ case hwmon_in:
+ return hwm_in_is_visible(ddat, attr);
default:
return 0;
}
@@ -45,7 +82,11 @@ static int
hwm_read(struct device *dev, enum hwmon_sensor_types type, u32 attr,
int channel, long *val)
{
+ struct hwm_drvdata *ddat = dev_get_drvdata(dev);
+
switch (type) {
+ case hwmon_in:
+ return hwm_in_read(ddat, attr, val);
default:
return -EOPNOTSUPP;
}
@@ -75,6 +116,12 @@ static const struct hwmon_chip_info hwm_chip_info = {
static void
hwm_get_preregistration_info(struct drm_i915_private *i915)
{
+ struct i915_hwmon *hwmon = i915->hwmon;
+
+ if (IS_DG1(i915) || IS_DG2(i915))
+ hwmon->rg.gt_perf_status = GEN12_RPSTAT1;
+ else
+ hwmon->rg.gt_perf_status = INVALID_MMIO_REG;
}
void i915_hwmon_register(struct drm_i915_private *i915)
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [Intel-gfx] [PATCH 2/7] drm/i915/hwmon: Add HWMON current voltage support
2022-08-12 17:37 ` [Intel-gfx] [PATCH 2/7] drm/i915/hwmon: Add HWMON current voltage support Badal Nilawar
@ 2022-08-12 18:05 ` Guenter Roeck
0 siblings, 0 replies; 21+ messages in thread
From: Guenter Roeck @ 2022-08-12 18:05 UTC (permalink / raw)
To: Badal Nilawar, intel-gfx; +Cc: linux-hwmon
On 8/12/22 10:37, Badal Nilawar wrote:
> From: Riana Tauro <riana.tauro@intel.com>
>
> Use i915 HWMON subsystem to display current input voltage.
>
> v2:
> - Updated date and kernel version in feature description
> - Fixed review comments (Ashutosh)
> v3: Use macro HWMON_CHANNEL_INFO to define hwmon channel (Guenter)
> v4:
> - Fixed review comments (Ashutosh)
> - Use hwm_ prefix for static functions (Ashutosh)
>
> Cc: Guenter Roeck <linux@roeck-us.net>
> Cc: Anshuman Gupta <anshuman.gupta@intel.com>
> Signed-off-by: Riana Tauro <riana.tauro@intel.com>
> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
Acked-by: Guenter Roeck <linux@roeck-us.net>
> ---
> .../ABI/testing/sysfs-driver-intel-i915-hwmon | 7 +++
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 ++
> drivers/gpu/drm/i915/i915_hwmon.c | 47 +++++++++++++++++++
> 3 files changed, 57 insertions(+)
> create mode 100644 Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
>
> diff --git a/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
> new file mode 100644
> index 000000000000..24c4b7477d51
> --- /dev/null
> +++ b/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
> @@ -0,0 +1,7 @@
> +What: /sys/devices/.../hwmon/hwmon<i>/in0_input
> +Date: June 2022
> +KernelVersion: 5.19
> +Contact: dri-devel@lists.freedesktop.org
> +Description: RO. Current Voltage in millivolt.
> +
> + Only supported for particular Intel i915 graphics platforms.
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index b3b49f6d6d1c..4604f6dbf8b6 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -1498,6 +1498,9 @@
> #define VLV_RENDER_C0_COUNT _MMIO(0x138118)
> #define VLV_MEDIA_C0_COUNT _MMIO(0x13811c)
>
> +#define GEN12_RPSTAT1 _MMIO(0x1381b4)
> +#define GEN12_VOLTAGE_MASK REG_GENMASK(10, 0)
> +
> #define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4))
> #define GEN11_CSME (31)
> #define GEN11_GUNIT (28)
> diff --git a/drivers/gpu/drm/i915/i915_hwmon.c b/drivers/gpu/drm/i915/i915_hwmon.c
> index 5b80a0f024f0..1893efe796a4 100644
> --- a/drivers/gpu/drm/i915/i915_hwmon.c
> +++ b/drivers/gpu/drm/i915/i915_hwmon.c
> @@ -10,8 +10,10 @@
> #include "i915_drv.h"
> #include "i915_hwmon.h"
> #include "intel_mchbar_regs.h"
> +#include "gt/intel_gt_regs.h"
>
> struct hwm_reg {
> + i915_reg_t gt_perf_status;
> };
>
> struct hwm_drvdata {
> @@ -28,14 +30,49 @@ struct i915_hwmon {
> };
>
> static const struct hwmon_channel_info *hwm_info[] = {
> + HWMON_CHANNEL_INFO(in, HWMON_I_INPUT),
> NULL
> };
>
> +static umode_t
> +hwm_in_is_visible(const struct hwm_drvdata *ddat, u32 attr)
> +{
> + switch (attr) {
> + case hwmon_in_input:
> + return i915_mmio_reg_valid(ddat->hwmon->rg.gt_perf_status) ? 0444 : 0;
> + default:
> + return 0;
> + }
> +}
> +
> +static int
> +hwm_in_read(struct hwm_drvdata *ddat, u32 attr, long *val)
> +{
> + struct i915_hwmon *hwmon = ddat->hwmon;
> + intel_wakeref_t wakeref;
> + u32 reg_value;
> +
> + switch (attr) {
> + case hwmon_in_input:
> + with_intel_runtime_pm(ddat->uncore->rpm, wakeref)
> + reg_value = intel_uncore_read(ddat->uncore, hwmon->rg.gt_perf_status);
> + /* In units of 2.5 millivolt */
> + *val = DIV_ROUND_CLOSEST(REG_FIELD_GET(GEN12_VOLTAGE_MASK, reg_value) * 25, 10);
> + return 0;
> + default:
> + return -EOPNOTSUPP;
> + }
> +}
> +
> static umode_t
> hwm_is_visible(const void *drvdata, enum hwmon_sensor_types type,
> u32 attr, int channel)
> {
> + struct hwm_drvdata *ddat = (struct hwm_drvdata *)drvdata;
> +
> switch (type) {
> + case hwmon_in:
> + return hwm_in_is_visible(ddat, attr);
> default:
> return 0;
> }
> @@ -45,7 +82,11 @@ static int
> hwm_read(struct device *dev, enum hwmon_sensor_types type, u32 attr,
> int channel, long *val)
> {
> + struct hwm_drvdata *ddat = dev_get_drvdata(dev);
> +
> switch (type) {
> + case hwmon_in:
> + return hwm_in_read(ddat, attr, val);
> default:
> return -EOPNOTSUPP;
> }
> @@ -75,6 +116,12 @@ static const struct hwmon_chip_info hwm_chip_info = {
> static void
> hwm_get_preregistration_info(struct drm_i915_private *i915)
> {
> + struct i915_hwmon *hwmon = i915->hwmon;
> +
> + if (IS_DG1(i915) || IS_DG2(i915))
> + hwmon->rg.gt_perf_status = GEN12_RPSTAT1;
> + else
> + hwmon->rg.gt_perf_status = INVALID_MMIO_REG;
> }
>
> void i915_hwmon_register(struct drm_i915_private *i915)
^ permalink raw reply [flat|nested] 21+ messages in thread
* [Intel-gfx] [PATCH 3/7] drm/i915/hwmon: Power PL1 limit and TDP setting
2022-08-12 17:37 [Intel-gfx] [PATCH 0/7] drm/i915: Add HWMON support Badal Nilawar
2022-08-12 17:37 ` [Intel-gfx] [PATCH 1/7] drm/i915/hwmon: Add HWMON infrastructure Badal Nilawar
2022-08-12 17:37 ` [Intel-gfx] [PATCH 2/7] drm/i915/hwmon: Add HWMON current voltage support Badal Nilawar
@ 2022-08-12 17:37 ` Badal Nilawar
2022-08-12 18:06 ` Guenter Roeck
2022-08-12 17:37 ` [Intel-gfx] [PATCH 4/7] drm/i915/hwmon: Show device level energy usage Badal Nilawar
` (7 subsequent siblings)
10 siblings, 1 reply; 21+ messages in thread
From: Badal Nilawar @ 2022-08-12 17:37 UTC (permalink / raw)
To: intel-gfx; +Cc: linux-hwmon, linux
From: Dale B Stimson <dale.b.stimson@intel.com>
Use i915 HWMON to display/modify dGfx power PL1 limit and TDP setting.
v2:
- Fix review comments (Ashutosh)
- Do not restore power1_max upon module unload/load sequence
because on production systems modules are always loaded
and not unloaded/reloaded (Ashutosh)
- Fix review comments (Jani)
- Remove endianness conversion (Ashutosh)
v3: Add power1_rated_max (Ashutosh)
v4:
- Use macro HWMON_CHANNEL_INFO to define power channel (Guenter)
- Update the date and kernel version in Documentation (Badal)
v5: Use hwm_ prefix for static functions (Ashutosh)
Cc: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Dale B Stimson <dale.b.stimson@intel.com>
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Signed-off-by: Riana Tauro <riana.tauro@intel.com>
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
---
.../ABI/testing/sysfs-driver-intel-i915-hwmon | 20 ++
drivers/gpu/drm/i915/i915_hwmon.c | 176 +++++++++++++++++-
drivers/gpu/drm/i915/i915_reg.h | 16 ++
drivers/gpu/drm/i915/intel_mchbar_regs.h | 7 +
4 files changed, 217 insertions(+), 2 deletions(-)
diff --git a/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
index 24c4b7477d51..9a2d10edfce8 100644
--- a/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
+++ b/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
@@ -5,3 +5,23 @@ Contact: dri-devel@lists.freedesktop.org
Description: RO. Current Voltage in millivolt.
Only supported for particular Intel i915 graphics platforms.
+
+What: /sys/devices/.../hwmon/hwmon<i>/power1_max
+Date: June 2022
+KernelVersion: 5.19
+Contact: dri-devel@lists.freedesktop.org
+Description: RW. Card reactive sustained (PL1/Tau) power limit in microwatts.
+
+ The power controller will throttle the operating frequency
+ if the power averaged over a window (typically seconds)
+ exceeds this limit.
+
+ Only supported for particular Intel i915 graphics platforms.
+
+What: /sys/devices/.../hwmon/hwmon<i>/power1_rated_max
+Date: June 2022
+KernelVersion: 5.19
+Contact: dri-devel@lists.freedesktop.org
+Description: RO. Card default power limit (default TDP setting).
+
+ Only supported for particular Intel i915 graphics platforms.
diff --git a/drivers/gpu/drm/i915/i915_hwmon.c b/drivers/gpu/drm/i915/i915_hwmon.c
index 1893efe796a4..2ce5bf94b220 100644
--- a/drivers/gpu/drm/i915/i915_hwmon.c
+++ b/drivers/gpu/drm/i915/i915_hwmon.c
@@ -12,8 +12,22 @@
#include "intel_mchbar_regs.h"
#include "gt/intel_gt_regs.h"
+/*
+ * SF_* - scale factors for particular quantities according to hwmon spec.
+ * - power - microwatts
+ */
+#define SF_POWER 1000000
+
+#define FIELD_SHIFT(__mask) \
+ (BUILD_BUG_ON_ZERO(!__builtin_constant_p(__mask)) + \
+ BUILD_BUG_ON_ZERO((__mask) == 0) + \
+ __bf_shf(__mask))
+
struct hwm_reg {
i915_reg_t gt_perf_status;
+ i915_reg_t pkg_power_sku_unit;
+ i915_reg_t pkg_power_sku;
+ i915_reg_t pkg_rapl_limit;
};
struct hwm_drvdata {
@@ -27,10 +41,70 @@ struct i915_hwmon {
struct hwm_drvdata ddat;
struct mutex hwmon_lock; /* counter overflow logic and rmw */
struct hwm_reg rg;
+ u32 power_max_initial_value;
+ int scl_shift_power;
};
+static void
+hwm_locked_with_pm_intel_uncore_rmw(struct hwm_drvdata *ddat,
+ i915_reg_t reg, u32 clear, u32 set)
+{
+ struct i915_hwmon *hwmon = ddat->hwmon;
+ struct intel_uncore *uncore = ddat->uncore;
+ intel_wakeref_t wakeref;
+
+ mutex_lock(&hwmon->hwmon_lock);
+
+ with_intel_runtime_pm(uncore->rpm, wakeref)
+ intel_uncore_rmw(uncore, reg, clear, set);
+
+ mutex_unlock(&hwmon->hwmon_lock);
+}
+
+/*
+ * This function's return type of u64 allows for the case where the scaling
+ * of the field taken from the 32-bit register value might cause a result to
+ * exceed 32 bits.
+ */
+static u64
+hwm_field_read_and_scale(struct hwm_drvdata *ddat, i915_reg_t rgadr,
+ u32 field_msk, int field_shift,
+ int nshift, u32 scale_factor)
+{
+ struct intel_uncore *uncore = ddat->uncore;
+ intel_wakeref_t wakeref;
+ u32 reg_value;
+
+ with_intel_runtime_pm(uncore->rpm, wakeref)
+ reg_value = intel_uncore_read(uncore, rgadr);
+
+ reg_value = (reg_value & field_msk) >> field_shift;
+
+ return mul_u64_u32_shr(reg_value, scale_factor, nshift);
+}
+
+static void
+hwm_field_scale_and_write(struct hwm_drvdata *ddat, i915_reg_t rgadr,
+ u32 field_msk, int field_shift,
+ int nshift, unsigned int scale_factor, long lval)
+{
+ u32 nval;
+ u32 bits_to_clear;
+ u32 bits_to_set;
+
+ /* Computation in 64-bits to avoid overflow. Round to nearest. */
+ nval = DIV_ROUND_CLOSEST_ULL((u64)lval << nshift, scale_factor);
+
+ bits_to_clear = field_msk;
+ bits_to_set = (nval << field_shift) & field_msk;
+
+ hwm_locked_with_pm_intel_uncore_rmw(ddat, rgadr,
+ bits_to_clear, bits_to_set);
+}
+
static const struct hwmon_channel_info *hwm_info[] = {
HWMON_CHANNEL_INFO(in, HWMON_I_INPUT),
+ HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX),
NULL
};
@@ -64,6 +138,67 @@ hwm_in_read(struct hwm_drvdata *ddat, u32 attr, long *val)
}
}
+static umode_t
+hwm_power_is_visible(const struct hwm_drvdata *ddat, u32 attr, int chan)
+{
+ struct i915_hwmon *hwmon = ddat->hwmon;
+
+ switch (attr) {
+ case hwmon_power_max:
+ return i915_mmio_reg_valid(hwmon->rg.pkg_rapl_limit) ? 0664 : 0;
+ case hwmon_power_rated_max:
+ return i915_mmio_reg_valid(hwmon->rg.pkg_power_sku) ? 0444 : 0;
+ default:
+ return 0;
+ }
+}
+
+static int
+hwm_power_read(struct hwm_drvdata *ddat, u32 attr, int chan, long *val)
+{
+ struct i915_hwmon *hwmon = ddat->hwmon;
+
+ switch (attr) {
+ case hwmon_power_max:
+ *val = hwm_field_read_and_scale(ddat,
+ hwmon->rg.pkg_rapl_limit,
+ PKG_PWR_LIM_1,
+ FIELD_SHIFT(PKG_PWR_LIM_1),
+ hwmon->scl_shift_power,
+ SF_POWER);
+ return 0;
+ case hwmon_power_rated_max:
+ *val = hwm_field_read_and_scale(ddat,
+ hwmon->rg.pkg_power_sku,
+ PKG_PKG_TDP,
+ FIELD_SHIFT(PKG_PKG_TDP),
+ hwmon->scl_shift_power,
+ SF_POWER);
+ return 0;
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
+static int
+hwm_power_write(struct hwm_drvdata *ddat, u32 attr, int chan, long val)
+{
+ struct i915_hwmon *hwmon = ddat->hwmon;
+
+ switch (attr) {
+ case hwmon_power_max:
+ hwm_field_scale_and_write(ddat,
+ hwmon->rg.pkg_rapl_limit,
+ PKG_PWR_LIM_1,
+ FIELD_SHIFT(PKG_PWR_LIM_1),
+ hwmon->scl_shift_power,
+ SF_POWER, val);
+ return 0;
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
static umode_t
hwm_is_visible(const void *drvdata, enum hwmon_sensor_types type,
u32 attr, int channel)
@@ -73,6 +208,8 @@ hwm_is_visible(const void *drvdata, enum hwmon_sensor_types type,
switch (type) {
case hwmon_in:
return hwm_in_is_visible(ddat, attr);
+ case hwmon_power:
+ return hwm_power_is_visible(ddat, attr, channel);
default:
return 0;
}
@@ -87,6 +224,8 @@ hwm_read(struct device *dev, enum hwmon_sensor_types type, u32 attr,
switch (type) {
case hwmon_in:
return hwm_in_read(ddat, attr, val);
+ case hwmon_power:
+ return hwm_power_read(ddat, attr, channel, val);
default:
return -EOPNOTSUPP;
}
@@ -96,7 +235,11 @@ static int
hwm_write(struct device *dev, enum hwmon_sensor_types type, u32 attr,
int channel, long val)
{
+ struct hwm_drvdata *ddat = dev_get_drvdata(dev);
+
switch (type) {
+ case hwmon_power:
+ return hwm_power_write(ddat, attr, channel, val);
default:
return -EOPNOTSUPP;
}
@@ -117,11 +260,40 @@ static void
hwm_get_preregistration_info(struct drm_i915_private *i915)
{
struct i915_hwmon *hwmon = i915->hwmon;
+ struct intel_uncore *uncore = &i915->uncore;
+ intel_wakeref_t wakeref;
+ u32 val_sku_unit;
- if (IS_DG1(i915) || IS_DG2(i915))
+ if (IS_DG1(i915) || IS_DG2(i915)) {
hwmon->rg.gt_perf_status = GEN12_RPSTAT1;
- else
+ hwmon->rg.pkg_power_sku_unit = PCU_PACKAGE_POWER_SKU_UNIT;
+ hwmon->rg.pkg_power_sku = INVALID_MMIO_REG;
+ hwmon->rg.pkg_rapl_limit = PCU_PACKAGE_RAPL_LIMIT;
+ } else {
hwmon->rg.gt_perf_status = INVALID_MMIO_REG;
+ hwmon->rg.pkg_power_sku_unit = INVALID_MMIO_REG;
+ hwmon->rg.pkg_power_sku = INVALID_MMIO_REG;
+ hwmon->rg.pkg_rapl_limit = INVALID_MMIO_REG;
+ }
+
+ with_intel_runtime_pm(uncore->rpm, wakeref) {
+ /*
+ * The contents of register hwmon->rg.pkg_power_sku_unit do not change,
+ * so read it once and store the shift values.
+ *
+ * For some platforms, this value is defined as available "for all
+ * tiles", with the values consistent across all tiles.
+ * In this case, use the tile 0 value for all.
+ */
+ if (i915_mmio_reg_valid(hwmon->rg.pkg_power_sku_unit)) {
+ val_sku_unit = intel_uncore_read(uncore,
+ hwmon->rg.pkg_power_sku_unit);
+ } else {
+ val_sku_unit = 0;
+ }
+
+ hwmon->scl_shift_power = REG_FIELD_GET(PKG_PWR_UNIT, val_sku_unit);
+ }
}
void i915_hwmon_register(struct drm_i915_private *i915)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ad2c441aceca..0bc6ae0c8bd7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1866,6 +1866,22 @@
#define POWER_LIMIT_1_MASK REG_BIT(11)
#define POWER_LIMIT_2_MASK REG_BIT(12)
+/*
+ * *_PACKAGE_POWER_SKU - SKU power and timing parameters.
+ * Used herein as a 64-bit register.
+ * These masks are defined using GENMASK_ULL as REG_GENMASK is limited to u32
+ * and as GENMASK is "long" and therefore 32-bits on a 32-bit system.
+ * PKG_PKG_TDP, PKG_MIN_PWR, and PKG_MAX_PWR are scaled in the same way as
+ * PKG_PWR_LIM_*, above.
+ * PKG_MAX_WIN has sub-fields for x and y, and has the value: is 1.x * 2^y.
+ */
+#define PKG_PKG_TDP GENMASK_ULL(14, 0)
+#define PKG_MIN_PWR GENMASK_ULL(30, 16)
+#define PKG_MAX_PWR GENMASK_ULL(46, 32)
+#define PKG_MAX_WIN GENMASK_ULL(54, 48)
+#define PKG_MAX_WIN_Y GENMASK_ULL(54, 53)
+#define PKG_MAX_WIN_X GENMASK_ULL(52, 48)
+
#define CHV_CLK_CTL1 _MMIO(0x101100)
#define VLV_CLK_CTL2 _MMIO(0x101104)
#define CLK_CTL2_CZCOUNT_30NS_SHIFT 28
diff --git a/drivers/gpu/drm/i915/intel_mchbar_regs.h b/drivers/gpu/drm/i915/intel_mchbar_regs.h
index 2aad2f0cc8db..4ba5f30b7901 100644
--- a/drivers/gpu/drm/i915/intel_mchbar_regs.h
+++ b/drivers/gpu/drm/i915/intel_mchbar_regs.h
@@ -189,6 +189,10 @@
#define DG1_QCLK_RATIO_MASK REG_GENMASK(9, 2)
#define DG1_QCLK_REFERENCE REG_BIT(10)
+#define PCU_PACKAGE_POWER_SKU_UNIT _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5938)
+#define PKG_PWR_UNIT REG_GENMASK(3, 0)
+#define PKG_TIME_UNIT REG_GENMASK(19, 16)
+
#define GEN6_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948)
#define GEN6_RP_STATE_LIMITS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994)
#define GEN6_RP_STATE_CAP _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998)
@@ -196,6 +200,9 @@
#define RP1_CAP_MASK REG_GENMASK(15, 8)
#define RPN_CAP_MASK REG_GENMASK(23, 16)
+#define PCU_PACKAGE_RAPL_LIMIT _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x59a0)
+#define PKG_PWR_LIM_1 REG_GENMASK(14, 0)
+
/* snb MCH registers for priority tuning */
#define MCH_SSKPD _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10)
#define SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [Intel-gfx] [PATCH 3/7] drm/i915/hwmon: Power PL1 limit and TDP setting
2022-08-12 17:37 ` [Intel-gfx] [PATCH 3/7] drm/i915/hwmon: Power PL1 limit and TDP setting Badal Nilawar
@ 2022-08-12 18:06 ` Guenter Roeck
2023-02-28 21:18 ` Dixit, Ashutosh
0 siblings, 1 reply; 21+ messages in thread
From: Guenter Roeck @ 2022-08-12 18:06 UTC (permalink / raw)
To: Badal Nilawar, intel-gfx; +Cc: linux-hwmon
On 8/12/22 10:37, Badal Nilawar wrote:
> From: Dale B Stimson <dale.b.stimson@intel.com>
>
> Use i915 HWMON to display/modify dGfx power PL1 limit and TDP setting.
>
> v2:
> - Fix review comments (Ashutosh)
> - Do not restore power1_max upon module unload/load sequence
> because on production systems modules are always loaded
> and not unloaded/reloaded (Ashutosh)
> - Fix review comments (Jani)
> - Remove endianness conversion (Ashutosh)
> v3: Add power1_rated_max (Ashutosh)
> v4:
> - Use macro HWMON_CHANNEL_INFO to define power channel (Guenter)
> - Update the date and kernel version in Documentation (Badal)
> v5: Use hwm_ prefix for static functions (Ashutosh)
>
> Cc: Guenter Roeck <linux@roeck-us.net>
> Signed-off-by: Dale B Stimson <dale.b.stimson@intel.com>
> Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
> Signed-off-by: Riana Tauro <riana.tauro@intel.com>
> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
Acked-by: Guenter Roeck <linux@roeck-us.net>
> ---
> .../ABI/testing/sysfs-driver-intel-i915-hwmon | 20 ++
> drivers/gpu/drm/i915/i915_hwmon.c | 176 +++++++++++++++++-
> drivers/gpu/drm/i915/i915_reg.h | 16 ++
> drivers/gpu/drm/i915/intel_mchbar_regs.h | 7 +
> 4 files changed, 217 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
> index 24c4b7477d51..9a2d10edfce8 100644
> --- a/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
> +++ b/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
> @@ -5,3 +5,23 @@ Contact: dri-devel@lists.freedesktop.org
> Description: RO. Current Voltage in millivolt.
>
> Only supported for particular Intel i915 graphics platforms.
> +
> +What: /sys/devices/.../hwmon/hwmon<i>/power1_max
> +Date: June 2022
> +KernelVersion: 5.19
> +Contact: dri-devel@lists.freedesktop.org
> +Description: RW. Card reactive sustained (PL1/Tau) power limit in microwatts.
> +
> + The power controller will throttle the operating frequency
> + if the power averaged over a window (typically seconds)
> + exceeds this limit.
> +
> + Only supported for particular Intel i915 graphics platforms.
> +
> +What: /sys/devices/.../hwmon/hwmon<i>/power1_rated_max
> +Date: June 2022
> +KernelVersion: 5.19
> +Contact: dri-devel@lists.freedesktop.org
> +Description: RO. Card default power limit (default TDP setting).
> +
> + Only supported for particular Intel i915 graphics platforms.
> diff --git a/drivers/gpu/drm/i915/i915_hwmon.c b/drivers/gpu/drm/i915/i915_hwmon.c
> index 1893efe796a4..2ce5bf94b220 100644
> --- a/drivers/gpu/drm/i915/i915_hwmon.c
> +++ b/drivers/gpu/drm/i915/i915_hwmon.c
> @@ -12,8 +12,22 @@
> #include "intel_mchbar_regs.h"
> #include "gt/intel_gt_regs.h"
>
> +/*
> + * SF_* - scale factors for particular quantities according to hwmon spec.
> + * - power - microwatts
> + */
> +#define SF_POWER 1000000
> +
> +#define FIELD_SHIFT(__mask) \
> + (BUILD_BUG_ON_ZERO(!__builtin_constant_p(__mask)) + \
> + BUILD_BUG_ON_ZERO((__mask) == 0) + \
> + __bf_shf(__mask))
> +
> struct hwm_reg {
> i915_reg_t gt_perf_status;
> + i915_reg_t pkg_power_sku_unit;
> + i915_reg_t pkg_power_sku;
> + i915_reg_t pkg_rapl_limit;
> };
>
> struct hwm_drvdata {
> @@ -27,10 +41,70 @@ struct i915_hwmon {
> struct hwm_drvdata ddat;
> struct mutex hwmon_lock; /* counter overflow logic and rmw */
> struct hwm_reg rg;
> + u32 power_max_initial_value;
> + int scl_shift_power;
> };
>
> +static void
> +hwm_locked_with_pm_intel_uncore_rmw(struct hwm_drvdata *ddat,
> + i915_reg_t reg, u32 clear, u32 set)
> +{
> + struct i915_hwmon *hwmon = ddat->hwmon;
> + struct intel_uncore *uncore = ddat->uncore;
> + intel_wakeref_t wakeref;
> +
> + mutex_lock(&hwmon->hwmon_lock);
> +
> + with_intel_runtime_pm(uncore->rpm, wakeref)
> + intel_uncore_rmw(uncore, reg, clear, set);
> +
> + mutex_unlock(&hwmon->hwmon_lock);
> +}
> +
> +/*
> + * This function's return type of u64 allows for the case where the scaling
> + * of the field taken from the 32-bit register value might cause a result to
> + * exceed 32 bits.
> + */
> +static u64
> +hwm_field_read_and_scale(struct hwm_drvdata *ddat, i915_reg_t rgadr,
> + u32 field_msk, int field_shift,
> + int nshift, u32 scale_factor)
> +{
> + struct intel_uncore *uncore = ddat->uncore;
> + intel_wakeref_t wakeref;
> + u32 reg_value;
> +
> + with_intel_runtime_pm(uncore->rpm, wakeref)
> + reg_value = intel_uncore_read(uncore, rgadr);
> +
> + reg_value = (reg_value & field_msk) >> field_shift;
> +
> + return mul_u64_u32_shr(reg_value, scale_factor, nshift);
> +}
> +
> +static void
> +hwm_field_scale_and_write(struct hwm_drvdata *ddat, i915_reg_t rgadr,
> + u32 field_msk, int field_shift,
> + int nshift, unsigned int scale_factor, long lval)
> +{
> + u32 nval;
> + u32 bits_to_clear;
> + u32 bits_to_set;
> +
> + /* Computation in 64-bits to avoid overflow. Round to nearest. */
> + nval = DIV_ROUND_CLOSEST_ULL((u64)lval << nshift, scale_factor);
> +
> + bits_to_clear = field_msk;
> + bits_to_set = (nval << field_shift) & field_msk;
> +
> + hwm_locked_with_pm_intel_uncore_rmw(ddat, rgadr,
> + bits_to_clear, bits_to_set);
> +}
> +
> static const struct hwmon_channel_info *hwm_info[] = {
> HWMON_CHANNEL_INFO(in, HWMON_I_INPUT),
> + HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX),
> NULL
> };
>
> @@ -64,6 +138,67 @@ hwm_in_read(struct hwm_drvdata *ddat, u32 attr, long *val)
> }
> }
>
> +static umode_t
> +hwm_power_is_visible(const struct hwm_drvdata *ddat, u32 attr, int chan)
> +{
> + struct i915_hwmon *hwmon = ddat->hwmon;
> +
> + switch (attr) {
> + case hwmon_power_max:
> + return i915_mmio_reg_valid(hwmon->rg.pkg_rapl_limit) ? 0664 : 0;
> + case hwmon_power_rated_max:
> + return i915_mmio_reg_valid(hwmon->rg.pkg_power_sku) ? 0444 : 0;
> + default:
> + return 0;
> + }
> +}
> +
> +static int
> +hwm_power_read(struct hwm_drvdata *ddat, u32 attr, int chan, long *val)
> +{
> + struct i915_hwmon *hwmon = ddat->hwmon;
> +
> + switch (attr) {
> + case hwmon_power_max:
> + *val = hwm_field_read_and_scale(ddat,
> + hwmon->rg.pkg_rapl_limit,
> + PKG_PWR_LIM_1,
> + FIELD_SHIFT(PKG_PWR_LIM_1),
> + hwmon->scl_shift_power,
> + SF_POWER);
> + return 0;
> + case hwmon_power_rated_max:
> + *val = hwm_field_read_and_scale(ddat,
> + hwmon->rg.pkg_power_sku,
> + PKG_PKG_TDP,
> + FIELD_SHIFT(PKG_PKG_TDP),
> + hwmon->scl_shift_power,
> + SF_POWER);
> + return 0;
> + default:
> + return -EOPNOTSUPP;
> + }
> +}
> +
> +static int
> +hwm_power_write(struct hwm_drvdata *ddat, u32 attr, int chan, long val)
> +{
> + struct i915_hwmon *hwmon = ddat->hwmon;
> +
> + switch (attr) {
> + case hwmon_power_max:
> + hwm_field_scale_and_write(ddat,
> + hwmon->rg.pkg_rapl_limit,
> + PKG_PWR_LIM_1,
> + FIELD_SHIFT(PKG_PWR_LIM_1),
> + hwmon->scl_shift_power,
> + SF_POWER, val);
> + return 0;
> + default:
> + return -EOPNOTSUPP;
> + }
> +}
> +
> static umode_t
> hwm_is_visible(const void *drvdata, enum hwmon_sensor_types type,
> u32 attr, int channel)
> @@ -73,6 +208,8 @@ hwm_is_visible(const void *drvdata, enum hwmon_sensor_types type,
> switch (type) {
> case hwmon_in:
> return hwm_in_is_visible(ddat, attr);
> + case hwmon_power:
> + return hwm_power_is_visible(ddat, attr, channel);
> default:
> return 0;
> }
> @@ -87,6 +224,8 @@ hwm_read(struct device *dev, enum hwmon_sensor_types type, u32 attr,
> switch (type) {
> case hwmon_in:
> return hwm_in_read(ddat, attr, val);
> + case hwmon_power:
> + return hwm_power_read(ddat, attr, channel, val);
> default:
> return -EOPNOTSUPP;
> }
> @@ -96,7 +235,11 @@ static int
> hwm_write(struct device *dev, enum hwmon_sensor_types type, u32 attr,
> int channel, long val)
> {
> + struct hwm_drvdata *ddat = dev_get_drvdata(dev);
> +
> switch (type) {
> + case hwmon_power:
> + return hwm_power_write(ddat, attr, channel, val);
> default:
> return -EOPNOTSUPP;
> }
> @@ -117,11 +260,40 @@ static void
> hwm_get_preregistration_info(struct drm_i915_private *i915)
> {
> struct i915_hwmon *hwmon = i915->hwmon;
> + struct intel_uncore *uncore = &i915->uncore;
> + intel_wakeref_t wakeref;
> + u32 val_sku_unit;
>
> - if (IS_DG1(i915) || IS_DG2(i915))
> + if (IS_DG1(i915) || IS_DG2(i915)) {
> hwmon->rg.gt_perf_status = GEN12_RPSTAT1;
> - else
> + hwmon->rg.pkg_power_sku_unit = PCU_PACKAGE_POWER_SKU_UNIT;
> + hwmon->rg.pkg_power_sku = INVALID_MMIO_REG;
> + hwmon->rg.pkg_rapl_limit = PCU_PACKAGE_RAPL_LIMIT;
> + } else {
> hwmon->rg.gt_perf_status = INVALID_MMIO_REG;
> + hwmon->rg.pkg_power_sku_unit = INVALID_MMIO_REG;
> + hwmon->rg.pkg_power_sku = INVALID_MMIO_REG;
> + hwmon->rg.pkg_rapl_limit = INVALID_MMIO_REG;
> + }
> +
> + with_intel_runtime_pm(uncore->rpm, wakeref) {
> + /*
> + * The contents of register hwmon->rg.pkg_power_sku_unit do not change,
> + * so read it once and store the shift values.
> + *
> + * For some platforms, this value is defined as available "for all
> + * tiles", with the values consistent across all tiles.
> + * In this case, use the tile 0 value for all.
> + */
> + if (i915_mmio_reg_valid(hwmon->rg.pkg_power_sku_unit)) {
> + val_sku_unit = intel_uncore_read(uncore,
> + hwmon->rg.pkg_power_sku_unit);
> + } else {
> + val_sku_unit = 0;
> + }
> +
> + hwmon->scl_shift_power = REG_FIELD_GET(PKG_PWR_UNIT, val_sku_unit);
> + }
> }
>
> void i915_hwmon_register(struct drm_i915_private *i915)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index ad2c441aceca..0bc6ae0c8bd7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1866,6 +1866,22 @@
> #define POWER_LIMIT_1_MASK REG_BIT(11)
> #define POWER_LIMIT_2_MASK REG_BIT(12)
>
> +/*
> + * *_PACKAGE_POWER_SKU - SKU power and timing parameters.
> + * Used herein as a 64-bit register.
> + * These masks are defined using GENMASK_ULL as REG_GENMASK is limited to u32
> + * and as GENMASK is "long" and therefore 32-bits on a 32-bit system.
> + * PKG_PKG_TDP, PKG_MIN_PWR, and PKG_MAX_PWR are scaled in the same way as
> + * PKG_PWR_LIM_*, above.
> + * PKG_MAX_WIN has sub-fields for x and y, and has the value: is 1.x * 2^y.
> + */
> +#define PKG_PKG_TDP GENMASK_ULL(14, 0)
> +#define PKG_MIN_PWR GENMASK_ULL(30, 16)
> +#define PKG_MAX_PWR GENMASK_ULL(46, 32)
> +#define PKG_MAX_WIN GENMASK_ULL(54, 48)
> +#define PKG_MAX_WIN_Y GENMASK_ULL(54, 53)
> +#define PKG_MAX_WIN_X GENMASK_ULL(52, 48)
> +
> #define CHV_CLK_CTL1 _MMIO(0x101100)
> #define VLV_CLK_CTL2 _MMIO(0x101104)
> #define CLK_CTL2_CZCOUNT_30NS_SHIFT 28
> diff --git a/drivers/gpu/drm/i915/intel_mchbar_regs.h b/drivers/gpu/drm/i915/intel_mchbar_regs.h
> index 2aad2f0cc8db..4ba5f30b7901 100644
> --- a/drivers/gpu/drm/i915/intel_mchbar_regs.h
> +++ b/drivers/gpu/drm/i915/intel_mchbar_regs.h
> @@ -189,6 +189,10 @@
> #define DG1_QCLK_RATIO_MASK REG_GENMASK(9, 2)
> #define DG1_QCLK_REFERENCE REG_BIT(10)
>
> +#define PCU_PACKAGE_POWER_SKU_UNIT _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5938)
> +#define PKG_PWR_UNIT REG_GENMASK(3, 0)
> +#define PKG_TIME_UNIT REG_GENMASK(19, 16)
> +
> #define GEN6_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948)
> #define GEN6_RP_STATE_LIMITS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994)
> #define GEN6_RP_STATE_CAP _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998)
> @@ -196,6 +200,9 @@
> #define RP1_CAP_MASK REG_GENMASK(15, 8)
> #define RPN_CAP_MASK REG_GENMASK(23, 16)
>
> +#define PCU_PACKAGE_RAPL_LIMIT _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x59a0)
> +#define PKG_PWR_LIM_1 REG_GENMASK(14, 0)
> +
> /* snb MCH registers for priority tuning */
> #define MCH_SSKPD _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10)
> #define SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [Intel-gfx] [PATCH 3/7] drm/i915/hwmon: Power PL1 limit and TDP setting
2022-08-12 18:06 ` Guenter Roeck
@ 2023-02-28 21:18 ` Dixit, Ashutosh
2023-03-09 16:33 ` Guenter Roeck
0 siblings, 1 reply; 21+ messages in thread
From: Dixit, Ashutosh @ 2023-02-28 21:18 UTC (permalink / raw)
To: Guenter Roeck; +Cc: linux-hwmon, intel-gfx, dri-devel, Guenter Roeck
On Fri, 12 Aug 2022 11:06:58 -0700, Guenter Roeck wrote:
>
Hi Guenter/linux-hwmon,
> On 8/12/22 10:37, Badal Nilawar wrote:
> > From: Dale B Stimson <dale.b.stimson@intel.com>
> >
> > Use i915 HWMON to display/modify dGfx power PL1 limit and TDP setting.
> >
/snip/
>
> Acked-by: Guenter Roeck <linux@roeck-us.net>
>
> > ---
> > .../ABI/testing/sysfs-driver-intel-i915-hwmon | 20 ++
> > drivers/gpu/drm/i915/i915_hwmon.c | 176 +++++++++++++++++-
> > drivers/gpu/drm/i915/i915_reg.h | 16 ++
> > drivers/gpu/drm/i915/intel_mchbar_regs.h | 7 +
> > 4 files changed, 217 insertions(+), 2 deletions(-)
> >
> > diff --git a/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
> > index 24c4b7477d51..9a2d10edfce8 100644
> > --- a/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
> > +++ b/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
> > @@ -5,3 +5,23 @@ Contact: dri-devel@lists.freedesktop.org
> > Description: RO. Current Voltage in millivolt.
> > Only supported for particular Intel i915 graphics
> > platforms.
> > +
> > +What: /sys/devices/.../hwmon/hwmon<i>/power1_max
> > +Date: June 2022
> > +KernelVersion: 5.19
> > +Contact: dri-devel@lists.freedesktop.org
> > +Description: RW. Card reactive sustained (PL1/Tau) power limit in microwatts.
> > +
> > + The power controller will throttle the operating frequency
> > + if the power averaged over a window (typically seconds)
> > + exceeds this limit.
We exposed this as 'power1_max' previously. However this is a "power
limit".
https://github.com/torvalds/linux/blob/master/Documentation/hwmon/sysfs-interface.rst
says power1_max is "Maximum power". On the other hand, power1_cap is "If
power use rises above this limit, the system should take action to reduce
power use". So it would seem we should have chosen power1_cap for this
power limit instead of power1_max? So do you think we should change this to
power1_cap instead? Though even power1_max has an associated alarm so it
also seems to be a sort of limit.
Is there any guidance as to how these different power limits should be
used? Generally speaking is: power1_max <= power1_cap <= power1_crit, or is
it arbitrary or something else?
Also, only power1_cap seems to have power1_cap_min and power1_cap_max (in
case we wanted to use min/max values for the limits), not the others.
Separately, we have already used up power1_crit (which is the other limit
in official hwmon power limits) so we can't use that.
Thanks.
--
Ashutosh
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [Intel-gfx] [PATCH 3/7] drm/i915/hwmon: Power PL1 limit and TDP setting
2023-02-28 21:18 ` Dixit, Ashutosh
@ 2023-03-09 16:33 ` Guenter Roeck
0 siblings, 0 replies; 21+ messages in thread
From: Guenter Roeck @ 2023-03-09 16:33 UTC (permalink / raw)
To: Dixit, Ashutosh; +Cc: linux-hwmon, intel-gfx, dri-devel
On Tue, Feb 28, 2023 at 01:18:55PM -0800, Dixit, Ashutosh wrote:
> On Fri, 12 Aug 2022 11:06:58 -0700, Guenter Roeck wrote:
> >
>
> Hi Guenter/linux-hwmon,
>
>
> > On 8/12/22 10:37, Badal Nilawar wrote:
> > > From: Dale B Stimson <dale.b.stimson@intel.com>
> > >
> > > Use i915 HWMON to display/modify dGfx power PL1 limit and TDP setting.
> > >
>
> /snip/
>
> >
> > Acked-by: Guenter Roeck <linux@roeck-us.net>
> >
> > > ---
> > > .../ABI/testing/sysfs-driver-intel-i915-hwmon | 20 ++
> > > drivers/gpu/drm/i915/i915_hwmon.c | 176 +++++++++++++++++-
> > > drivers/gpu/drm/i915/i915_reg.h | 16 ++
> > > drivers/gpu/drm/i915/intel_mchbar_regs.h | 7 +
> > > 4 files changed, 217 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
> > > index 24c4b7477d51..9a2d10edfce8 100644
> > > --- a/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
> > > +++ b/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
> > > @@ -5,3 +5,23 @@ Contact: dri-devel@lists.freedesktop.org
> > > Description: RO. Current Voltage in millivolt.
> > > Only supported for particular Intel i915 graphics
> > > platforms.
> > > +
> > > +What: /sys/devices/.../hwmon/hwmon<i>/power1_max
> > > +Date: June 2022
> > > +KernelVersion: 5.19
> > > +Contact: dri-devel@lists.freedesktop.org
> > > +Description: RW. Card reactive sustained (PL1/Tau) power limit in microwatts.
> > > +
> > > + The power controller will throttle the operating frequency
> > > + if the power averaged over a window (typically seconds)
> > > + exceeds this limit.
>
> We exposed this as 'power1_max' previously. However this is a "power
> limit".
>
> https://github.com/torvalds/linux/blob/master/Documentation/hwmon/sysfs-interface.rst
>
> says power1_max is "Maximum power". On the other hand, power1_cap is "If
> power use rises above this limit, the system should take action to reduce
> power use". So it would seem we should have chosen power1_cap for this
> power limit instead of power1_max? So do you think we should change this to
> power1_cap instead? Though even power1_max has an associated alarm so it
> also seems to be a sort of limit.
>
> Is there any guidance as to how these different power limits should be
> used? Generally speaking is: power1_max <= power1_cap <= power1_crit, or is
> it arbitrary or something else?
>
Nothing should ever be "arbitrary" but have some reason. Arbitrary is
if you glue all the possible attributes onto a wall and then select the
ones to use by throwing darts at it.
powerX_min, powerX_max and powerX_crit are typically hard limits which
can not actively be influenced without drastic measures such as turning
off some hardware. powerX_cap is supposed to be more flexible; the
assumption is that the hardware or firmware has some means to control power
such that it does not exceed powerX_cap (while maintaining operational
status), for example by modifying operational frequencies.
Nowadays everything may be a bit more flexible; for example, one could
imagine that a modern system could (via software) reduce the operational
frequency of the system if power consumption exceeds powerX_max or
powerX_crit. The distinction would be that with powerX_cap, the hardware
or firmware would in general be in control, while with powerX_max
and powerX_crit the host software would be in control.
> Also, only power1_cap seems to have power1_cap_min and power1_cap_max (in
> case we wanted to use min/max values for the limits), not the others.
powerX_min is supported by the infrastructure. It not being documented
is an oversight.
Guenter
>
> Separately, we have already used up power1_crit (which is the other limit
> in official hwmon power limits) so we can't use that.
>
> Thanks.
> --
> Ashutosh
^ permalink raw reply [flat|nested] 21+ messages in thread
* [Intel-gfx] [PATCH 4/7] drm/i915/hwmon: Show device level energy usage
2022-08-12 17:37 [Intel-gfx] [PATCH 0/7] drm/i915: Add HWMON support Badal Nilawar
` (2 preceding siblings ...)
2022-08-12 17:37 ` [Intel-gfx] [PATCH 3/7] drm/i915/hwmon: Power PL1 limit and TDP setting Badal Nilawar
@ 2022-08-12 17:37 ` Badal Nilawar
2022-08-12 18:08 ` Guenter Roeck
2022-08-12 17:37 ` [Intel-gfx] [PATCH 5/7] drm/i915/hwmon: Expose card reactive critical power Badal Nilawar
` (6 subsequent siblings)
10 siblings, 1 reply; 21+ messages in thread
From: Badal Nilawar @ 2022-08-12 17:37 UTC (permalink / raw)
To: intel-gfx; +Cc: linux-hwmon, linux
From: Dale B Stimson <dale.b.stimson@intel.com>
Use i915 HWMON to display device level energy input.
v2:
- Updated the date and kernel version in feature description
Signed-off-by: Dale B Stimson <dale.b.stimson@intel.com>
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Signed-off-by: Riana Tauro <riana.tauro@intel.com>
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
---
.../ABI/testing/sysfs-driver-intel-i915-hwmon | 8 ++
drivers/gpu/drm/i915/i915_hwmon.c | 119 +++++++++++++++++-
drivers/gpu/drm/i915/i915_hwmon.h | 1 +
drivers/gpu/drm/i915/intel_mchbar_regs.h | 2 +
4 files changed, 128 insertions(+), 2 deletions(-)
diff --git a/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
index 9a2d10edfce8..03d71c6869d3 100644
--- a/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
+++ b/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
@@ -25,3 +25,11 @@ Contact: dri-devel@lists.freedesktop.org
Description: RO. Card default power limit (default TDP setting).
Only supported for particular Intel i915 graphics platforms.
+
+What: /sys/devices/.../hwmon/hwmon<i>/energy1_input
+Date: June 2022
+KernelVersion: 5.19
+Contact: dri-devel@lists.freedesktop.org
+Description: RO. Energy input of device in microjoules.
+
+ Only supported for particular Intel i915 graphics platforms.
diff --git a/drivers/gpu/drm/i915/i915_hwmon.c b/drivers/gpu/drm/i915/i915_hwmon.c
index 2ce5bf94b220..416c77c89609 100644
--- a/drivers/gpu/drm/i915/i915_hwmon.c
+++ b/drivers/gpu/drm/i915/i915_hwmon.c
@@ -15,8 +15,10 @@
/*
* SF_* - scale factors for particular quantities according to hwmon spec.
* - power - microwatts
+ * - energy - microjoules
*/
#define SF_POWER 1000000
+#define SF_ENERGY 1000000
#define FIELD_SHIFT(__mask) \
(BUILD_BUG_ON_ZERO(!__builtin_constant_p(__mask)) + \
@@ -28,12 +30,19 @@ struct hwm_reg {
i915_reg_t pkg_power_sku_unit;
i915_reg_t pkg_power_sku;
i915_reg_t pkg_rapl_limit;
+ i915_reg_t energy_status_all;
+};
+
+struct hwm_energy_info {
+ u32 reg_val_prev;
+ long accum_energy; /* Accumulated energy for energy1_input */
};
struct hwm_drvdata {
struct i915_hwmon *hwmon;
struct intel_uncore *uncore;
struct device *hwmon_dev;
+ struct hwm_energy_info ei; /* Energy info for energy1_input */
char name[12];
};
@@ -43,6 +52,7 @@ struct i915_hwmon {
struct hwm_reg rg;
u32 power_max_initial_value;
int scl_shift_power;
+ int scl_shift_energy;
};
static void
@@ -102,9 +112,72 @@ hwm_field_scale_and_write(struct hwm_drvdata *ddat, i915_reg_t rgadr,
bits_to_clear, bits_to_set);
}
+/*
+ * hwm_energy - Obtain energy value
+ *
+ * The underlying energy hardware register is 32-bits and is subject to
+ * overflow. How long before overflow? For example, with an example
+ * scaling bit shift of 14 bits (see register *PACKAGE_POWER_SKU_UNIT) and
+ * a power draw of 1000 watts, the 32-bit counter will overflow in
+ * approximately 4.36 minutes.
+ *
+ * Examples:
+ * 1 watt: (2^32 >> 14) / 1 W / (60 * 60 * 24) secs/day -> 3 days
+ * 1000 watts: (2^32 >> 14) / 1000 W / 60 secs/min -> 4.36 minutes
+ *
+ * The function significantly increases overflow duration (from 4.36
+ * minutes) by accumulating the energy register into a 'long' as allowed by
+ * the hwmon API. Using x86_64 128 bit arithmetic (see mul_u64_u32_shr()),
+ * a 'long' of 63 bits, SF_ENERGY of 1e6 (~20 bits) and
+ * hwmon->scl_shift_energy of 14 bits we have 57 (63 - 20 + 14) bits before
+ * energy1_input overflows. This at 1000 W is an overflow duration of 278 years.
+ */
+static int
+hwm_energy(struct hwm_drvdata *ddat, long *energy)
+{
+ struct intel_uncore *uncore = ddat->uncore;
+ struct i915_hwmon *hwmon = ddat->hwmon;
+ struct hwm_energy_info *ei = &ddat->ei;
+ intel_wakeref_t wakeref;
+ i915_reg_t rgaddr;
+ u32 reg_val;
+
+ rgaddr = hwmon->rg.energy_status_all;
+
+ if (!i915_mmio_reg_valid(rgaddr))
+ return -EOPNOTSUPP;
+
+ mutex_lock(&hwmon->hwmon_lock);
+
+ with_intel_runtime_pm(uncore->rpm, wakeref)
+ reg_val = intel_uncore_read(uncore, rgaddr);
+
+ if (reg_val >= ei->reg_val_prev)
+ ei->accum_energy += reg_val - ei->reg_val_prev;
+ else
+ ei->accum_energy += UINT_MAX - ei->reg_val_prev + reg_val;
+ ei->reg_val_prev = reg_val;
+
+ *energy = mul_u64_u32_shr(ei->accum_energy, SF_ENERGY,
+ hwmon->scl_shift_energy);
+ mutex_unlock(&hwmon->hwmon_lock);
+
+ return 0;
+}
+
+int
+i915_hwmon_energy_status_get(struct drm_i915_private *i915, long *energy)
+{
+ struct i915_hwmon *hwmon = i915->hwmon;
+ struct hwm_drvdata *ddat = &hwmon->ddat;
+
+ return hwm_energy(ddat, energy);
+}
+
static const struct hwmon_channel_info *hwm_info[] = {
HWMON_CHANNEL_INFO(in, HWMON_I_INPUT),
HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX),
+ HWMON_CHANNEL_INFO(energy, HWMON_E_INPUT),
NULL
};
@@ -199,6 +272,32 @@ hwm_power_write(struct hwm_drvdata *ddat, u32 attr, int chan, long val)
}
}
+static umode_t
+hwm_energy_is_visible(const struct hwm_drvdata *ddat, u32 attr)
+{
+ struct i915_hwmon *hwmon = ddat->hwmon;
+ i915_reg_t rgaddr;
+
+ switch (attr) {
+ case hwmon_energy_input:
+ rgaddr = hwmon->rg.energy_status_all;
+ return i915_mmio_reg_valid(rgaddr) ? 0444 : 0;
+ default:
+ return 0;
+ }
+}
+
+static int
+hwm_energy_read(struct hwm_drvdata *ddat, u32 attr, long *val)
+{
+ switch (attr) {
+ case hwmon_energy_input:
+ return hwm_energy(ddat, val);
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
static umode_t
hwm_is_visible(const void *drvdata, enum hwmon_sensor_types type,
u32 attr, int channel)
@@ -210,6 +309,8 @@ hwm_is_visible(const void *drvdata, enum hwmon_sensor_types type,
return hwm_in_is_visible(ddat, attr);
case hwmon_power:
return hwm_power_is_visible(ddat, attr, channel);
+ case hwmon_energy:
+ return hwm_energy_is_visible(ddat, attr);
default:
return 0;
}
@@ -226,6 +327,8 @@ hwm_read(struct device *dev, enum hwmon_sensor_types type, u32 attr,
return hwm_in_read(ddat, attr, val);
case hwmon_power:
return hwm_power_read(ddat, attr, channel, val);
+ case hwmon_energy:
+ return hwm_energy_read(ddat, attr, val);
default:
return -EOPNOTSUPP;
}
@@ -261,19 +364,23 @@ hwm_get_preregistration_info(struct drm_i915_private *i915)
{
struct i915_hwmon *hwmon = i915->hwmon;
struct intel_uncore *uncore = &i915->uncore;
+ struct hwm_drvdata *ddat = &hwmon->ddat;
intel_wakeref_t wakeref;
u32 val_sku_unit;
+ long energy;
if (IS_DG1(i915) || IS_DG2(i915)) {
hwmon->rg.gt_perf_status = GEN12_RPSTAT1;
hwmon->rg.pkg_power_sku_unit = PCU_PACKAGE_POWER_SKU_UNIT;
hwmon->rg.pkg_power_sku = INVALID_MMIO_REG;
hwmon->rg.pkg_rapl_limit = PCU_PACKAGE_RAPL_LIMIT;
+ hwmon->rg.energy_status_all = PCU_PACKAGE_ENERGY_STATUS;
} else {
hwmon->rg.gt_perf_status = INVALID_MMIO_REG;
hwmon->rg.pkg_power_sku_unit = INVALID_MMIO_REG;
hwmon->rg.pkg_power_sku = INVALID_MMIO_REG;
hwmon->rg.pkg_rapl_limit = INVALID_MMIO_REG;
+ hwmon->rg.energy_status_all = INVALID_MMIO_REG;
}
with_intel_runtime_pm(uncore->rpm, wakeref) {
@@ -291,9 +398,17 @@ hwm_get_preregistration_info(struct drm_i915_private *i915)
} else {
val_sku_unit = 0;
}
-
- hwmon->scl_shift_power = REG_FIELD_GET(PKG_PWR_UNIT, val_sku_unit);
}
+
+ hwmon->scl_shift_power = REG_FIELD_GET(PKG_PWR_UNIT, val_sku_unit);
+ hwmon->scl_shift_energy = REG_FIELD_GET(PKG_ENERGY_UNIT, val_sku_unit);
+
+ /*
+ * Initialize 'struct hwm_energy_info', i.e. set fields to the
+ * first value of the energy register read
+ */
+ if (i915_mmio_reg_valid(hwmon->rg.energy_status_all))
+ hwm_energy(ddat, &energy);
}
void i915_hwmon_register(struct drm_i915_private *i915)
diff --git a/drivers/gpu/drm/i915/i915_hwmon.h b/drivers/gpu/drm/i915/i915_hwmon.h
index 921ae76099d3..d5d7f4a0bf4e 100644
--- a/drivers/gpu/drm/i915/i915_hwmon.h
+++ b/drivers/gpu/drm/i915/i915_hwmon.h
@@ -17,4 +17,5 @@ struct drm_i915_private;
void i915_hwmon_register(struct drm_i915_private *i915);
void i915_hwmon_unregister(struct drm_i915_private *i915);
+int i915_hwmon_energy_status_get(struct drm_i915_private *i915, long *energy);
#endif /* __I915_HWMON_H__ */
diff --git a/drivers/gpu/drm/i915/intel_mchbar_regs.h b/drivers/gpu/drm/i915/intel_mchbar_regs.h
index 4ba5f30b7901..18fcfc39ca2f 100644
--- a/drivers/gpu/drm/i915/intel_mchbar_regs.h
+++ b/drivers/gpu/drm/i915/intel_mchbar_regs.h
@@ -191,7 +191,9 @@
#define PCU_PACKAGE_POWER_SKU_UNIT _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5938)
#define PKG_PWR_UNIT REG_GENMASK(3, 0)
+#define PKG_ENERGY_UNIT REG_GENMASK(12, 8)
#define PKG_TIME_UNIT REG_GENMASK(19, 16)
+#define PCU_PACKAGE_ENERGY_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x593c)
#define GEN6_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948)
#define GEN6_RP_STATE_LIMITS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994)
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [Intel-gfx] [PATCH 4/7] drm/i915/hwmon: Show device level energy usage
2022-08-12 17:37 ` [Intel-gfx] [PATCH 4/7] drm/i915/hwmon: Show device level energy usage Badal Nilawar
@ 2022-08-12 18:08 ` Guenter Roeck
0 siblings, 0 replies; 21+ messages in thread
From: Guenter Roeck @ 2022-08-12 18:08 UTC (permalink / raw)
To: Badal Nilawar, intel-gfx; +Cc: linux-hwmon
On 8/12/22 10:37, Badal Nilawar wrote:
> From: Dale B Stimson <dale.b.stimson@intel.com>
>
> Use i915 HWMON to display device level energy input.
>
> v2:
> - Updated the date and kernel version in feature description
>
> Signed-off-by: Dale B Stimson <dale.b.stimson@intel.com>
> Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
> Signed-off-by: Riana Tauro <riana.tauro@intel.com>
> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
Acked-by: Guenter Roeck <linux@roeck-us.net>
> ---
> .../ABI/testing/sysfs-driver-intel-i915-hwmon | 8 ++
> drivers/gpu/drm/i915/i915_hwmon.c | 119 +++++++++++++++++-
> drivers/gpu/drm/i915/i915_hwmon.h | 1 +
> drivers/gpu/drm/i915/intel_mchbar_regs.h | 2 +
> 4 files changed, 128 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
> index 9a2d10edfce8..03d71c6869d3 100644
> --- a/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
> +++ b/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
> @@ -25,3 +25,11 @@ Contact: dri-devel@lists.freedesktop.org
> Description: RO. Card default power limit (default TDP setting).
>
> Only supported for particular Intel i915 graphics platforms.
> +
> +What: /sys/devices/.../hwmon/hwmon<i>/energy1_input
> +Date: June 2022
> +KernelVersion: 5.19
> +Contact: dri-devel@lists.freedesktop.org
> +Description: RO. Energy input of device in microjoules.
> +
> + Only supported for particular Intel i915 graphics platforms.
> diff --git a/drivers/gpu/drm/i915/i915_hwmon.c b/drivers/gpu/drm/i915/i915_hwmon.c
> index 2ce5bf94b220..416c77c89609 100644
> --- a/drivers/gpu/drm/i915/i915_hwmon.c
> +++ b/drivers/gpu/drm/i915/i915_hwmon.c
> @@ -15,8 +15,10 @@
> /*
> * SF_* - scale factors for particular quantities according to hwmon spec.
> * - power - microwatts
> + * - energy - microjoules
> */
> #define SF_POWER 1000000
> +#define SF_ENERGY 1000000
>
> #define FIELD_SHIFT(__mask) \
> (BUILD_BUG_ON_ZERO(!__builtin_constant_p(__mask)) + \
> @@ -28,12 +30,19 @@ struct hwm_reg {
> i915_reg_t pkg_power_sku_unit;
> i915_reg_t pkg_power_sku;
> i915_reg_t pkg_rapl_limit;
> + i915_reg_t energy_status_all;
> +};
> +
> +struct hwm_energy_info {
> + u32 reg_val_prev;
> + long accum_energy; /* Accumulated energy for energy1_input */
> };
>
> struct hwm_drvdata {
> struct i915_hwmon *hwmon;
> struct intel_uncore *uncore;
> struct device *hwmon_dev;
> + struct hwm_energy_info ei; /* Energy info for energy1_input */
> char name[12];
> };
>
> @@ -43,6 +52,7 @@ struct i915_hwmon {
> struct hwm_reg rg;
> u32 power_max_initial_value;
> int scl_shift_power;
> + int scl_shift_energy;
> };
>
> static void
> @@ -102,9 +112,72 @@ hwm_field_scale_and_write(struct hwm_drvdata *ddat, i915_reg_t rgadr,
> bits_to_clear, bits_to_set);
> }
>
> +/*
> + * hwm_energy - Obtain energy value
> + *
> + * The underlying energy hardware register is 32-bits and is subject to
> + * overflow. How long before overflow? For example, with an example
> + * scaling bit shift of 14 bits (see register *PACKAGE_POWER_SKU_UNIT) and
> + * a power draw of 1000 watts, the 32-bit counter will overflow in
> + * approximately 4.36 minutes.
> + *
> + * Examples:
> + * 1 watt: (2^32 >> 14) / 1 W / (60 * 60 * 24) secs/day -> 3 days
> + * 1000 watts: (2^32 >> 14) / 1000 W / 60 secs/min -> 4.36 minutes
> + *
> + * The function significantly increases overflow duration (from 4.36
> + * minutes) by accumulating the energy register into a 'long' as allowed by
> + * the hwmon API. Using x86_64 128 bit arithmetic (see mul_u64_u32_shr()),
> + * a 'long' of 63 bits, SF_ENERGY of 1e6 (~20 bits) and
> + * hwmon->scl_shift_energy of 14 bits we have 57 (63 - 20 + 14) bits before
> + * energy1_input overflows. This at 1000 W is an overflow duration of 278 years.
> + */
> +static int
> +hwm_energy(struct hwm_drvdata *ddat, long *energy)
> +{
> + struct intel_uncore *uncore = ddat->uncore;
> + struct i915_hwmon *hwmon = ddat->hwmon;
> + struct hwm_energy_info *ei = &ddat->ei;
> + intel_wakeref_t wakeref;
> + i915_reg_t rgaddr;
> + u32 reg_val;
> +
> + rgaddr = hwmon->rg.energy_status_all;
> +
> + if (!i915_mmio_reg_valid(rgaddr))
> + return -EOPNOTSUPP;
> +
> + mutex_lock(&hwmon->hwmon_lock);
> +
> + with_intel_runtime_pm(uncore->rpm, wakeref)
> + reg_val = intel_uncore_read(uncore, rgaddr);
> +
> + if (reg_val >= ei->reg_val_prev)
> + ei->accum_energy += reg_val - ei->reg_val_prev;
> + else
> + ei->accum_energy += UINT_MAX - ei->reg_val_prev + reg_val;
> + ei->reg_val_prev = reg_val;
> +
> + *energy = mul_u64_u32_shr(ei->accum_energy, SF_ENERGY,
> + hwmon->scl_shift_energy);
> + mutex_unlock(&hwmon->hwmon_lock);
> +
> + return 0;
> +}
> +
> +int
> +i915_hwmon_energy_status_get(struct drm_i915_private *i915, long *energy)
> +{
> + struct i915_hwmon *hwmon = i915->hwmon;
> + struct hwm_drvdata *ddat = &hwmon->ddat;
> +
> + return hwm_energy(ddat, energy);
> +}
> +
> static const struct hwmon_channel_info *hwm_info[] = {
> HWMON_CHANNEL_INFO(in, HWMON_I_INPUT),
> HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX),
> + HWMON_CHANNEL_INFO(energy, HWMON_E_INPUT),
> NULL
> };
>
> @@ -199,6 +272,32 @@ hwm_power_write(struct hwm_drvdata *ddat, u32 attr, int chan, long val)
> }
> }
>
> +static umode_t
> +hwm_energy_is_visible(const struct hwm_drvdata *ddat, u32 attr)
> +{
> + struct i915_hwmon *hwmon = ddat->hwmon;
> + i915_reg_t rgaddr;
> +
> + switch (attr) {
> + case hwmon_energy_input:
> + rgaddr = hwmon->rg.energy_status_all;
> + return i915_mmio_reg_valid(rgaddr) ? 0444 : 0;
> + default:
> + return 0;
> + }
> +}
> +
> +static int
> +hwm_energy_read(struct hwm_drvdata *ddat, u32 attr, long *val)
> +{
> + switch (attr) {
> + case hwmon_energy_input:
> + return hwm_energy(ddat, val);
> + default:
> + return -EOPNOTSUPP;
> + }
> +}
> +
> static umode_t
> hwm_is_visible(const void *drvdata, enum hwmon_sensor_types type,
> u32 attr, int channel)
> @@ -210,6 +309,8 @@ hwm_is_visible(const void *drvdata, enum hwmon_sensor_types type,
> return hwm_in_is_visible(ddat, attr);
> case hwmon_power:
> return hwm_power_is_visible(ddat, attr, channel);
> + case hwmon_energy:
> + return hwm_energy_is_visible(ddat, attr);
> default:
> return 0;
> }
> @@ -226,6 +327,8 @@ hwm_read(struct device *dev, enum hwmon_sensor_types type, u32 attr,
> return hwm_in_read(ddat, attr, val);
> case hwmon_power:
> return hwm_power_read(ddat, attr, channel, val);
> + case hwmon_energy:
> + return hwm_energy_read(ddat, attr, val);
> default:
> return -EOPNOTSUPP;
> }
> @@ -261,19 +364,23 @@ hwm_get_preregistration_info(struct drm_i915_private *i915)
> {
> struct i915_hwmon *hwmon = i915->hwmon;
> struct intel_uncore *uncore = &i915->uncore;
> + struct hwm_drvdata *ddat = &hwmon->ddat;
> intel_wakeref_t wakeref;
> u32 val_sku_unit;
> + long energy;
>
> if (IS_DG1(i915) || IS_DG2(i915)) {
> hwmon->rg.gt_perf_status = GEN12_RPSTAT1;
> hwmon->rg.pkg_power_sku_unit = PCU_PACKAGE_POWER_SKU_UNIT;
> hwmon->rg.pkg_power_sku = INVALID_MMIO_REG;
> hwmon->rg.pkg_rapl_limit = PCU_PACKAGE_RAPL_LIMIT;
> + hwmon->rg.energy_status_all = PCU_PACKAGE_ENERGY_STATUS;
> } else {
> hwmon->rg.gt_perf_status = INVALID_MMIO_REG;
> hwmon->rg.pkg_power_sku_unit = INVALID_MMIO_REG;
> hwmon->rg.pkg_power_sku = INVALID_MMIO_REG;
> hwmon->rg.pkg_rapl_limit = INVALID_MMIO_REG;
> + hwmon->rg.energy_status_all = INVALID_MMIO_REG;
> }
>
> with_intel_runtime_pm(uncore->rpm, wakeref) {
> @@ -291,9 +398,17 @@ hwm_get_preregistration_info(struct drm_i915_private *i915)
> } else {
> val_sku_unit = 0;
> }
> -
> - hwmon->scl_shift_power = REG_FIELD_GET(PKG_PWR_UNIT, val_sku_unit);
> }
> +
> + hwmon->scl_shift_power = REG_FIELD_GET(PKG_PWR_UNIT, val_sku_unit);
> + hwmon->scl_shift_energy = REG_FIELD_GET(PKG_ENERGY_UNIT, val_sku_unit);
> +
> + /*
> + * Initialize 'struct hwm_energy_info', i.e. set fields to the
> + * first value of the energy register read
> + */
> + if (i915_mmio_reg_valid(hwmon->rg.energy_status_all))
> + hwm_energy(ddat, &energy);
> }
>
> void i915_hwmon_register(struct drm_i915_private *i915)
> diff --git a/drivers/gpu/drm/i915/i915_hwmon.h b/drivers/gpu/drm/i915/i915_hwmon.h
> index 921ae76099d3..d5d7f4a0bf4e 100644
> --- a/drivers/gpu/drm/i915/i915_hwmon.h
> +++ b/drivers/gpu/drm/i915/i915_hwmon.h
> @@ -17,4 +17,5 @@ struct drm_i915_private;
> void i915_hwmon_register(struct drm_i915_private *i915);
> void i915_hwmon_unregister(struct drm_i915_private *i915);
>
> +int i915_hwmon_energy_status_get(struct drm_i915_private *i915, long *energy);
> #endif /* __I915_HWMON_H__ */
> diff --git a/drivers/gpu/drm/i915/intel_mchbar_regs.h b/drivers/gpu/drm/i915/intel_mchbar_regs.h
> index 4ba5f30b7901..18fcfc39ca2f 100644
> --- a/drivers/gpu/drm/i915/intel_mchbar_regs.h
> +++ b/drivers/gpu/drm/i915/intel_mchbar_regs.h
> @@ -191,7 +191,9 @@
>
> #define PCU_PACKAGE_POWER_SKU_UNIT _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5938)
> #define PKG_PWR_UNIT REG_GENMASK(3, 0)
> +#define PKG_ENERGY_UNIT REG_GENMASK(12, 8)
> #define PKG_TIME_UNIT REG_GENMASK(19, 16)
> +#define PCU_PACKAGE_ENERGY_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x593c)
>
> #define GEN6_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948)
> #define GEN6_RP_STATE_LIMITS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994)
^ permalink raw reply [flat|nested] 21+ messages in thread
* [Intel-gfx] [PATCH 5/7] drm/i915/hwmon: Expose card reactive critical power
2022-08-12 17:37 [Intel-gfx] [PATCH 0/7] drm/i915: Add HWMON support Badal Nilawar
` (3 preceding siblings ...)
2022-08-12 17:37 ` [Intel-gfx] [PATCH 4/7] drm/i915/hwmon: Show device level energy usage Badal Nilawar
@ 2022-08-12 17:37 ` Badal Nilawar
2022-08-12 18:09 ` Guenter Roeck
2022-08-12 17:37 ` [Intel-gfx] [PATCH 6/7] drm/i915/hwmon: Expose power1_max_interval Badal Nilawar
` (5 subsequent siblings)
10 siblings, 1 reply; 21+ messages in thread
From: Badal Nilawar @ 2022-08-12 17:37 UTC (permalink / raw)
To: intel-gfx; +Cc: linux-hwmon, linux
From: Ashutosh Dixit <ashutosh.dixit@intel.com>
Expose the card reactive critical (I1) power. I1 is exposed as
power1_crit in microwatts (typically for client products) or as
curr1_crit in milliamperes (typically for server).
v2: Add curr1_crit functionality (Ashutosh)
v3:
- Use HWMON_CHANNEL_INFO to define power1_crit, curr1_crit (Badal)
- Update date and kernel version in Documentation.
v4: Use hwm_ prefix for static functions (Ashutosh)
Acked-by: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
---
.../ABI/testing/sysfs-driver-intel-i915-hwmon | 26 +++++
drivers/gpu/drm/i915/i915_hwmon.c | 95 ++++++++++++++++++-
drivers/gpu/drm/i915/i915_reg.h | 6 ++
3 files changed, 126 insertions(+), 1 deletion(-)
diff --git a/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
index 03d71c6869d3..bb1101757154 100644
--- a/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
+++ b/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
@@ -26,6 +26,32 @@ Description: RO. Card default power limit (default TDP setting).
Only supported for particular Intel i915 graphics platforms.
+What: /sys/devices/.../hwmon/hwmon<i>/power1_crit
+Date: June 2022
+KernelVersion: 5.19
+Contact: dri-devel@lists.freedesktop.org
+Description: RW. Card reactive critical (I1) power limit in microwatts.
+
+ Card reactive critical (I1) power limit in microwatts is exposed
+ for client products. The power controller will throttle the
+ operating frequency if the power averaged over a window exceeds
+ this limit.
+
+ Only supported for particular Intel i915 graphics platforms.
+
+What: /sys/devices/.../hwmon/hwmon<i>/curr1_crit
+Date: June 2022
+KernelVersion: 5.19
+Contact: dri-devel@lists.freedesktop.org
+Description: RW. Card reactive critical (I1) power limit in milliamperes.
+
+ Card reactive critical (I1) power limit in milliamperes is
+ exposed for server products. The power controller will throttle
+ the operating frequency if the power averaged over a window
+ exceeds this limit.
+
+ Only supported for particular Intel i915 graphics platforms.
+
What: /sys/devices/.../hwmon/hwmon<i>/energy1_input
Date: June 2022
KernelVersion: 5.19
diff --git a/drivers/gpu/drm/i915/i915_hwmon.c b/drivers/gpu/drm/i915/i915_hwmon.c
index 416c77c89609..b1a89a6aa220 100644
--- a/drivers/gpu/drm/i915/i915_hwmon.c
+++ b/drivers/gpu/drm/i915/i915_hwmon.c
@@ -10,14 +10,17 @@
#include "i915_drv.h"
#include "i915_hwmon.h"
#include "intel_mchbar_regs.h"
+#include "intel_pcode.h"
#include "gt/intel_gt_regs.h"
/*
* SF_* - scale factors for particular quantities according to hwmon spec.
* - power - microwatts
+ * - curr - milliamperes
* - energy - microjoules
*/
#define SF_POWER 1000000
+#define SF_CURR 1000
#define SF_ENERGY 1000000
#define FIELD_SHIFT(__mask) \
@@ -176,11 +179,25 @@ i915_hwmon_energy_status_get(struct drm_i915_private *i915, long *energy)
static const struct hwmon_channel_info *hwm_info[] = {
HWMON_CHANNEL_INFO(in, HWMON_I_INPUT),
- HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX),
+ HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_CRIT),
HWMON_CHANNEL_INFO(energy, HWMON_E_INPUT),
+ HWMON_CHANNEL_INFO(curr, HWMON_C_CRIT),
NULL
};
+/* I1 is exposed as power_crit or as curr_crit depending on bit 31 */
+static int hwm_pcode_read_i1(struct drm_i915_private *i915, u32 *uval)
+{
+ return snb_pcode_read_p(&i915->uncore, PCODE_POWER_SETUP,
+ POWER_SETUP_SUBCOMMAND_READ_I1, 0, uval);
+}
+
+static int hwm_pcode_write_i1(struct drm_i915_private *i915, u32 uval)
+{
+ return snb_pcode_write_p(&i915->uncore, PCODE_POWER_SETUP,
+ POWER_SETUP_SUBCOMMAND_WRITE_I1, 0, uval);
+}
+
static umode_t
hwm_in_is_visible(const struct hwm_drvdata *ddat, u32 attr)
{
@@ -214,13 +231,18 @@ hwm_in_read(struct hwm_drvdata *ddat, u32 attr, long *val)
static umode_t
hwm_power_is_visible(const struct hwm_drvdata *ddat, u32 attr, int chan)
{
+ struct drm_i915_private *i915 = ddat->uncore->i915;
struct i915_hwmon *hwmon = ddat->hwmon;
+ u32 uval;
switch (attr) {
case hwmon_power_max:
return i915_mmio_reg_valid(hwmon->rg.pkg_rapl_limit) ? 0664 : 0;
case hwmon_power_rated_max:
return i915_mmio_reg_valid(hwmon->rg.pkg_power_sku) ? 0444 : 0;
+ case hwmon_power_crit:
+ return (hwm_pcode_read_i1(i915, &uval) ||
+ !(uval & POWER_SETUP_I1_WATTS)) ? 0 : 0644;
default:
return 0;
}
@@ -230,6 +252,8 @@ static int
hwm_power_read(struct hwm_drvdata *ddat, u32 attr, int chan, long *val)
{
struct i915_hwmon *hwmon = ddat->hwmon;
+ int ret;
+ u32 uval;
switch (attr) {
case hwmon_power_max:
@@ -248,6 +272,15 @@ hwm_power_read(struct hwm_drvdata *ddat, u32 attr, int chan, long *val)
hwmon->scl_shift_power,
SF_POWER);
return 0;
+ case hwmon_power_crit:
+ ret = hwm_pcode_read_i1(ddat->uncore->i915, &uval);
+ if (ret)
+ return ret;
+ if (!(uval & POWER_SETUP_I1_WATTS))
+ return -ENODEV;
+ *val = mul_u64_u32_shr(REG_FIELD_GET(POWER_SETUP_I1_DATA_MASK, uval),
+ SF_POWER, POWER_SETUP_I1_SHIFT);
+ return 0;
default:
return -EOPNOTSUPP;
}
@@ -257,6 +290,7 @@ static int
hwm_power_write(struct hwm_drvdata *ddat, u32 attr, int chan, long val)
{
struct i915_hwmon *hwmon = ddat->hwmon;
+ u32 uval;
switch (attr) {
case hwmon_power_max:
@@ -267,6 +301,9 @@ hwm_power_write(struct hwm_drvdata *ddat, u32 attr, int chan, long val)
hwmon->scl_shift_power,
SF_POWER, val);
return 0;
+ case hwmon_power_crit:
+ uval = DIV_ROUND_CLOSEST_ULL(val << POWER_SETUP_I1_SHIFT, SF_POWER);
+ return hwm_pcode_write_i1(ddat->uncore->i915, uval);
default:
return -EOPNOTSUPP;
}
@@ -298,6 +335,56 @@ hwm_energy_read(struct hwm_drvdata *ddat, u32 attr, long *val)
}
}
+static umode_t
+hwm_curr_is_visible(const struct hwm_drvdata *ddat, u32 attr)
+{
+ struct drm_i915_private *i915 = ddat->uncore->i915;
+ u32 uval;
+
+ switch (attr) {
+ case hwmon_curr_crit:
+ return (hwm_pcode_read_i1(i915, &uval) ||
+ (uval & POWER_SETUP_I1_WATTS)) ? 0 : 0644;
+ default:
+ return 0;
+ }
+}
+
+static int
+hwm_curr_read(struct hwm_drvdata *ddat, u32 attr, long *val)
+{
+ int ret;
+ u32 uval;
+
+ switch (attr) {
+ case hwmon_curr_crit:
+ ret = hwm_pcode_read_i1(ddat->uncore->i915, &uval);
+ if (ret)
+ return ret;
+ if (uval & POWER_SETUP_I1_WATTS)
+ return -ENODEV;
+ *val = mul_u64_u32_shr(REG_FIELD_GET(POWER_SETUP_I1_DATA_MASK, uval),
+ SF_CURR, POWER_SETUP_I1_SHIFT);
+ return 0;
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
+static int
+hwm_curr_write(struct hwm_drvdata *ddat, u32 attr, long val)
+{
+ u32 uval;
+
+ switch (attr) {
+ case hwmon_curr_crit:
+ uval = DIV_ROUND_CLOSEST_ULL(val << POWER_SETUP_I1_SHIFT, SF_CURR);
+ return hwm_pcode_write_i1(ddat->uncore->i915, uval);
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
static umode_t
hwm_is_visible(const void *drvdata, enum hwmon_sensor_types type,
u32 attr, int channel)
@@ -311,6 +398,8 @@ hwm_is_visible(const void *drvdata, enum hwmon_sensor_types type,
return hwm_power_is_visible(ddat, attr, channel);
case hwmon_energy:
return hwm_energy_is_visible(ddat, attr);
+ case hwmon_curr:
+ return hwm_curr_is_visible(ddat, attr);
default:
return 0;
}
@@ -329,6 +418,8 @@ hwm_read(struct device *dev, enum hwmon_sensor_types type, u32 attr,
return hwm_power_read(ddat, attr, channel, val);
case hwmon_energy:
return hwm_energy_read(ddat, attr, val);
+ case hwmon_curr:
+ return hwm_curr_read(ddat, attr, val);
default:
return -EOPNOTSUPP;
}
@@ -343,6 +434,8 @@ hwm_write(struct device *dev, enum hwmon_sensor_types type, u32 attr,
switch (type) {
case hwmon_power:
return hwm_power_write(ddat, attr, channel, val);
+ case hwmon_curr:
+ return hwm_curr_write(ddat, attr, val);
default:
return -EOPNOTSUPP;
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0bc6ae0c8bd7..041b858b95f4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6788,6 +6788,12 @@
#define DG1_PCODE_STATUS 0x7E
#define DG1_UNCORE_GET_INIT_STATUS 0x0
#define DG1_UNCORE_INIT_STATUS_COMPLETE 0x1
+#define PCODE_POWER_SETUP 0x7C
+#define POWER_SETUP_SUBCOMMAND_READ_I1 0x4
+#define POWER_SETUP_SUBCOMMAND_WRITE_I1 0x5
+#define POWER_SETUP_I1_WATTS REG_BIT(31)
+#define POWER_SETUP_I1_SHIFT 6 /* 10.6 fixed point format */
+#define POWER_SETUP_I1_DATA_MASK REG_GENMASK(15, 0)
#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23
#define XEHP_PCODE_FREQUENCY_CONFIG 0x6e /* xehpsdv, pvc */
/* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [Intel-gfx] [PATCH 5/7] drm/i915/hwmon: Expose card reactive critical power
2022-08-12 17:37 ` [Intel-gfx] [PATCH 5/7] drm/i915/hwmon: Expose card reactive critical power Badal Nilawar
@ 2022-08-12 18:09 ` Guenter Roeck
0 siblings, 0 replies; 21+ messages in thread
From: Guenter Roeck @ 2022-08-12 18:09 UTC (permalink / raw)
To: Badal Nilawar, intel-gfx; +Cc: linux-hwmon
On 8/12/22 10:37, Badal Nilawar wrote:
> From: Ashutosh Dixit <ashutosh.dixit@intel.com>
>
> Expose the card reactive critical (I1) power. I1 is exposed as
> power1_crit in microwatts (typically for client products) or as
> curr1_crit in milliamperes (typically for server).
>
> v2: Add curr1_crit functionality (Ashutosh)
> v3:
> - Use HWMON_CHANNEL_INFO to define power1_crit, curr1_crit (Badal)
> - Update date and kernel version in Documentation.
> v4: Use hwm_ prefix for static functions (Ashutosh)
>
> Acked-by: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
> Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
Acked-by: Guenter Roeck <linux@roeck-us.net>
> ---
> .../ABI/testing/sysfs-driver-intel-i915-hwmon | 26 +++++
> drivers/gpu/drm/i915/i915_hwmon.c | 95 ++++++++++++++++++-
> drivers/gpu/drm/i915/i915_reg.h | 6 ++
> 3 files changed, 126 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
> index 03d71c6869d3..bb1101757154 100644
> --- a/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
> +++ b/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
> @@ -26,6 +26,32 @@ Description: RO. Card default power limit (default TDP setting).
>
> Only supported for particular Intel i915 graphics platforms.
>
> +What: /sys/devices/.../hwmon/hwmon<i>/power1_crit
> +Date: June 2022
> +KernelVersion: 5.19
> +Contact: dri-devel@lists.freedesktop.org
> +Description: RW. Card reactive critical (I1) power limit in microwatts.
> +
> + Card reactive critical (I1) power limit in microwatts is exposed
> + for client products. The power controller will throttle the
> + operating frequency if the power averaged over a window exceeds
> + this limit.
> +
> + Only supported for particular Intel i915 graphics platforms.
> +
> +What: /sys/devices/.../hwmon/hwmon<i>/curr1_crit
> +Date: June 2022
> +KernelVersion: 5.19
> +Contact: dri-devel@lists.freedesktop.org
> +Description: RW. Card reactive critical (I1) power limit in milliamperes.
> +
> + Card reactive critical (I1) power limit in milliamperes is
> + exposed for server products. The power controller will throttle
> + the operating frequency if the power averaged over a window
> + exceeds this limit.
> +
> + Only supported for particular Intel i915 graphics platforms.
> +
> What: /sys/devices/.../hwmon/hwmon<i>/energy1_input
> Date: June 2022
> KernelVersion: 5.19
> diff --git a/drivers/gpu/drm/i915/i915_hwmon.c b/drivers/gpu/drm/i915/i915_hwmon.c
> index 416c77c89609..b1a89a6aa220 100644
> --- a/drivers/gpu/drm/i915/i915_hwmon.c
> +++ b/drivers/gpu/drm/i915/i915_hwmon.c
> @@ -10,14 +10,17 @@
> #include "i915_drv.h"
> #include "i915_hwmon.h"
> #include "intel_mchbar_regs.h"
> +#include "intel_pcode.h"
> #include "gt/intel_gt_regs.h"
>
> /*
> * SF_* - scale factors for particular quantities according to hwmon spec.
> * - power - microwatts
> + * - curr - milliamperes
> * - energy - microjoules
> */
> #define SF_POWER 1000000
> +#define SF_CURR 1000
> #define SF_ENERGY 1000000
>
> #define FIELD_SHIFT(__mask) \
> @@ -176,11 +179,25 @@ i915_hwmon_energy_status_get(struct drm_i915_private *i915, long *energy)
>
> static const struct hwmon_channel_info *hwm_info[] = {
> HWMON_CHANNEL_INFO(in, HWMON_I_INPUT),
> - HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX),
> + HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_CRIT),
> HWMON_CHANNEL_INFO(energy, HWMON_E_INPUT),
> + HWMON_CHANNEL_INFO(curr, HWMON_C_CRIT),
> NULL
> };
>
> +/* I1 is exposed as power_crit or as curr_crit depending on bit 31 */
> +static int hwm_pcode_read_i1(struct drm_i915_private *i915, u32 *uval)
> +{
> + return snb_pcode_read_p(&i915->uncore, PCODE_POWER_SETUP,
> + POWER_SETUP_SUBCOMMAND_READ_I1, 0, uval);
> +}
> +
> +static int hwm_pcode_write_i1(struct drm_i915_private *i915, u32 uval)
> +{
> + return snb_pcode_write_p(&i915->uncore, PCODE_POWER_SETUP,
> + POWER_SETUP_SUBCOMMAND_WRITE_I1, 0, uval);
> +}
> +
> static umode_t
> hwm_in_is_visible(const struct hwm_drvdata *ddat, u32 attr)
> {
> @@ -214,13 +231,18 @@ hwm_in_read(struct hwm_drvdata *ddat, u32 attr, long *val)
> static umode_t
> hwm_power_is_visible(const struct hwm_drvdata *ddat, u32 attr, int chan)
> {
> + struct drm_i915_private *i915 = ddat->uncore->i915;
> struct i915_hwmon *hwmon = ddat->hwmon;
> + u32 uval;
>
> switch (attr) {
> case hwmon_power_max:
> return i915_mmio_reg_valid(hwmon->rg.pkg_rapl_limit) ? 0664 : 0;
> case hwmon_power_rated_max:
> return i915_mmio_reg_valid(hwmon->rg.pkg_power_sku) ? 0444 : 0;
> + case hwmon_power_crit:
> + return (hwm_pcode_read_i1(i915, &uval) ||
> + !(uval & POWER_SETUP_I1_WATTS)) ? 0 : 0644;
> default:
> return 0;
> }
> @@ -230,6 +252,8 @@ static int
> hwm_power_read(struct hwm_drvdata *ddat, u32 attr, int chan, long *val)
> {
> struct i915_hwmon *hwmon = ddat->hwmon;
> + int ret;
> + u32 uval;
>
> switch (attr) {
> case hwmon_power_max:
> @@ -248,6 +272,15 @@ hwm_power_read(struct hwm_drvdata *ddat, u32 attr, int chan, long *val)
> hwmon->scl_shift_power,
> SF_POWER);
> return 0;
> + case hwmon_power_crit:
> + ret = hwm_pcode_read_i1(ddat->uncore->i915, &uval);
> + if (ret)
> + return ret;
> + if (!(uval & POWER_SETUP_I1_WATTS))
> + return -ENODEV;
> + *val = mul_u64_u32_shr(REG_FIELD_GET(POWER_SETUP_I1_DATA_MASK, uval),
> + SF_POWER, POWER_SETUP_I1_SHIFT);
> + return 0;
> default:
> return -EOPNOTSUPP;
> }
> @@ -257,6 +290,7 @@ static int
> hwm_power_write(struct hwm_drvdata *ddat, u32 attr, int chan, long val)
> {
> struct i915_hwmon *hwmon = ddat->hwmon;
> + u32 uval;
>
> switch (attr) {
> case hwmon_power_max:
> @@ -267,6 +301,9 @@ hwm_power_write(struct hwm_drvdata *ddat, u32 attr, int chan, long val)
> hwmon->scl_shift_power,
> SF_POWER, val);
> return 0;
> + case hwmon_power_crit:
> + uval = DIV_ROUND_CLOSEST_ULL(val << POWER_SETUP_I1_SHIFT, SF_POWER);
> + return hwm_pcode_write_i1(ddat->uncore->i915, uval);
> default:
> return -EOPNOTSUPP;
> }
> @@ -298,6 +335,56 @@ hwm_energy_read(struct hwm_drvdata *ddat, u32 attr, long *val)
> }
> }
>
> +static umode_t
> +hwm_curr_is_visible(const struct hwm_drvdata *ddat, u32 attr)
> +{
> + struct drm_i915_private *i915 = ddat->uncore->i915;
> + u32 uval;
> +
> + switch (attr) {
> + case hwmon_curr_crit:
> + return (hwm_pcode_read_i1(i915, &uval) ||
> + (uval & POWER_SETUP_I1_WATTS)) ? 0 : 0644;
> + default:
> + return 0;
> + }
> +}
> +
> +static int
> +hwm_curr_read(struct hwm_drvdata *ddat, u32 attr, long *val)
> +{
> + int ret;
> + u32 uval;
> +
> + switch (attr) {
> + case hwmon_curr_crit:
> + ret = hwm_pcode_read_i1(ddat->uncore->i915, &uval);
> + if (ret)
> + return ret;
> + if (uval & POWER_SETUP_I1_WATTS)
> + return -ENODEV;
> + *val = mul_u64_u32_shr(REG_FIELD_GET(POWER_SETUP_I1_DATA_MASK, uval),
> + SF_CURR, POWER_SETUP_I1_SHIFT);
> + return 0;
> + default:
> + return -EOPNOTSUPP;
> + }
> +}
> +
> +static int
> +hwm_curr_write(struct hwm_drvdata *ddat, u32 attr, long val)
> +{
> + u32 uval;
> +
> + switch (attr) {
> + case hwmon_curr_crit:
> + uval = DIV_ROUND_CLOSEST_ULL(val << POWER_SETUP_I1_SHIFT, SF_CURR);
> + return hwm_pcode_write_i1(ddat->uncore->i915, uval);
> + default:
> + return -EOPNOTSUPP;
> + }
> +}
> +
> static umode_t
> hwm_is_visible(const void *drvdata, enum hwmon_sensor_types type,
> u32 attr, int channel)
> @@ -311,6 +398,8 @@ hwm_is_visible(const void *drvdata, enum hwmon_sensor_types type,
> return hwm_power_is_visible(ddat, attr, channel);
> case hwmon_energy:
> return hwm_energy_is_visible(ddat, attr);
> + case hwmon_curr:
> + return hwm_curr_is_visible(ddat, attr);
> default:
> return 0;
> }
> @@ -329,6 +418,8 @@ hwm_read(struct device *dev, enum hwmon_sensor_types type, u32 attr,
> return hwm_power_read(ddat, attr, channel, val);
> case hwmon_energy:
> return hwm_energy_read(ddat, attr, val);
> + case hwmon_curr:
> + return hwm_curr_read(ddat, attr, val);
> default:
> return -EOPNOTSUPP;
> }
> @@ -343,6 +434,8 @@ hwm_write(struct device *dev, enum hwmon_sensor_types type, u32 attr,
> switch (type) {
> case hwmon_power:
> return hwm_power_write(ddat, attr, channel, val);
> + case hwmon_curr:
> + return hwm_curr_write(ddat, attr, val);
> default:
> return -EOPNOTSUPP;
> }
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0bc6ae0c8bd7..041b858b95f4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6788,6 +6788,12 @@
> #define DG1_PCODE_STATUS 0x7E
> #define DG1_UNCORE_GET_INIT_STATUS 0x0
> #define DG1_UNCORE_INIT_STATUS_COMPLETE 0x1
> +#define PCODE_POWER_SETUP 0x7C
> +#define POWER_SETUP_SUBCOMMAND_READ_I1 0x4
> +#define POWER_SETUP_SUBCOMMAND_WRITE_I1 0x5
> +#define POWER_SETUP_I1_WATTS REG_BIT(31)
> +#define POWER_SETUP_I1_SHIFT 6 /* 10.6 fixed point format */
> +#define POWER_SETUP_I1_DATA_MASK REG_GENMASK(15, 0)
> #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23
> #define XEHP_PCODE_FREQUENCY_CONFIG 0x6e /* xehpsdv, pvc */
> /* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
^ permalink raw reply [flat|nested] 21+ messages in thread
* [Intel-gfx] [PATCH 6/7] drm/i915/hwmon: Expose power1_max_interval
2022-08-12 17:37 [Intel-gfx] [PATCH 0/7] drm/i915: Add HWMON support Badal Nilawar
` (4 preceding siblings ...)
2022-08-12 17:37 ` [Intel-gfx] [PATCH 5/7] drm/i915/hwmon: Expose card reactive critical power Badal Nilawar
@ 2022-08-12 17:37 ` Badal Nilawar
2022-08-12 18:10 ` Guenter Roeck
2022-08-12 17:37 ` [Intel-gfx] [PATCH 7/7] drm/i915/hwmon: Extend power/energy for XEHPSDV Badal Nilawar
` (4 subsequent siblings)
10 siblings, 1 reply; 21+ messages in thread
From: Badal Nilawar @ 2022-08-12 17:37 UTC (permalink / raw)
To: intel-gfx; +Cc: linux-hwmon, linux
From: Ashutosh Dixit <ashutosh.dixit@intel.com>
Expose power1_max_interval, that is the tau corresponding to PL1. Some bit
manipulation is needed because of the format of PKG_PWR_LIM_1_TIME in
GT0_PACKAGE_RAPL_LIMIT register (1.x * power(2,y)).
v2: Update date and kernel version in Documentation (Badal)
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
---
.../ABI/testing/sysfs-driver-intel-i915-hwmon | 9 ++
drivers/gpu/drm/i915/i915_hwmon.c | 128 +++++++++++++++++-
drivers/gpu/drm/i915/i915_reg.h | 4 +-
drivers/gpu/drm/i915/intel_mchbar_regs.h | 4 +
4 files changed, 142 insertions(+), 3 deletions(-)
diff --git a/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
index bb1101757154..34668f6c2dc4 100644
--- a/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
+++ b/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
@@ -26,6 +26,15 @@ Description: RO. Card default power limit (default TDP setting).
Only supported for particular Intel i915 graphics platforms.
+What: /sys/devices/.../hwmon/hwmon<i>/power1_max_interval
+Date: June 2022
+KernelVersion: 5.19
+Contact: dri-devel@lists.freedesktop.org
+Description: RW. Sustained power limit interval (Tau in PL1/Tau) in
+ milliseconds over which sustained power is averaged.
+
+ Only supported for particular Intel i915 graphics platforms.
+
What: /sys/devices/.../hwmon/hwmon<i>/power1_crit
Date: June 2022
KernelVersion: 5.19
diff --git a/drivers/gpu/drm/i915/i915_hwmon.c b/drivers/gpu/drm/i915/i915_hwmon.c
index b1a89a6aa220..6760133c7905 100644
--- a/drivers/gpu/drm/i915/i915_hwmon.c
+++ b/drivers/gpu/drm/i915/i915_hwmon.c
@@ -15,10 +15,12 @@
/*
* SF_* - scale factors for particular quantities according to hwmon spec.
+ * - time - milliseconds
* - power - microwatts
* - curr - milliamperes
* - energy - microjoules
*/
+#define SF_TIME 1000
#define SF_POWER 1000000
#define SF_CURR 1000
#define SF_ENERGY 1000000
@@ -56,6 +58,7 @@ struct i915_hwmon {
u32 power_max_initial_value;
int scl_shift_power;
int scl_shift_energy;
+ int scl_shift_time;
};
static void
@@ -177,6 +180,128 @@ i915_hwmon_energy_status_get(struct drm_i915_private *i915, long *energy)
return hwm_energy(ddat, energy);
}
+static ssize_t
+hwm_power1_max_interval_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct hwm_drvdata *ddat = dev_get_drvdata(dev);
+ struct i915_hwmon *hwmon = ddat->hwmon;
+ intel_wakeref_t wakeref;
+ u32 r, x, y, x_w = 2; /* 2 bits */
+ u64 tau4, out;
+
+ with_intel_runtime_pm(ddat->uncore->rpm, wakeref)
+ r = intel_uncore_read(ddat->uncore, hwmon->rg.pkg_rapl_limit);
+
+ x = REG_FIELD_GET(PKG_PWR_LIM_1_TIME_X, r);
+ y = REG_FIELD_GET(PKG_PWR_LIM_1_TIME_Y, r);
+ /*
+ * tau = 1.x * power(2,y), x = bits(23:22), y = bits(21:17)
+ * = (4 | x) << (y - 2)
+ * where (y - 2) ensures a 1.x fixed point representation of 1.x
+ * However because y can be < 2, we compute
+ * tau4 = (4 | x) << y
+ * but add 2 when doing the final right shift to account for units
+ */
+ tau4 = ((1 << x_w) | x) << y;
+ /* val in hwmon interface units (millisec) */
+ out = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time + x_w);
+
+ return sysfs_emit(buf, "%llu\n", out);
+}
+
+static ssize_t
+hwm_power1_max_interval_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct hwm_drvdata *ddat = dev_get_drvdata(dev);
+ struct i915_hwmon *hwmon = ddat->hwmon;
+ long val, max_win, ret;
+ u32 x, y, rxy, x_w = 2; /* 2 bits */
+ intel_wakeref_t wakeref;
+ u64 tau4, r;
+
+#define PKG_MAX_WIN_DEFAULT 0x12ull
+
+ ret = kstrtoul(buf, 0, &val);
+ if (ret)
+ return ret;
+
+ /* val must be < max in hwmon interface units */
+ if (i915_mmio_reg_valid(hwmon->rg.pkg_power_sku)) {
+ with_intel_runtime_pm(ddat->uncore->rpm, wakeref)
+ r = intel_uncore_read64(ddat->uncore, hwmon->rg.pkg_power_sku);
+ /*
+ * FIXME
+ * Wa_22015381490:pvc rg.pkg_power_sku value is incorrect on PVC
+ * at least. The following seems to work:
+ * r <<= 8;
+ * However for now to be safe just use the default value
+ * below. Once issue is resolved remove the one line below.
+ */
+ r = FIELD_PREP(PKG_MAX_WIN, PKG_MAX_WIN_DEFAULT);
+ } else {
+ r = FIELD_PREP(PKG_MAX_WIN, PKG_MAX_WIN_DEFAULT);
+ }
+
+ /* Steps below are explained in i915_power1_max_interval_show() */
+ x = REG_FIELD_GET(PKG_MAX_WIN_X, r);
+ y = REG_FIELD_GET(PKG_MAX_WIN_Y, r);
+ tau4 = ((1 << x_w) | x) << y;
+ max_win = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time + x_w);
+
+ if (val > max_win)
+ return -EINVAL;
+
+ /* val in hw units */
+ val = DIV_ROUND_CLOSEST_ULL((u64)val << hwmon->scl_shift_time, SF_TIME);
+ /* Convert to 1.x * power(2,y) */
+ if (!val)
+ return -EINVAL;
+ y = ilog2(val);
+ /* x = (val - (1 << y)) >> (y - 2); */
+ x = (val - (1ul << y)) << x_w >> y;
+
+ rxy = REG_FIELD_PREP(PKG_PWR_LIM_1_TIME_X, x) | REG_FIELD_PREP(PKG_PWR_LIM_1_TIME_Y, y);
+
+ hwm_locked_with_pm_intel_uncore_rmw(ddat, hwmon->rg.pkg_rapl_limit,
+ PKG_PWR_LIM_1_TIME, rxy);
+ return count;
+}
+
+static SENSOR_DEVICE_ATTR(power1_max_interval, 0664,
+ hwm_power1_max_interval_show,
+ hwm_power1_max_interval_store, 0);
+
+static struct attribute *hwm_attributes[] = {
+ &sensor_dev_attr_power1_max_interval.dev_attr.attr,
+ NULL
+};
+
+static umode_t hwm_attributes_visible(struct kobject *kobj,
+ struct attribute *attr, int index)
+{
+ struct device *dev = kobj_to_dev(kobj);
+ struct hwm_drvdata *ddat = dev_get_drvdata(dev);
+ struct i915_hwmon *hwmon = ddat->hwmon;
+
+ if (attr == &sensor_dev_attr_power1_max_interval.dev_attr.attr)
+ return i915_mmio_reg_valid(hwmon->rg.pkg_rapl_limit) ? attr->mode : 0;
+ else
+ return 0;
+}
+
+static const struct attribute_group hwm_attrgroup = {
+ .attrs = hwm_attributes,
+ .is_visible = hwm_attributes_visible,
+};
+
+static const struct attribute_group *hwm_groups[] = {
+ &hwm_attrgroup,
+ NULL
+};
+
static const struct hwmon_channel_info *hwm_info[] = {
HWMON_CHANNEL_INFO(in, HWMON_I_INPUT),
HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_CRIT),
@@ -495,6 +620,7 @@ hwm_get_preregistration_info(struct drm_i915_private *i915)
hwmon->scl_shift_power = REG_FIELD_GET(PKG_PWR_UNIT, val_sku_unit);
hwmon->scl_shift_energy = REG_FIELD_GET(PKG_ENERGY_UNIT, val_sku_unit);
+ hwmon->scl_shift_time = REG_FIELD_GET(PKG_TIME_UNIT, val_sku_unit);
/*
* Initialize 'struct hwm_energy_info', i.e. set fields to the
@@ -533,7 +659,7 @@ void i915_hwmon_register(struct drm_i915_private *i915)
hwmon_dev = hwmon_device_register_with_info(dev, ddat->name,
ddat,
&hwm_chip_info,
- NULL);
+ hwm_groups);
if (IS_ERR(hwmon_dev)) {
mutex_destroy(&hwmon->hwmon_lock);
i915->hwmon = NULL;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 041b858b95f4..05db98252a2f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1879,8 +1879,8 @@
#define PKG_MIN_PWR GENMASK_ULL(30, 16)
#define PKG_MAX_PWR GENMASK_ULL(46, 32)
#define PKG_MAX_WIN GENMASK_ULL(54, 48)
-#define PKG_MAX_WIN_Y GENMASK_ULL(54, 53)
-#define PKG_MAX_WIN_X GENMASK_ULL(52, 48)
+#define PKG_MAX_WIN_X GENMASK_ULL(54, 53)
+#define PKG_MAX_WIN_Y GENMASK_ULL(52, 48)
#define CHV_CLK_CTL1 _MMIO(0x101100)
#define VLV_CLK_CTL2 _MMIO(0x101104)
diff --git a/drivers/gpu/drm/i915/intel_mchbar_regs.h b/drivers/gpu/drm/i915/intel_mchbar_regs.h
index 18fcfc39ca2f..930cb4d76bbb 100644
--- a/drivers/gpu/drm/i915/intel_mchbar_regs.h
+++ b/drivers/gpu/drm/i915/intel_mchbar_regs.h
@@ -204,6 +204,10 @@
#define PCU_PACKAGE_RAPL_LIMIT _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x59a0)
#define PKG_PWR_LIM_1 REG_GENMASK(14, 0)
+#define PKG_PWR_LIM_1_EN REG_BIT(15)
+#define PKG_PWR_LIM_1_TIME REG_GENMASK(23, 17)
+#define PKG_PWR_LIM_1_TIME_X REG_GENMASK(23, 22)
+#define PKG_PWR_LIM_1_TIME_Y REG_GENMASK(21, 17)
/* snb MCH registers for priority tuning */
#define MCH_SSKPD _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10)
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [Intel-gfx] [PATCH 6/7] drm/i915/hwmon: Expose power1_max_interval
2022-08-12 17:37 ` [Intel-gfx] [PATCH 6/7] drm/i915/hwmon: Expose power1_max_interval Badal Nilawar
@ 2022-08-12 18:10 ` Guenter Roeck
0 siblings, 0 replies; 21+ messages in thread
From: Guenter Roeck @ 2022-08-12 18:10 UTC (permalink / raw)
To: Badal Nilawar, intel-gfx; +Cc: linux-hwmon
On 8/12/22 10:37, Badal Nilawar wrote:
> From: Ashutosh Dixit <ashutosh.dixit@intel.com>
>
> Expose power1_max_interval, that is the tau corresponding to PL1. Some bit
> manipulation is needed because of the format of PKG_PWR_LIM_1_TIME in
> GT0_PACKAGE_RAPL_LIMIT register (1.x * power(2,y)).
>
> v2: Update date and kernel version in Documentation (Badal)
>
> Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
Acked-by: Guenter Roeck <linux@roeck-us.net>
> ---
> .../ABI/testing/sysfs-driver-intel-i915-hwmon | 9 ++
> drivers/gpu/drm/i915/i915_hwmon.c | 128 +++++++++++++++++-
> drivers/gpu/drm/i915/i915_reg.h | 4 +-
> drivers/gpu/drm/i915/intel_mchbar_regs.h | 4 +
> 4 files changed, 142 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
> index bb1101757154..34668f6c2dc4 100644
> --- a/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
> +++ b/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
> @@ -26,6 +26,15 @@ Description: RO. Card default power limit (default TDP setting).
>
> Only supported for particular Intel i915 graphics platforms.
>
> +What: /sys/devices/.../hwmon/hwmon<i>/power1_max_interval
> +Date: June 2022
> +KernelVersion: 5.19
> +Contact: dri-devel@lists.freedesktop.org
> +Description: RW. Sustained power limit interval (Tau in PL1/Tau) in
> + milliseconds over which sustained power is averaged.
> +
> + Only supported for particular Intel i915 graphics platforms.
> +
> What: /sys/devices/.../hwmon/hwmon<i>/power1_crit
> Date: June 2022
> KernelVersion: 5.19
> diff --git a/drivers/gpu/drm/i915/i915_hwmon.c b/drivers/gpu/drm/i915/i915_hwmon.c
> index b1a89a6aa220..6760133c7905 100644
> --- a/drivers/gpu/drm/i915/i915_hwmon.c
> +++ b/drivers/gpu/drm/i915/i915_hwmon.c
> @@ -15,10 +15,12 @@
>
> /*
> * SF_* - scale factors for particular quantities according to hwmon spec.
> + * - time - milliseconds
> * - power - microwatts
> * - curr - milliamperes
> * - energy - microjoules
> */
> +#define SF_TIME 1000
> #define SF_POWER 1000000
> #define SF_CURR 1000
> #define SF_ENERGY 1000000
> @@ -56,6 +58,7 @@ struct i915_hwmon {
> u32 power_max_initial_value;
> int scl_shift_power;
> int scl_shift_energy;
> + int scl_shift_time;
> };
>
> static void
> @@ -177,6 +180,128 @@ i915_hwmon_energy_status_get(struct drm_i915_private *i915, long *energy)
> return hwm_energy(ddat, energy);
> }
>
> +static ssize_t
> +hwm_power1_max_interval_show(struct device *dev, struct device_attribute *attr,
> + char *buf)
> +{
> + struct hwm_drvdata *ddat = dev_get_drvdata(dev);
> + struct i915_hwmon *hwmon = ddat->hwmon;
> + intel_wakeref_t wakeref;
> + u32 r, x, y, x_w = 2; /* 2 bits */
> + u64 tau4, out;
> +
> + with_intel_runtime_pm(ddat->uncore->rpm, wakeref)
> + r = intel_uncore_read(ddat->uncore, hwmon->rg.pkg_rapl_limit);
> +
> + x = REG_FIELD_GET(PKG_PWR_LIM_1_TIME_X, r);
> + y = REG_FIELD_GET(PKG_PWR_LIM_1_TIME_Y, r);
> + /*
> + * tau = 1.x * power(2,y), x = bits(23:22), y = bits(21:17)
> + * = (4 | x) << (y - 2)
> + * where (y - 2) ensures a 1.x fixed point representation of 1.x
> + * However because y can be < 2, we compute
> + * tau4 = (4 | x) << y
> + * but add 2 when doing the final right shift to account for units
> + */
> + tau4 = ((1 << x_w) | x) << y;
> + /* val in hwmon interface units (millisec) */
> + out = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time + x_w);
> +
> + return sysfs_emit(buf, "%llu\n", out);
> +}
> +
> +static ssize_t
> +hwm_power1_max_interval_store(struct device *dev,
> + struct device_attribute *attr,
> + const char *buf, size_t count)
> +{
> + struct hwm_drvdata *ddat = dev_get_drvdata(dev);
> + struct i915_hwmon *hwmon = ddat->hwmon;
> + long val, max_win, ret;
> + u32 x, y, rxy, x_w = 2; /* 2 bits */
> + intel_wakeref_t wakeref;
> + u64 tau4, r;
> +
> +#define PKG_MAX_WIN_DEFAULT 0x12ull
> +
> + ret = kstrtoul(buf, 0, &val);
> + if (ret)
> + return ret;
> +
> + /* val must be < max in hwmon interface units */
> + if (i915_mmio_reg_valid(hwmon->rg.pkg_power_sku)) {
> + with_intel_runtime_pm(ddat->uncore->rpm, wakeref)
> + r = intel_uncore_read64(ddat->uncore, hwmon->rg.pkg_power_sku);
> + /*
> + * FIXME
> + * Wa_22015381490:pvc rg.pkg_power_sku value is incorrect on PVC
> + * at least. The following seems to work:
> + * r <<= 8;
> + * However for now to be safe just use the default value
> + * below. Once issue is resolved remove the one line below.
> + */
> + r = FIELD_PREP(PKG_MAX_WIN, PKG_MAX_WIN_DEFAULT);
> + } else {
> + r = FIELD_PREP(PKG_MAX_WIN, PKG_MAX_WIN_DEFAULT);
> + }
> +
> + /* Steps below are explained in i915_power1_max_interval_show() */
> + x = REG_FIELD_GET(PKG_MAX_WIN_X, r);
> + y = REG_FIELD_GET(PKG_MAX_WIN_Y, r);
> + tau4 = ((1 << x_w) | x) << y;
> + max_win = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time + x_w);
> +
> + if (val > max_win)
> + return -EINVAL;
> +
> + /* val in hw units */
> + val = DIV_ROUND_CLOSEST_ULL((u64)val << hwmon->scl_shift_time, SF_TIME);
> + /* Convert to 1.x * power(2,y) */
> + if (!val)
> + return -EINVAL;
> + y = ilog2(val);
> + /* x = (val - (1 << y)) >> (y - 2); */
> + x = (val - (1ul << y)) << x_w >> y;
> +
> + rxy = REG_FIELD_PREP(PKG_PWR_LIM_1_TIME_X, x) | REG_FIELD_PREP(PKG_PWR_LIM_1_TIME_Y, y);
> +
> + hwm_locked_with_pm_intel_uncore_rmw(ddat, hwmon->rg.pkg_rapl_limit,
> + PKG_PWR_LIM_1_TIME, rxy);
> + return count;
> +}
> +
> +static SENSOR_DEVICE_ATTR(power1_max_interval, 0664,
> + hwm_power1_max_interval_show,
> + hwm_power1_max_interval_store, 0);
> +
> +static struct attribute *hwm_attributes[] = {
> + &sensor_dev_attr_power1_max_interval.dev_attr.attr,
> + NULL
> +};
> +
> +static umode_t hwm_attributes_visible(struct kobject *kobj,
> + struct attribute *attr, int index)
> +{
> + struct device *dev = kobj_to_dev(kobj);
> + struct hwm_drvdata *ddat = dev_get_drvdata(dev);
> + struct i915_hwmon *hwmon = ddat->hwmon;
> +
> + if (attr == &sensor_dev_attr_power1_max_interval.dev_attr.attr)
> + return i915_mmio_reg_valid(hwmon->rg.pkg_rapl_limit) ? attr->mode : 0;
> + else
> + return 0;
> +}
> +
> +static const struct attribute_group hwm_attrgroup = {
> + .attrs = hwm_attributes,
> + .is_visible = hwm_attributes_visible,
> +};
> +
> +static const struct attribute_group *hwm_groups[] = {
> + &hwm_attrgroup,
> + NULL
> +};
> +
> static const struct hwmon_channel_info *hwm_info[] = {
> HWMON_CHANNEL_INFO(in, HWMON_I_INPUT),
> HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_CRIT),
> @@ -495,6 +620,7 @@ hwm_get_preregistration_info(struct drm_i915_private *i915)
>
> hwmon->scl_shift_power = REG_FIELD_GET(PKG_PWR_UNIT, val_sku_unit);
> hwmon->scl_shift_energy = REG_FIELD_GET(PKG_ENERGY_UNIT, val_sku_unit);
> + hwmon->scl_shift_time = REG_FIELD_GET(PKG_TIME_UNIT, val_sku_unit);
>
> /*
> * Initialize 'struct hwm_energy_info', i.e. set fields to the
> @@ -533,7 +659,7 @@ void i915_hwmon_register(struct drm_i915_private *i915)
> hwmon_dev = hwmon_device_register_with_info(dev, ddat->name,
> ddat,
> &hwm_chip_info,
> - NULL);
> + hwm_groups);
> if (IS_ERR(hwmon_dev)) {
> mutex_destroy(&hwmon->hwmon_lock);
> i915->hwmon = NULL;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 041b858b95f4..05db98252a2f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1879,8 +1879,8 @@
> #define PKG_MIN_PWR GENMASK_ULL(30, 16)
> #define PKG_MAX_PWR GENMASK_ULL(46, 32)
> #define PKG_MAX_WIN GENMASK_ULL(54, 48)
> -#define PKG_MAX_WIN_Y GENMASK_ULL(54, 53)
> -#define PKG_MAX_WIN_X GENMASK_ULL(52, 48)
> +#define PKG_MAX_WIN_X GENMASK_ULL(54, 53)
> +#define PKG_MAX_WIN_Y GENMASK_ULL(52, 48)
>
> #define CHV_CLK_CTL1 _MMIO(0x101100)
> #define VLV_CLK_CTL2 _MMIO(0x101104)
> diff --git a/drivers/gpu/drm/i915/intel_mchbar_regs.h b/drivers/gpu/drm/i915/intel_mchbar_regs.h
> index 18fcfc39ca2f..930cb4d76bbb 100644
> --- a/drivers/gpu/drm/i915/intel_mchbar_regs.h
> +++ b/drivers/gpu/drm/i915/intel_mchbar_regs.h
> @@ -204,6 +204,10 @@
>
> #define PCU_PACKAGE_RAPL_LIMIT _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x59a0)
> #define PKG_PWR_LIM_1 REG_GENMASK(14, 0)
> +#define PKG_PWR_LIM_1_EN REG_BIT(15)
> +#define PKG_PWR_LIM_1_TIME REG_GENMASK(23, 17)
> +#define PKG_PWR_LIM_1_TIME_X REG_GENMASK(23, 22)
> +#define PKG_PWR_LIM_1_TIME_Y REG_GENMASK(21, 17)
>
> /* snb MCH registers for priority tuning */
> #define MCH_SSKPD _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10)
^ permalink raw reply [flat|nested] 21+ messages in thread
* [Intel-gfx] [PATCH 7/7] drm/i915/hwmon: Extend power/energy for XEHPSDV
2022-08-12 17:37 [Intel-gfx] [PATCH 0/7] drm/i915: Add HWMON support Badal Nilawar
` (5 preceding siblings ...)
2022-08-12 17:37 ` [Intel-gfx] [PATCH 6/7] drm/i915/hwmon: Expose power1_max_interval Badal Nilawar
@ 2022-08-12 17:37 ` Badal Nilawar
2022-08-12 18:11 ` Guenter Roeck
2022-08-12 18:15 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Add HWMON support (rev3) Patchwork
` (3 subsequent siblings)
10 siblings, 1 reply; 21+ messages in thread
From: Badal Nilawar @ 2022-08-12 17:37 UTC (permalink / raw)
To: intel-gfx; +Cc: linux-hwmon, linux
From: Dale B Stimson <dale.b.stimson@intel.com>
Extend hwmon power/energy for XEHPSDV especially per gt level energy
usage.
v2: Update to latest HWMON spec (Ashutosh)
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Signed-off-by: Dale B Stimson <dale.b.stimson@intel.com>
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
---
.../ABI/testing/sysfs-driver-intel-i915-hwmon | 7 +-
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 5 +
drivers/gpu/drm/i915/i915_hwmon.c | 120 +++++++++++++++++-
3 files changed, 128 insertions(+), 4 deletions(-)
diff --git a/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
index 34668f6c2dc4..e69bc43d4c9e 100644
--- a/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
+++ b/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
@@ -65,6 +65,11 @@ What: /sys/devices/.../hwmon/hwmon<i>/energy1_input
Date: June 2022
KernelVersion: 5.19
Contact: dri-devel@lists.freedesktop.org
-Description: RO. Energy input of device in microjoules.
+Description: RO. Energy input of device or gt in microjoules.
+
+ For i915 device level hwmon devices (name "i915") this
+ reflects energy input for the entire device. For gt level
+ hwmon devices (name "i915_gtN") this reflects energy input
+ for the gt.
Only supported for particular Intel i915 graphics platforms.
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 4604f6dbf8b6..dc3bc07cdd24 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1569,4 +1569,9 @@
#define GEN12_SFC_DONE(n) _MMIO(0x1cc000 + (n) * 0x1000)
+#define GT0_PACKAGE_ENERGY_STATUS _MMIO(0x250004)
+#define GT0_PACKAGE_RAPL_LIMIT _MMIO(0x250008)
+#define GT0_PACKAGE_POWER_SKU_UNIT _MMIO(0x250068)
+#define GT0_PLATFORM_ENERGY_STATUS _MMIO(0x25006c)
+
#endif /* __INTEL_GT_REGS__ */
diff --git a/drivers/gpu/drm/i915/i915_hwmon.c b/drivers/gpu/drm/i915/i915_hwmon.c
index 6760133c7905..4c2e8d3cfe52 100644
--- a/drivers/gpu/drm/i915/i915_hwmon.c
+++ b/drivers/gpu/drm/i915/i915_hwmon.c
@@ -11,6 +11,7 @@
#include "i915_hwmon.h"
#include "intel_mchbar_regs.h"
#include "intel_pcode.h"
+#include "gt/intel_gt.h"
#include "gt/intel_gt_regs.h"
/*
@@ -20,7 +21,7 @@
* - curr - milliamperes
* - energy - microjoules
*/
-#define SF_TIME 1000
+#define SF_TIME 1000
#define SF_POWER 1000000
#define SF_CURR 1000
#define SF_ENERGY 1000000
@@ -36,6 +37,7 @@ struct hwm_reg {
i915_reg_t pkg_power_sku;
i915_reg_t pkg_rapl_limit;
i915_reg_t energy_status_all;
+ i915_reg_t energy_status_tile;
};
struct hwm_energy_info {
@@ -49,10 +51,12 @@ struct hwm_drvdata {
struct device *hwmon_dev;
struct hwm_energy_info ei; /* Energy info for energy1_input */
char name[12];
+ int gt_n;
};
struct i915_hwmon {
struct hwm_drvdata ddat;
+ struct hwm_drvdata ddat_gt[I915_MAX_GT];
struct mutex hwmon_lock; /* counter overflow logic and rmw */
struct hwm_reg rg;
u32 power_max_initial_value;
@@ -148,7 +152,10 @@ hwm_energy(struct hwm_drvdata *ddat, long *energy)
i915_reg_t rgaddr;
u32 reg_val;
- rgaddr = hwmon->rg.energy_status_all;
+ if (ddat->gt_n >= 0)
+ rgaddr = hwmon->rg.energy_status_tile;
+ else
+ rgaddr = hwmon->rg.energy_status_all;
if (!i915_mmio_reg_valid(rgaddr))
return -EOPNOTSUPP;
@@ -310,6 +317,11 @@ static const struct hwmon_channel_info *hwm_info[] = {
NULL
};
+static const struct hwmon_channel_info *hwm_gt_info[] = {
+ HWMON_CHANNEL_INFO(energy, HWMON_E_INPUT),
+ NULL
+};
+
/* I1 is exposed as power_crit or as curr_crit depending on bit 31 */
static int hwm_pcode_read_i1(struct drm_i915_private *i915, u32 *uval)
{
@@ -442,7 +454,10 @@ hwm_energy_is_visible(const struct hwm_drvdata *ddat, u32 attr)
switch (attr) {
case hwmon_energy_input:
- rgaddr = hwmon->rg.energy_status_all;
+ if (ddat->gt_n >= 0)
+ rgaddr = hwmon->rg.energy_status_tile;
+ else
+ rgaddr = hwmon->rg.energy_status_all;
return i915_mmio_reg_valid(rgaddr) ? 0444 : 0;
default:
return 0;
@@ -577,6 +592,44 @@ static const struct hwmon_chip_info hwm_chip_info = {
.info = hwm_info,
};
+static umode_t
+hwm_gt_is_visible(const void *drvdata, enum hwmon_sensor_types type,
+ u32 attr, int channel)
+{
+ struct hwm_drvdata *ddat = (struct hwm_drvdata *)drvdata;
+
+ switch (type) {
+ case hwmon_energy:
+ return hwm_energy_is_visible(ddat, attr);
+ default:
+ return 0;
+ }
+}
+
+static int
+hwm_gt_read(struct device *dev, enum hwmon_sensor_types type, u32 attr,
+ int channel, long *val)
+{
+ struct hwm_drvdata *ddat = dev_get_drvdata(dev);
+
+ switch (type) {
+ case hwmon_energy:
+ return hwm_energy_read(ddat, attr, val);
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
+static const struct hwmon_ops hwm_gt_ops = {
+ .is_visible = hwm_gt_is_visible,
+ .read = hwm_gt_read,
+};
+
+static const struct hwmon_chip_info hwm_gt_chip_info = {
+ .ops = &hwm_gt_ops,
+ .info = hwm_gt_info,
+};
+
static void
hwm_get_preregistration_info(struct drm_i915_private *i915)
{
@@ -585,7 +638,9 @@ hwm_get_preregistration_info(struct drm_i915_private *i915)
struct hwm_drvdata *ddat = &hwmon->ddat;
intel_wakeref_t wakeref;
u32 val_sku_unit;
+ struct intel_gt *gt;
long energy;
+ int i;
if (IS_DG1(i915) || IS_DG2(i915)) {
hwmon->rg.gt_perf_status = GEN12_RPSTAT1;
@@ -593,12 +648,21 @@ hwm_get_preregistration_info(struct drm_i915_private *i915)
hwmon->rg.pkg_power_sku = INVALID_MMIO_REG;
hwmon->rg.pkg_rapl_limit = PCU_PACKAGE_RAPL_LIMIT;
hwmon->rg.energy_status_all = PCU_PACKAGE_ENERGY_STATUS;
+ hwmon->rg.energy_status_tile = INVALID_MMIO_REG;
+ } else if (IS_XEHPSDV(i915)) {
+ hwmon->rg.pkg_power_sku_unit = GT0_PACKAGE_POWER_SKU_UNIT;
+ hwmon->rg.pkg_power_sku = INVALID_MMIO_REG;
+ hwmon->rg.pkg_rapl_limit = GT0_PACKAGE_RAPL_LIMIT;
+ hwmon->rg.energy_status_all = GT0_PLATFORM_ENERGY_STATUS;
+ hwmon->rg.energy_status_tile = GT0_PACKAGE_ENERGY_STATUS;
+ hwmon->rg.gt_perf_status = INVALID_MMIO_REG;
} else {
hwmon->rg.gt_perf_status = INVALID_MMIO_REG;
hwmon->rg.pkg_power_sku_unit = INVALID_MMIO_REG;
hwmon->rg.pkg_power_sku = INVALID_MMIO_REG;
hwmon->rg.pkg_rapl_limit = INVALID_MMIO_REG;
hwmon->rg.energy_status_all = INVALID_MMIO_REG;
+ hwmon->rg.energy_status_tile = INVALID_MMIO_REG;
}
with_intel_runtime_pm(uncore->rpm, wakeref) {
@@ -628,6 +692,10 @@ hwm_get_preregistration_info(struct drm_i915_private *i915)
*/
if (i915_mmio_reg_valid(hwmon->rg.energy_status_all))
hwm_energy(ddat, &energy);
+ if (i915_mmio_reg_valid(hwmon->rg.energy_status_tile)) {
+ for_each_gt(gt, i915, i)
+ hwm_energy(&hwmon->ddat_gt[i], &energy);
+ }
}
void i915_hwmon_register(struct drm_i915_private *i915)
@@ -636,6 +704,10 @@ void i915_hwmon_register(struct drm_i915_private *i915)
struct i915_hwmon *hwmon;
struct device *hwmon_dev;
struct hwm_drvdata *ddat;
+ struct hwm_drvdata *ddat_gt;
+ struct intel_gt *gt;
+ const char *ddname;
+ int i;
/* hwmon is available only for dGfx */
if (!IS_DGFX(i915))
@@ -652,6 +724,16 @@ void i915_hwmon_register(struct drm_i915_private *i915)
ddat->hwmon = hwmon;
ddat->uncore = &i915->uncore;
snprintf(ddat->name, sizeof(ddat->name), "i915");
+ ddat->gt_n = -1;
+
+ for_each_gt(gt, i915, i) {
+ ddat_gt = hwmon->ddat_gt + i;
+
+ ddat_gt->hwmon = hwmon;
+ ddat_gt->uncore = gt->uncore;
+ snprintf(ddat_gt->name, sizeof(ddat_gt->name), "i915_gt%u", i);
+ ddat_gt->gt_n = i;
+ }
hwm_get_preregistration_info(i915);
@@ -668,18 +750,50 @@ void i915_hwmon_register(struct drm_i915_private *i915)
}
ddat->hwmon_dev = hwmon_dev;
+
+ for_each_gt(gt, i915, i) {
+ ddat_gt = hwmon->ddat_gt + i;
+ /*
+ * Create per-gt directories only if a per-gt attribute is
+ * visible. Currently this is only energy
+ */
+ if (!hwm_gt_is_visible(ddat_gt, hwmon_energy, hwmon_energy_input, 0))
+ continue;
+
+ ddname = ddat_gt->name;
+ hwmon_dev = hwmon_device_register_with_info(dev, ddname,
+ ddat_gt,
+ &hwm_gt_chip_info,
+ NULL);
+ if (!IS_ERR(hwmon_dev))
+ ddat_gt->hwmon_dev = hwmon_dev;
+ }
}
void i915_hwmon_unregister(struct drm_i915_private *i915)
{
struct i915_hwmon *hwmon;
struct hwm_drvdata *ddat;
+ struct intel_gt *gt;
+ int i;
hwmon = fetch_and_zero(&i915->hwmon);
if (!hwmon)
return;
ddat = &hwmon->ddat;
+
+ for_each_gt(gt, i915, i) {
+ struct hwm_drvdata *ddat_gt;
+
+ ddat_gt = hwmon->ddat_gt + i;
+
+ if (ddat_gt->hwmon_dev) {
+ hwmon_device_unregister(ddat_gt->hwmon_dev);
+ ddat_gt->hwmon_dev = NULL;
+ }
+ }
+
if (ddat->hwmon_dev)
hwmon_device_unregister(ddat->hwmon_dev);
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [Intel-gfx] [PATCH 7/7] drm/i915/hwmon: Extend power/energy for XEHPSDV
2022-08-12 17:37 ` [Intel-gfx] [PATCH 7/7] drm/i915/hwmon: Extend power/energy for XEHPSDV Badal Nilawar
@ 2022-08-12 18:11 ` Guenter Roeck
0 siblings, 0 replies; 21+ messages in thread
From: Guenter Roeck @ 2022-08-12 18:11 UTC (permalink / raw)
To: Badal Nilawar, intel-gfx; +Cc: linux-hwmon
On 8/12/22 10:37, Badal Nilawar wrote:
> From: Dale B Stimson <dale.b.stimson@intel.com>
>
> Extend hwmon power/energy for XEHPSDV especially per gt level energy
> usage.
>
> v2: Update to latest HWMON spec (Ashutosh)
>
> Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
> Signed-off-by: Dale B Stimson <dale.b.stimson@intel.com>
> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
Acked-by: Guenter Roeck <linux@roeck-us.net>
> ---
> .../ABI/testing/sysfs-driver-intel-i915-hwmon | 7 +-
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 5 +
> drivers/gpu/drm/i915/i915_hwmon.c | 120 +++++++++++++++++-
> 3 files changed, 128 insertions(+), 4 deletions(-)
>
> diff --git a/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
> index 34668f6c2dc4..e69bc43d4c9e 100644
> --- a/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
> +++ b/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
> @@ -65,6 +65,11 @@ What: /sys/devices/.../hwmon/hwmon<i>/energy1_input
> Date: June 2022
> KernelVersion: 5.19
> Contact: dri-devel@lists.freedesktop.org
> -Description: RO. Energy input of device in microjoules.
> +Description: RO. Energy input of device or gt in microjoules.
> +
> + For i915 device level hwmon devices (name "i915") this
> + reflects energy input for the entire device. For gt level
> + hwmon devices (name "i915_gtN") this reflects energy input
> + for the gt.
>
> Only supported for particular Intel i915 graphics platforms.
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 4604f6dbf8b6..dc3bc07cdd24 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -1569,4 +1569,9 @@
>
> #define GEN12_SFC_DONE(n) _MMIO(0x1cc000 + (n) * 0x1000)
>
> +#define GT0_PACKAGE_ENERGY_STATUS _MMIO(0x250004)
> +#define GT0_PACKAGE_RAPL_LIMIT _MMIO(0x250008)
> +#define GT0_PACKAGE_POWER_SKU_UNIT _MMIO(0x250068)
> +#define GT0_PLATFORM_ENERGY_STATUS _MMIO(0x25006c)
> +
> #endif /* __INTEL_GT_REGS__ */
> diff --git a/drivers/gpu/drm/i915/i915_hwmon.c b/drivers/gpu/drm/i915/i915_hwmon.c
> index 6760133c7905..4c2e8d3cfe52 100644
> --- a/drivers/gpu/drm/i915/i915_hwmon.c
> +++ b/drivers/gpu/drm/i915/i915_hwmon.c
> @@ -11,6 +11,7 @@
> #include "i915_hwmon.h"
> #include "intel_mchbar_regs.h"
> #include "intel_pcode.h"
> +#include "gt/intel_gt.h"
> #include "gt/intel_gt_regs.h"
>
> /*
> @@ -20,7 +21,7 @@
> * - curr - milliamperes
> * - energy - microjoules
> */
> -#define SF_TIME 1000
> +#define SF_TIME 1000
> #define SF_POWER 1000000
> #define SF_CURR 1000
> #define SF_ENERGY 1000000
> @@ -36,6 +37,7 @@ struct hwm_reg {
> i915_reg_t pkg_power_sku;
> i915_reg_t pkg_rapl_limit;
> i915_reg_t energy_status_all;
> + i915_reg_t energy_status_tile;
> };
>
> struct hwm_energy_info {
> @@ -49,10 +51,12 @@ struct hwm_drvdata {
> struct device *hwmon_dev;
> struct hwm_energy_info ei; /* Energy info for energy1_input */
> char name[12];
> + int gt_n;
> };
>
> struct i915_hwmon {
> struct hwm_drvdata ddat;
> + struct hwm_drvdata ddat_gt[I915_MAX_GT];
> struct mutex hwmon_lock; /* counter overflow logic and rmw */
> struct hwm_reg rg;
> u32 power_max_initial_value;
> @@ -148,7 +152,10 @@ hwm_energy(struct hwm_drvdata *ddat, long *energy)
> i915_reg_t rgaddr;
> u32 reg_val;
>
> - rgaddr = hwmon->rg.energy_status_all;
> + if (ddat->gt_n >= 0)
> + rgaddr = hwmon->rg.energy_status_tile;
> + else
> + rgaddr = hwmon->rg.energy_status_all;
>
> if (!i915_mmio_reg_valid(rgaddr))
> return -EOPNOTSUPP;
> @@ -310,6 +317,11 @@ static const struct hwmon_channel_info *hwm_info[] = {
> NULL
> };
>
> +static const struct hwmon_channel_info *hwm_gt_info[] = {
> + HWMON_CHANNEL_INFO(energy, HWMON_E_INPUT),
> + NULL
> +};
> +
> /* I1 is exposed as power_crit or as curr_crit depending on bit 31 */
> static int hwm_pcode_read_i1(struct drm_i915_private *i915, u32 *uval)
> {
> @@ -442,7 +454,10 @@ hwm_energy_is_visible(const struct hwm_drvdata *ddat, u32 attr)
>
> switch (attr) {
> case hwmon_energy_input:
> - rgaddr = hwmon->rg.energy_status_all;
> + if (ddat->gt_n >= 0)
> + rgaddr = hwmon->rg.energy_status_tile;
> + else
> + rgaddr = hwmon->rg.energy_status_all;
> return i915_mmio_reg_valid(rgaddr) ? 0444 : 0;
> default:
> return 0;
> @@ -577,6 +592,44 @@ static const struct hwmon_chip_info hwm_chip_info = {
> .info = hwm_info,
> };
>
> +static umode_t
> +hwm_gt_is_visible(const void *drvdata, enum hwmon_sensor_types type,
> + u32 attr, int channel)
> +{
> + struct hwm_drvdata *ddat = (struct hwm_drvdata *)drvdata;
> +
> + switch (type) {
> + case hwmon_energy:
> + return hwm_energy_is_visible(ddat, attr);
> + default:
> + return 0;
> + }
> +}
> +
> +static int
> +hwm_gt_read(struct device *dev, enum hwmon_sensor_types type, u32 attr,
> + int channel, long *val)
> +{
> + struct hwm_drvdata *ddat = dev_get_drvdata(dev);
> +
> + switch (type) {
> + case hwmon_energy:
> + return hwm_energy_read(ddat, attr, val);
> + default:
> + return -EOPNOTSUPP;
> + }
> +}
> +
> +static const struct hwmon_ops hwm_gt_ops = {
> + .is_visible = hwm_gt_is_visible,
> + .read = hwm_gt_read,
> +};
> +
> +static const struct hwmon_chip_info hwm_gt_chip_info = {
> + .ops = &hwm_gt_ops,
> + .info = hwm_gt_info,
> +};
> +
> static void
> hwm_get_preregistration_info(struct drm_i915_private *i915)
> {
> @@ -585,7 +638,9 @@ hwm_get_preregistration_info(struct drm_i915_private *i915)
> struct hwm_drvdata *ddat = &hwmon->ddat;
> intel_wakeref_t wakeref;
> u32 val_sku_unit;
> + struct intel_gt *gt;
> long energy;
> + int i;
>
> if (IS_DG1(i915) || IS_DG2(i915)) {
> hwmon->rg.gt_perf_status = GEN12_RPSTAT1;
> @@ -593,12 +648,21 @@ hwm_get_preregistration_info(struct drm_i915_private *i915)
> hwmon->rg.pkg_power_sku = INVALID_MMIO_REG;
> hwmon->rg.pkg_rapl_limit = PCU_PACKAGE_RAPL_LIMIT;
> hwmon->rg.energy_status_all = PCU_PACKAGE_ENERGY_STATUS;
> + hwmon->rg.energy_status_tile = INVALID_MMIO_REG;
> + } else if (IS_XEHPSDV(i915)) {
> + hwmon->rg.pkg_power_sku_unit = GT0_PACKAGE_POWER_SKU_UNIT;
> + hwmon->rg.pkg_power_sku = INVALID_MMIO_REG;
> + hwmon->rg.pkg_rapl_limit = GT0_PACKAGE_RAPL_LIMIT;
> + hwmon->rg.energy_status_all = GT0_PLATFORM_ENERGY_STATUS;
> + hwmon->rg.energy_status_tile = GT0_PACKAGE_ENERGY_STATUS;
> + hwmon->rg.gt_perf_status = INVALID_MMIO_REG;
> } else {
> hwmon->rg.gt_perf_status = INVALID_MMIO_REG;
> hwmon->rg.pkg_power_sku_unit = INVALID_MMIO_REG;
> hwmon->rg.pkg_power_sku = INVALID_MMIO_REG;
> hwmon->rg.pkg_rapl_limit = INVALID_MMIO_REG;
> hwmon->rg.energy_status_all = INVALID_MMIO_REG;
> + hwmon->rg.energy_status_tile = INVALID_MMIO_REG;
> }
>
> with_intel_runtime_pm(uncore->rpm, wakeref) {
> @@ -628,6 +692,10 @@ hwm_get_preregistration_info(struct drm_i915_private *i915)
> */
> if (i915_mmio_reg_valid(hwmon->rg.energy_status_all))
> hwm_energy(ddat, &energy);
> + if (i915_mmio_reg_valid(hwmon->rg.energy_status_tile)) {
> + for_each_gt(gt, i915, i)
> + hwm_energy(&hwmon->ddat_gt[i], &energy);
> + }
> }
>
> void i915_hwmon_register(struct drm_i915_private *i915)
> @@ -636,6 +704,10 @@ void i915_hwmon_register(struct drm_i915_private *i915)
> struct i915_hwmon *hwmon;
> struct device *hwmon_dev;
> struct hwm_drvdata *ddat;
> + struct hwm_drvdata *ddat_gt;
> + struct intel_gt *gt;
> + const char *ddname;
> + int i;
>
> /* hwmon is available only for dGfx */
> if (!IS_DGFX(i915))
> @@ -652,6 +724,16 @@ void i915_hwmon_register(struct drm_i915_private *i915)
> ddat->hwmon = hwmon;
> ddat->uncore = &i915->uncore;
> snprintf(ddat->name, sizeof(ddat->name), "i915");
> + ddat->gt_n = -1;
> +
> + for_each_gt(gt, i915, i) {
> + ddat_gt = hwmon->ddat_gt + i;
> +
> + ddat_gt->hwmon = hwmon;
> + ddat_gt->uncore = gt->uncore;
> + snprintf(ddat_gt->name, sizeof(ddat_gt->name), "i915_gt%u", i);
> + ddat_gt->gt_n = i;
> + }
>
> hwm_get_preregistration_info(i915);
>
> @@ -668,18 +750,50 @@ void i915_hwmon_register(struct drm_i915_private *i915)
> }
>
> ddat->hwmon_dev = hwmon_dev;
> +
> + for_each_gt(gt, i915, i) {
> + ddat_gt = hwmon->ddat_gt + i;
> + /*
> + * Create per-gt directories only if a per-gt attribute is
> + * visible. Currently this is only energy
> + */
> + if (!hwm_gt_is_visible(ddat_gt, hwmon_energy, hwmon_energy_input, 0))
> + continue;
> +
> + ddname = ddat_gt->name;
> + hwmon_dev = hwmon_device_register_with_info(dev, ddname,
> + ddat_gt,
> + &hwm_gt_chip_info,
> + NULL);
> + if (!IS_ERR(hwmon_dev))
> + ddat_gt->hwmon_dev = hwmon_dev;
> + }
> }
>
> void i915_hwmon_unregister(struct drm_i915_private *i915)
> {
> struct i915_hwmon *hwmon;
> struct hwm_drvdata *ddat;
> + struct intel_gt *gt;
> + int i;
>
> hwmon = fetch_and_zero(&i915->hwmon);
> if (!hwmon)
> return;
>
> ddat = &hwmon->ddat;
> +
> + for_each_gt(gt, i915, i) {
> + struct hwm_drvdata *ddat_gt;
> +
> + ddat_gt = hwmon->ddat_gt + i;
> +
> + if (ddat_gt->hwmon_dev) {
> + hwmon_device_unregister(ddat_gt->hwmon_dev);
> + ddat_gt->hwmon_dev = NULL;
> + }
> + }
> +
> if (ddat->hwmon_dev)
> hwmon_device_unregister(ddat->hwmon_dev);
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Add HWMON support (rev3)
2022-08-12 17:37 [Intel-gfx] [PATCH 0/7] drm/i915: Add HWMON support Badal Nilawar
` (6 preceding siblings ...)
2022-08-12 17:37 ` [Intel-gfx] [PATCH 7/7] drm/i915/hwmon: Extend power/energy for XEHPSDV Badal Nilawar
@ 2022-08-12 18:15 ` Patchwork
2022-08-12 18:15 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
10 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2022-08-12 18:15 UTC (permalink / raw)
To: Badal Nilawar; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Add HWMON support (rev3)
URL : https://patchwork.freedesktop.org/series/104278/
State : warning
== Summary ==
Error: dim checkpatch failed
1de65e10c7ff drm/i915/hwmon: Add HWMON infrastructure
Traceback (most recent call last):
File "scripts/spdxcheck.py", line 11, in <module>
import git
ModuleNotFoundError: No module named 'git'
Traceback (most recent call last):
File "scripts/spdxcheck.py", line 11, in <module>
import git
ModuleNotFoundError: No module named 'git'
-:81: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#81:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 197 lines checked
bd255119218f drm/i915/hwmon: Add HWMON current voltage support
-:23: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#23:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 98 lines checked
76f73f1465a1 drm/i915/hwmon: Power PL1 limit and TDP setting
-:70: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__mask' - possible side-effects?
#70: FILE: drivers/gpu/drm/i915/i915_hwmon.c:21:
+#define FIELD_SHIFT(__mask) \
+ (BUILD_BUG_ON_ZERO(!__builtin_constant_p(__mask)) + \
+ BUILD_BUG_ON_ZERO((__mask) == 0) + \
+ __bf_shf(__mask))
total: 0 errors, 0 warnings, 1 checks, 292 lines checked
0ca509ffa1ae drm/i915/hwmon: Show device level energy usage
543c91fde2e1 drm/i915/hwmon: Expose card reactive critical power
f027f0c2de33 drm/i915/hwmon: Expose power1_max_interval
0868fe54f0a0 drm/i915/hwmon: Extend power/energy for XEHPSDV
^ permalink raw reply [flat|nested] 21+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Add HWMON support (rev3)
2022-08-12 17:37 [Intel-gfx] [PATCH 0/7] drm/i915: Add HWMON support Badal Nilawar
` (7 preceding siblings ...)
2022-08-12 18:15 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Add HWMON support (rev3) Patchwork
@ 2022-08-12 18:15 ` Patchwork
2022-08-12 18:38 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-08-13 0:27 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
10 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2022-08-12 18:15 UTC (permalink / raw)
To: Badal Nilawar; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Add HWMON support (rev3)
URL : https://patchwork.freedesktop.org/series/104278/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 21+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Add HWMON support (rev3)
2022-08-12 17:37 [Intel-gfx] [PATCH 0/7] drm/i915: Add HWMON support Badal Nilawar
` (8 preceding siblings ...)
2022-08-12 18:15 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2022-08-12 18:38 ` Patchwork
2022-08-13 0:27 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
10 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2022-08-12 18:38 UTC (permalink / raw)
To: Badal Nilawar; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 7595 bytes --]
== Series Details ==
Series: drm/i915: Add HWMON support (rev3)
URL : https://patchwork.freedesktop.org/series/104278/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11986 -> Patchwork_104278v3
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/index.html
Participating hosts (38 -> 39)
------------------------------
Additional (1): bat-adln-1
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_104278v3:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_pm_rpm@module-reload:
- {bat-dg2-10}: NOTRUN -> [DMESG-WARN][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/bat-dg2-10/igt@i915_pm_rpm@module-reload.html
Known issues
------------
Here are the changes found in Patchwork_104278v3 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@gem:
- fi-blb-e6850: NOTRUN -> [DMESG-FAIL][2] ([i915#4528])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/fi-blb-e6850/igt@i915_selftest@live@gem.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-g3258: [PASS][3] -> [INCOMPLETE][4] ([i915#3303] / [i915#4785])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/fi-hsw-g3258/igt@i915_selftest@live@hangcheck.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/fi-hsw-g3258/igt@i915_selftest@live@hangcheck.html
- bat-dg1-5: [PASS][5] -> [DMESG-FAIL][6] ([i915#4494] / [i915#4957])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/bat-dg1-5/igt@i915_selftest@live@hangcheck.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/bat-dg1-5/igt@i915_selftest@live@hangcheck.html
* igt@runner@aborted:
- fi-hsw-g3258: NOTRUN -> [FAIL][7] ([fdo#109271] / [i915#4312] / [i915#6246])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/fi-hsw-g3258/igt@runner@aborted.html
#### Possible fixes ####
* igt@core_hotunplug@unbind-rebind:
- {bat-dg2-10}: [DMESG-WARN][8] -> [PASS][9]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/bat-dg2-10/igt@core_hotunplug@unbind-rebind.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/bat-dg2-10/igt@core_hotunplug@unbind-rebind.html
* igt@gem_exec_suspend@basic-s0@smem:
- {bat-adlm-1}: [DMESG-WARN][10] ([i915#2867]) -> [PASS][11] +1 similar issue
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/bat-adlm-1/igt@gem_exec_suspend@basic-s0@smem.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/bat-adlm-1/igt@gem_exec_suspend@basic-s0@smem.html
* igt@i915_selftest@live@requests:
- fi-blb-e6850: [DMESG-FAIL][12] ([i915#4528]) -> [PASS][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/fi-blb-e6850/igt@i915_selftest@live@requests.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/fi-blb-e6850/igt@i915_selftest@live@requests.html
- {bat-rpls-1}: [DMESG-FAIL][14] ([i915#5087] / [i915#6257]) -> [PASS][15]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/bat-rpls-1/igt@i915_selftest@live@requests.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/bat-rpls-1/igt@i915_selftest@live@requests.html
* igt@i915_selftest@live@reset:
- {bat-rpls-1}: [DMESG-FAIL][16] ([i915#4983]) -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/bat-rpls-1/igt@i915_selftest@live@reset.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/bat-rpls-1/igt@i915_selftest@live@reset.html
* igt@kms_frontbuffer_tracking@basic:
- {bat-rpls-2}: [SKIP][18] ([i915#1849]) -> [PASS][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/bat-rpls-2/igt@kms_frontbuffer_tracking@basic.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/bat-rpls-2/igt@kms_frontbuffer_tracking@basic.html
* igt@prime_vgem@basic-fence-flip:
- {bat-rpls-2}: [SKIP][20] ([fdo#109295] / [i915#1845] / [i915#3708]) -> [PASS][21]
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/bat-rpls-2/igt@prime_vgem@basic-fence-flip.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/bat-rpls-2/igt@prime_vgem@basic-fence-flip.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
[i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5087]: https://gitlab.freedesktop.org/drm/intel/issues/5087
[i915#5950]: https://gitlab.freedesktop.org/drm/intel/issues/5950
[i915#6246]: https://gitlab.freedesktop.org/drm/intel/issues/6246
[i915#6257]: https://gitlab.freedesktop.org/drm/intel/issues/6257
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
Build changes
-------------
* Linux: CI_DRM_11986 -> Patchwork_104278v3
CI-20190529: 20190529
CI_DRM_11986: 1cb5379e17f93685065d8ec54444f1baf9386ffe @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6623: c8edfca649da71b296d882bb0319181d94e619eb @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_104278v3: 1cb5379e17f93685065d8ec54444f1baf9386ffe @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
4f21165bc6ba drm/i915/hwmon: Extend power/energy for XEHPSDV
6ff57cfe781f drm/i915/hwmon: Expose power1_max_interval
73041076ed86 drm/i915/hwmon: Expose card reactive critical power
e9b44e5a4ac3 drm/i915/hwmon: Show device level energy usage
970d727d12bd drm/i915/hwmon: Power PL1 limit and TDP setting
38b3453db612 drm/i915/hwmon: Add HWMON current voltage support
71e0b729e5d1 drm/i915/hwmon: Add HWMON infrastructure
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/index.html
[-- Attachment #2: Type: text/html, Size: 7833 bytes --]
^ permalink raw reply [flat|nested] 21+ messages in thread* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Add HWMON support (rev3)
2022-08-12 17:37 [Intel-gfx] [PATCH 0/7] drm/i915: Add HWMON support Badal Nilawar
` (9 preceding siblings ...)
2022-08-12 18:38 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2022-08-13 0:27 ` Patchwork
10 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2022-08-13 0:27 UTC (permalink / raw)
To: Badal Nilawar; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 41330 bytes --]
== Series Details ==
Series: drm/i915: Add HWMON support (rev3)
URL : https://patchwork.freedesktop.org/series/104278/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11986_full -> Patchwork_104278v3_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_104278v3_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_104278v3_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (13 -> 13)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_104278v3_full:
### IGT changes ###
#### Possible regressions ####
* igt@i915_pm_rpm@cursor:
- shard-iclb: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-iclb2/igt@i915_pm_rpm@cursor.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-iclb4/igt@i915_pm_rpm@cursor.html
Known issues
------------
Here are the changes found in Patchwork_104278v3_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_exec@basic-nohangcheck:
- shard-tglb: [PASS][3] -> [FAIL][4] ([i915#6268])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-tglb3/igt@gem_ctx_exec@basic-nohangcheck.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-tglb5/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_ctx_isolation@preservation-s3@vcs0:
- shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([i915#180]) +6 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-kbl7/igt@gem_ctx_isolation@preservation-s3@vcs0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-kbl7/igt@gem_ctx_isolation@preservation-s3@vcs0.html
* igt@gem_eio@in-flight-10ms:
- shard-tglb: [PASS][7] -> [TIMEOUT][8] ([i915#3063])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-tglb7/igt@gem_eio@in-flight-10ms.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-tglb3/igt@gem_eio@in-flight-10ms.html
* igt@gem_eio@kms:
- shard-tglb: [PASS][9] -> [FAIL][10] ([i915#5784])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-tglb7/igt@gem_eio@kms.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-tglb2/igt@gem_eio@kms.html
* igt@gem_exec_balancer@parallel-contexts:
- shard-iclb: [PASS][11] -> [SKIP][12] ([i915#4525]) +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-iclb4/igt@gem_exec_balancer@parallel-contexts.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-iclb8/igt@gem_exec_balancer@parallel-contexts.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][13] -> [FAIL][14] ([i915#2842])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-glk5/igt@gem_exec_fair@basic-pace-share@rcs0.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-glk1/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@bcs0:
- shard-iclb: [PASS][15] -> [FAIL][16] ([i915#2842]) +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-iclb2/igt@gem_exec_fair@basic-pace@bcs0.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-iclb4/igt@gem_exec_fair@basic-pace@bcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-kbl: [PASS][17] -> [SKIP][18] ([fdo#109271])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-kbl7/igt@gem_exec_fair@basic-pace@vecs0.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-kbl4/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][19] -> [FAIL][20] ([i915#2849])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-iclb4/igt@gem_exec_fair@basic-throttle@rcs0.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-iclb3/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_params@no-blt:
- shard-kbl: NOTRUN -> [SKIP][21] ([fdo#109271]) +11 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-kbl4/igt@gem_exec_params@no-blt.html
* igt@gem_lmem_swapping@parallel-random-engines:
- shard-glk: NOTRUN -> [SKIP][22] ([fdo#109271] / [i915#4613])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-glk5/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@gem_pread@exhaustion:
- shard-apl: NOTRUN -> [WARN][23] ([i915#2658])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-apl6/igt@gem_pread@exhaustion.html
* igt@gem_pxp@create-regular-context-2:
- shard-apl: NOTRUN -> [SKIP][24] ([fdo#109271]) +53 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-apl8/igt@gem_pxp@create-regular-context-2.html
* igt@gem_workarounds@suspend-resume-fd:
- shard-skl: [PASS][25] -> [INCOMPLETE][26] ([i915#5129])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-skl10/igt@gem_workarounds@suspend-resume-fd.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-skl4/igt@gem_workarounds@suspend-resume-fd.html
* igt@i915_pm_dc@dc6-dpms:
- shard-iclb: [PASS][27] -> [FAIL][28] ([i915#454])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-iclb8/igt@i915_pm_dc@dc6-dpms.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_suspend@sysfs-reader:
- shard-apl: [PASS][29] -> [DMESG-WARN][30] ([i915#180]) +1 similar issue
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-apl6/igt@i915_suspend@sysfs-reader.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-apl4/igt@i915_suspend@sysfs-reader.html
* igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1:
- shard-tglb: [PASS][31] -> [FAIL][32] ([i915#2521])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-tglb7/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-tglb2/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1.html
* igt@kms_async_flips@alternate-sync-async-flip@pipe-c-edp-1:
- shard-skl: [PASS][33] -> [FAIL][34] ([i915#2521])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-skl1/igt@kms_async_flips@alternate-sync-async-flip@pipe-c-edp-1.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-skl7/igt@kms_async_flips@alternate-sync-async-flip@pipe-c-edp-1.html
* igt@kms_big_fb@x-tiled-16bpp-rotate-270:
- shard-glk: NOTRUN -> [SKIP][35] ([fdo#109271]) +38 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-glk5/igt@kms_big_fb@x-tiled-16bpp-rotate-270.html
* igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][36] ([fdo#109271] / [i915#3886]) +2 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-apl6/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
- shard-kbl: NOTRUN -> [SKIP][37] ([fdo#109271] / [i915#3886])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-kbl4/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_chamelium@dp-hpd-after-suspend:
- shard-apl: NOTRUN -> [SKIP][38] ([fdo#109271] / [fdo#111827]) +3 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-apl6/igt@kms_chamelium@dp-hpd-after-suspend.html
* igt@kms_chamelium@hdmi-mode-timings:
- shard-kbl: NOTRUN -> [SKIP][39] ([fdo#109271] / [fdo#111827])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-kbl4/igt@kms_chamelium@hdmi-mode-timings.html
* igt@kms_content_protection@srm:
- shard-apl: NOTRUN -> [TIMEOUT][40] ([i915#1319])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-apl8/igt@kms_content_protection@srm.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-apl: [PASS][41] -> [INCOMPLETE][42] ([i915#180] / [i915#1982] / [i915#4939])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-apl8/igt@kms_fbcon_fbt@fbc-suspend.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-apl6/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-valid-mode:
- shard-iclb: NOTRUN -> [SKIP][43] ([i915#2672]) +6 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-iclb6/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][44] ([i915#3555])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][45] ([i915#2672] / [i915#3555]) +1 similar issue
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-iclb3/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling@pipe-a-default-mode.html
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-edp-1:
- shard-skl: [PASS][46] -> [INCOMPLETE][47] ([i915#4939])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-skl1/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-edp-1.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-skl1/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-edp-1.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-basic:
- shard-apl: NOTRUN -> [FAIL][48] ([fdo#108145] / [i915#265])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-apl6/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: [PASS][49] -> [FAIL][50] ([fdo#108145] / [i915#265])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-skl1/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
- shard-glk: NOTRUN -> [FAIL][51] ([i915#265])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-glk5/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
* igt@kms_psr@psr2_cursor_mmap_gtt:
- shard-iclb: [PASS][52] -> [SKIP][53] ([fdo#109441]) +1 similar issue
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_gtt.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-iclb4/igt@kms_psr@psr2_cursor_mmap_gtt.html
* igt@kms_vblank@pipe-d-wait-idle:
- shard-glk: NOTRUN -> [SKIP][54] ([fdo#109271] / [i915#533])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-glk5/igt@kms_vblank@pipe-d-wait-idle.html
* igt@sysfs_clients@fair-1:
- shard-glk: NOTRUN -> [SKIP][55] ([fdo#109271] / [i915#2994])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-glk5/igt@sysfs_clients@fair-1.html
#### Possible fixes ####
* igt@drm_read@short-buffer-nonblock:
- {shard-rkl}: [SKIP][56] ([i915#4098]) -> [PASS][57]
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-rkl-1/igt@drm_read@short-buffer-nonblock.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-rkl-6/igt@drm_read@short-buffer-nonblock.html
* igt@fbdev@unaligned-read:
- {shard-rkl}: [SKIP][58] ([i915#2582]) -> [PASS][59]
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-rkl-1/igt@fbdev@unaligned-read.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-rkl-6/igt@fbdev@unaligned-read.html
* igt@gem_ctx_exec@basic-nohangcheck:
- {shard-tglu}: [FAIL][60] ([i915#6268]) -> [PASS][61]
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-tglu-4/igt@gem_ctx_exec@basic-nohangcheck.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-tglu-2/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_exec_balancer@fairslice:
- {shard-rkl}: [SKIP][62] ([i915#6259]) -> [PASS][63]
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-rkl-5/igt@gem_exec_balancer@fairslice.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-rkl-1/igt@gem_exec_balancer@fairslice.html
* igt@gem_exec_balancer@parallel:
- shard-iclb: [SKIP][64] ([i915#4525]) -> [PASS][65]
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-iclb8/igt@gem_exec_balancer@parallel.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-iclb2/igt@gem_exec_balancer@parallel.html
* igt@gem_exec_endless@dispatch@bcs0:
- {shard-rkl}: [SKIP][66] ([i915#6247]) -> [PASS][67]
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-rkl-5/igt@gem_exec_endless@dispatch@bcs0.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-rkl-1/igt@gem_exec_endless@dispatch@bcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl: [FAIL][68] ([i915#2842]) -> [PASS][69] +2 similar issues
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-kbl7/igt@gem_exec_fair@basic-none@vcs0.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-kbl4/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- {shard-tglu}: [FAIL][70] ([i915#2842]) -> [PASS][71]
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-tglu-2/igt@gem_exec_fair@basic-pace-share@rcs0.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-tglu-2/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-kbl: [FAIL][72] ([i915#2851]) -> [PASS][73]
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-kbl7/igt@gem_exec_fair@basic-pace@rcs0.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-kbl4/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_fence@basic-wait@bcs0:
- {shard-rkl}: [SKIP][74] ([i915#6251]) -> [PASS][75]
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-rkl-5/igt@gem_exec_fence@basic-wait@bcs0.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-rkl-6/igt@gem_exec_fence@basic-wait@bcs0.html
* igt@gem_exec_reloc@basic-wc:
- {shard-rkl}: [SKIP][76] ([i915#3281]) -> [PASS][77] +2 similar issues
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-rkl-2/igt@gem_exec_reloc@basic-wc.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-rkl-5/igt@gem_exec_reloc@basic-wc.html
* igt@gem_ppgtt@blt-vs-render-ctxn:
- {shard-rkl}: [INCOMPLETE][78] ([i915#3692]) -> [PASS][79]
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-rkl-5/igt@gem_ppgtt@blt-vs-render-ctxn.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-rkl-2/igt@gem_ppgtt@blt-vs-render-ctxn.html
* igt@gem_pread@bench:
- {shard-rkl}: [SKIP][80] ([i915#3282]) -> [PASS][81] +1 similar issue
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-rkl-2/igt@gem_pread@bench.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-rkl-5/igt@gem_pread@bench.html
* igt@gen9_exec_parse@bb-start-far:
- {shard-rkl}: [SKIP][82] ([i915#2527]) -> [PASS][83] +2 similar issues
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-rkl-2/igt@gen9_exec_parse@bb-start-far.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-rkl-5/igt@gen9_exec_parse@bb-start-far.html
* igt@i915_hangman@engine-engine-error@bcs0:
- {shard-rkl}: [SKIP][84] ([i915#6258]) -> [PASS][85]
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-rkl-5/igt@i915_hangman@engine-engine-error@bcs0.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-rkl-2/igt@i915_hangman@engine-engine-error@bcs0.html
* igt@i915_pm_backlight@fade:
- {shard-rkl}: [SKIP][86] ([i915#3012]) -> [PASS][87]
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-rkl-2/igt@i915_pm_backlight@fade.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-rkl-6/igt@i915_pm_backlight@fade.html
* igt@i915_pm_dc@dc5-psr:
- {shard-rkl}: [SKIP][88] ([i915#658]) -> [PASS][89]
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-rkl-1/igt@i915_pm_dc@dc5-psr.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-rkl-6/igt@i915_pm_dc@dc5-psr.html
* igt@i915_pm_dc@dc9-dpms:
- {shard-rkl}: [SKIP][90] ([i915#3361]) -> [PASS][91]
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-rkl-5/igt@i915_pm_dc@dc9-dpms.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-rkl-1/igt@i915_pm_dc@dc9-dpms.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a:
- {shard-dg1}: [SKIP][92] ([i915#1937]) -> [PASS][93]
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-dg1-12/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-dg1-19/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
* igt@i915_pm_rpm@dpms-non-lpsp:
- {shard-dg1}: [SKIP][94] ([i915#1397]) -> [PASS][95] +2 similar issues
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-dg1-18/igt@i915_pm_rpm@dpms-non-lpsp.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-dg1-14/igt@i915_pm_rpm@dpms-non-lpsp.html
* igt@i915_pm_rpm@modeset-lpsp:
- {shard-rkl}: [SKIP][96] ([i915#1397]) -> [PASS][97] +1 similar issue
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-rkl-1/igt@i915_pm_rpm@modeset-lpsp.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-rkl-6/igt@i915_pm_rpm@modeset-lpsp.html
* igt@i915_pm_rpm@pm-tiling:
- {shard-rkl}: [SKIP][98] ([fdo#109308]) -> [PASS][99]
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-rkl-2/igt@i915_pm_rpm@pm-tiling.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-rkl-6/igt@i915_pm_rpm@pm-tiling.html
* igt@i915_pm_rps@waitboost:
- {shard-rkl}: [FAIL][100] ([i915#4016]) -> [PASS][101]
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-rkl-2/igt@i915_pm_rps@waitboost.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-rkl-6/igt@i915_pm_rps@waitboost.html
* igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions:
- shard-glk: [FAIL][102] ([i915#2346]) -> [PASS][103] +1 similar issue
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-glk2/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-glk9/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html
* igt@kms_draw_crc@draw-method-rgb565-pwrite-untiled:
- {shard-rkl}: [SKIP][104] ([fdo#111314] / [i915#4098] / [i915#4369]) -> [PASS][105] +11 similar issues
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-rkl-5/igt@kms_draw_crc@draw-method-rgb565-pwrite-untiled.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-rkl-6/igt@kms_draw_crc@draw-method-rgb565-pwrite-untiled.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
- shard-skl: [FAIL][106] ([i915#79]) -> [PASS][107]
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
* igt@kms_flip@flip-vs-suspend@a-dp1:
- shard-apl: [DMESG-WARN][108] ([i915#180]) -> [PASS][109] +3 similar issues
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-apl3/igt@kms_flip@flip-vs-suspend@a-dp1.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-apl4/igt@kms_flip@flip-vs-suspend@a-dp1.html
* igt@kms_flip@flip-vs-suspend@c-dp1:
- shard-kbl: [DMESG-WARN][110] ([i915#180]) -> [PASS][111] +2 similar issues
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-kbl1/igt@kms_flip@flip-vs-suspend@c-dp1.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-kbl1/igt@kms_flip@flip-vs-suspend@c-dp1.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt:
- {shard-rkl}: [SKIP][112] ([i915#1849] / [i915#4098]) -> [PASS][113] +27 similar issues
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-rkl-2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt.html
* igt@kms_plane@pixel-format@pipe-a-planes:
- {shard-rkl}: [SKIP][114] ([i915#1849] / [i915#3558]) -> [PASS][115] +1 similar issue
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-rkl-5/igt@kms_plane@pixel-format@pipe-a-planes.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-rkl-6/igt@kms_plane@pixel-format@pipe-a-planes.html
* igt@kms_plane@plane-panning-bottom-right@pipe-b-planes:
- {shard-rkl}: [SKIP][116] ([i915#3558]) -> [PASS][117] +1 similar issue
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-rkl-1/igt@kms_plane@plane-panning-bottom-right@pipe-b-planes.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-rkl-6/igt@kms_plane@plane-panning-bottom-right@pipe-b-planes.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-mid:
- {shard-rkl}: [SKIP][118] ([i915#1849] / [i915#3546] / [i915#4070] / [i915#4098]) -> [PASS][119]
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-rkl-2/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-mid.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-rkl-6/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-mid.html
* igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
- {shard-rkl}: [SKIP][120] ([i915#1849] / [i915#3558] / [i915#4070]) -> [PASS][121] +1 similar issue
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-rkl-2/igt@kms_plane_multiple@atomic-pipe-a-tiling-y.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-rkl-6/igt@kms_plane_multiple@atomic-pipe-a-tiling-y.html
* igt@kms_properties@plane-properties-atomic:
- {shard-rkl}: [SKIP][122] ([i915#1849]) -> [PASS][123] +1 similar issue
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-rkl-2/igt@kms_properties@plane-properties-atomic.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-rkl-6/igt@kms_properties@plane-properties-atomic.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-iclb: [SKIP][124] ([fdo#109642] / [fdo#111068] / [i915#658]) -> [PASS][125]
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-iclb8/igt@kms_psr2_su@frontbuffer-xrgb8888.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-iclb2/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr@psr2_sprite_mmap_gtt:
- shard-iclb: [SKIP][126] ([fdo#109441]) -> [PASS][127] +1 similar issue
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-iclb8/igt@kms_psr@psr2_sprite_mmap_gtt.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
* igt@kms_psr@sprite_plane_onoff:
- {shard-rkl}: [SKIP][128] ([i915#1072]) -> [PASS][129] +2 similar issues
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-rkl-1/igt@kms_psr@sprite_plane_onoff.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-rkl-6/igt@kms_psr@sprite_plane_onoff.html
* igt@kms_universal_plane@cursor-fb-leak-pipe-b:
- {shard-rkl}: [SKIP][130] ([i915#1845] / [i915#4070] / [i915#4098]) -> [PASS][131]
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-rkl-1/igt@kms_universal_plane@cursor-fb-leak-pipe-b.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-rkl-6/igt@kms_universal_plane@cursor-fb-leak-pipe-b.html
* igt@kms_vblank@pipe-b-query-idle:
- {shard-rkl}: [SKIP][132] ([i915#1845] / [i915#4098]) -> [PASS][133] +38 similar issues
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-rkl-5/igt@kms_vblank@pipe-b-query-idle.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-rkl-6/igt@kms_vblank@pipe-b-query-idle.html
* igt@perf@gen12-unprivileged-single-ctx-counters:
- {shard-rkl}: [SKIP][134] ([fdo#109289]) -> [PASS][135]
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-rkl-5/igt@perf@gen12-unprivileged-single-ctx-counters.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-rkl-6/igt@perf@gen12-unprivileged-single-ctx-counters.html
* igt@perf@polling:
- {shard-rkl}: [FAIL][136] ([i915#5639]) -> [PASS][137]
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-rkl-1/igt@perf@polling.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-rkl-6/igt@perf@polling.html
* igt@perf@stress-open-close:
- shard-glk: [INCOMPLETE][138] ([i915#5213]) -> [PASS][139]
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-glk3/igt@perf@stress-open-close.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-glk5/igt@perf@stress-open-close.html
* igt@prime_vgem@basic-fence-flip:
- {shard-rkl}: [SKIP][140] ([fdo#109295] / [i915#3708] / [i915#4098]) -> [PASS][141]
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-rkl-2/igt@prime_vgem@basic-fence-flip.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-rkl-6/igt@prime_vgem@basic-fence-flip.html
* igt@vgem_basic@unload:
- {shard-rkl}: [SKIP][142] -> [PASS][143]
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-rkl-5/igt@vgem_basic@unload.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-rkl-1/igt@vgem_basic@unload.html
#### Warnings ####
* igt@gem_exec_balancer@parallel-ordering:
- shard-iclb: [SKIP][144] ([i915#4525]) -> [FAIL][145] ([i915#6117])
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-iclb5/igt@gem_exec_balancer@parallel-ordering.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-iclb1/igt@gem_exec_balancer@parallel-ordering.html
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-iclb: [SKIP][146] ([i915#658]) -> [SKIP][147] ([i915#588])
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-iclb7/igt@i915_pm_dc@dc3co-vpb-simulation.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_gen12_rc_ccs_cc:
- shard-skl: [SKIP][148] ([fdo#109271] / [i915#1888] / [i915#3886]) -> [SKIP][149] ([fdo#109271] / [i915#3886])
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-skl1/igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-skl7/igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_flip@flip-vs-expired-vblank@c-edp1:
- shard-skl: [FAIL][150] ([i915#2122]) -> [FAIL][151] ([i915#79])
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-skl6/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-skl9/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-pwrite:
- shard-skl: [SKIP][152] ([fdo#109271] / [i915#1888]) -> [SKIP][153] ([fdo#109271])
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-skl1/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-pwrite.html
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-skl7/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-pwrite.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-fully-sf:
- shard-iclb: [SKIP][154] ([i915#2920]) -> [SKIP][155] ([i915#658])
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-iclb2/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-fully-sf.html
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-iclb7/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area:
- shard-iclb: [SKIP][156] ([fdo#111068] / [i915#658]) -> [SKIP][157] ([i915#2920])
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11986/shard-iclb7/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
[fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
[fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110254]: https://bugs.freedesktop.org/show_bug.cgi?id=110254
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111314]: https://bugs.freedesktop.org/show_bug.cgi?id=111314
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2232]: https://gitlab.freedesktop.org/drm/intel/issues/2232
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2849]: https://gitlab.freedesktop.org/drm/intel/issues/2849
[i915#2851]: https://gitlab.freedesktop.org/drm/intel/issues/2851
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
[i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3692]: https://gitlab.freedesktop.org/drm/intel/issues/3692
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3828]: https://gitlab.freedesktop.org/drm/intel/issues/3828
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#4016]: https://gitlab.freedesktop.org/drm/intel/issues/4016
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4369]: https://gitlab.freedesktop.org/drm/intel/issues/4369
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4818]: https://gitlab.freedesktop.org/drm/intel/issues/4818
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4853]: https://gitlab.freedesktop.org/drm/intel/issues/4853
[i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
[i915#4883]: https://gitlab.freedesktop.org/drm/intel/issues/4883
[i915#4893]: https://gitlab.freedesktop.org/drm/intel/issues/4893
[i915#4936]: https://gitlab.freedesktop.org/drm/intel/issues/4936
[i915#4939]: https://gitlab.freedesktop.org/drm/intel/issues/4939
[i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
[i915#5129]: https://gitlab.freedesktop.org/drm/intel/issues/5129
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5182]: https://gitlab.freedesktop.org/drm/intel/issues/5182
[i915#5213]: https://gitlab.freedesktop.org/drm/intel/issues/5213
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5287]: https://gitlab.freedesktop.org/drm/intel/issues/5287
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#5327]: https://gitlab.freedesktop.org/drm/intel/issues/5327
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
[i915#5639]: https://gitlab.freedesktop.org/drm/intel/issues/5639
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588
[i915#5982]: https://gitlab.freedesktop.org/drm/intel/issues/5982
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
[i915#6247]: https://gitlab.freedesktop.org/drm/intel/issues/6247
[i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
[i915#6251]: https://gitlab.freedesktop.org/drm/intel/issues/6251
[i915#6252]: https://gitlab.freedesktop.org/drm/intel/issues/6252
[i915#6258]: https://gitlab.freedesktop.org/drm/intel/issues/6258
[i915#6259]: https://gitlab.freedesktop.org/drm/intel/issues/6259
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
[i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
[i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
Build changes
-------------
* Linux: CI_DRM_11986 -> Patchwork_104278v3
CI-20190529: 20190529
CI_DRM_11986: 1cb5379e17f93685065d8ec54444f1baf9386ffe @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6623: c8edfca649da71b296d882bb0319181d94e619eb @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_104278v3: 1cb5379e17f93685065d8ec54444f1baf9386ffe @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104278v3/index.html
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