From: Patchwork <patchwork@emeril.freedesktop.org>
To: fei.yang@intel.com
Cc: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/4] drm/i915/guc: Define CTB based TLB invalidation routines
Date: Wed, 21 Sep 2022 09:03:57 -0000 [thread overview]
Message-ID: <166375103773.11599.499795621695356800@emeril.freedesktop.org> (raw)
In-Reply-To: <20220921074901.3651252-1-fei.yang@intel.com>
== Series Details ==
Series: series starting with [1/4] drm/i915/guc: Define CTB based TLB invalidation routines
URL : https://patchwork.freedesktop.org/series/108818/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
next prev parent reply other threads:[~2022-09-21 9:04 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-21 7:48 [Intel-gfx] [PATCH 1/4] drm/i915/guc: Define CTB based TLB invalidation routines fei.yang
2022-09-21 7:48 ` [Intel-gfx] [PATCH 2/4] drm/i915/xehpsdv: Define GuC Based full TLB invalidation routine fei.yang
2022-09-21 7:49 ` [Intel-gfx] [PATCH 3/4] drm/i915: Add support for GuC tlb invalidation fei.yang
2022-09-21 7:49 ` [Intel-gfx] [PATCH 4/4] drm/i915/guc: enable GuC GGTT invalidation from the start fei.yang
2022-09-21 9:03 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm/i915/guc: Define CTB based TLB invalidation routines Patchwork
2022-09-21 9:03 ` Patchwork [this message]
2022-09-21 9:33 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
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