[Intel-gfx] [RFC 0/5] Panel replay phase1 implementation

[Intel-gfx] [RFC 0/5] Panel replay phase1 implementation

[Animesh Manna]

Panel Replay is a power saving feature for DP 2.0 monitor and similar
to PSR on EDP.

These patches are basic enablement patches and reused psr
framework to add panel replay related new changes which
may need further fine tuning to fill the gap if there is any.

Note: The patches are not tested due to unavailability of monitor

Animesh Manna (5):
  drm/i915/panelreplay: update plane selective fetch register definition
  drm/i915/panelreplay: Feature flag added for panel replay
  drm/i915/panelreplay: Initializaton and compute config for panel
    replay
  drm/i915/panelreplay: enable/disable panel replay
  drm/i915/panelreplay: Added state checker for panel replay state

 drivers/gpu/drm/i915/display/intel_display.c  |  1 +
 .../drm/i915/display/intel_display_types.h    |  4 +
 drivers/gpu/drm/i915/display/intel_dp.c       | 47 +++++++++--
 drivers/gpu/drm/i915/display/intel_psr.c      | 82 +++++++++++++++++--
 drivers/gpu/drm/i915/display/intel_psr.h      |  3 +
 drivers/gpu/drm/i915/i915_drv.h               |  1 +
 drivers/gpu/drm/i915/i915_pci.c               |  1 +
 drivers/gpu/drm/i915/i915_reg.h               | 33 ++++----
 drivers/gpu/drm/i915/intel_device_info.h      |  1 +
 include/drm/drm_dp_helper.h                   |  6 ++
 10 files changed, 147 insertions(+), 32 deletions(-)

-- 
2.29.0

[Intel-gfx] [RFC 1/5] drm/i915/panelreplay: update plane selective fetch register definition

[Animesh Manna]

Panel replay can be enabled for all pipes driving DP 2.0 monitor,
so updated the plane selective fetch register difinition accordingly.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c |  8 +++---
 drivers/gpu/drm/i915/i915_reg.h          | 32 +++++++++++++-----------
 2 files changed, 22 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 3f6fb7d67f84..5fa76b148f6d 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1445,7 +1445,7 @@ void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
 
 	val = plane_state ? plane_state->ctl : 0;
 	val &= plane->id == PLANE_CURSOR ? val : PLANE_SEL_FETCH_CTL_ENABLE;
-	intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), val);
+	intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(dev_priv, pipe, plane->id), val);
 	if (!val || plane->id == PLANE_CURSOR)
 		return;
 
@@ -1453,19 +1453,19 @@ void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
 
 	val = (clip->y1 + plane_state->uapi.dst.y1) << 16;
 	val |= plane_state->uapi.dst.x1;
-	intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane->id), val);
+	intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(dev_priv, pipe, plane->id), val);
 
 	/* TODO: consider auxiliary surfaces */
 	x = plane_state->uapi.src.x1 >> 16;
 	y = (plane_state->uapi.src.y1 >> 16) + clip->y1;
 	val = y << 16 | x;
-	intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane->id),
+	intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(dev_priv, pipe, plane->id),
 			  val);
 
 	/* Sizes are 0 based */
 	val = (drm_rect_height(clip) - 1) << 16;
 	val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1;
-	intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane->id), val);
+	intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(dev_priv, pipe, plane->id), val);
 }
 
 void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c2853cc005ee..5bc8f22fa9a8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7471,6 +7471,7 @@ enum {
 #define _SEL_FETCH_PLANE_BASE_7_A		0x70960
 #define _SEL_FETCH_PLANE_BASE_CUR_A		0x70880
 #define _SEL_FETCH_PLANE_BASE_1_B		0x70990
+#define _DG2_SEL_FETCH_PLANE_BASE_1_B		0x71890
 
 #define _SEL_FETCH_PLANE_BASE_A(plane) _PICK(plane, \
 					     _SEL_FETCH_PLANE_BASE_1_A, \
@@ -7481,31 +7482,34 @@ enum {
 					     _SEL_FETCH_PLANE_BASE_6_A, \
 					     _SEL_FETCH_PLANE_BASE_7_A, \
 					     _SEL_FETCH_PLANE_BASE_CUR_A)
-#define _SEL_FETCH_PLANE_BASE_1(pipe) _PIPE(pipe, _SEL_FETCH_PLANE_BASE_1_A, _SEL_FETCH_PLANE_BASE_1_B)
-#define _SEL_FETCH_PLANE_BASE(pipe, plane) (_SEL_FETCH_PLANE_BASE_1(pipe) - \
-					    _SEL_FETCH_PLANE_BASE_1_A + \
-					    _SEL_FETCH_PLANE_BASE_A(plane))
+#define _SEL_FETCH_PLANE_BASE_1(dev_priv, pipe) _PIPE(pipe, _SEL_FETCH_PLANE_BASE_1_A, \
+						      DISPLAY_VER(dev_priv) > 12 ? \
+						      _DG2_SEL_FETCH_PLANE_BASE_1_B : \
+						      _SEL_FETCH_PLANE_BASE_1_B)
+#define _SEL_FETCH_PLANE_BASE(dev_priv, pipe, plane) (_SEL_FETCH_PLANE_BASE_1(dev_priv, pipe) - \
+						      _SEL_FETCH_PLANE_BASE_1_A + \
+						      _SEL_FETCH_PLANE_BASE_A(plane))
 
 #define _SEL_FETCH_PLANE_CTL_1_A		0x70890
-#define PLANE_SEL_FETCH_CTL(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
+#define PLANE_SEL_FETCH_CTL(dev_priv, pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(dev_priv, pipe, plane) + \
 					       _SEL_FETCH_PLANE_CTL_1_A - \
 					       _SEL_FETCH_PLANE_BASE_1_A)
 #define PLANE_SEL_FETCH_CTL_ENABLE		REG_BIT(31)
 
 #define _SEL_FETCH_PLANE_POS_1_A		0x70894
-#define PLANE_SEL_FETCH_POS(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
-					       _SEL_FETCH_PLANE_POS_1_A - \
-					       _SEL_FETCH_PLANE_BASE_1_A)
+#define PLANE_SEL_FETCH_POS(dev_priv, pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(dev_priv, pipe, plane) + \
+							 _SEL_FETCH_PLANE_POS_1_A - \
+							 _SEL_FETCH_PLANE_BASE_1_A)
 
 #define _SEL_FETCH_PLANE_SIZE_1_A		0x70898
-#define PLANE_SEL_FETCH_SIZE(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
-						_SEL_FETCH_PLANE_SIZE_1_A - \
-						_SEL_FETCH_PLANE_BASE_1_A)
+#define PLANE_SEL_FETCH_SIZE(dev_priv, pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(dev_priv, pipe, plane) + \
+							  _SEL_FETCH_PLANE_SIZE_1_A - \
+							  _SEL_FETCH_PLANE_BASE_1_A)
 
 #define _SEL_FETCH_PLANE_OFFSET_1_A		0x7089C
-#define PLANE_SEL_FETCH_OFFSET(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
-						  _SEL_FETCH_PLANE_OFFSET_1_A - \
-						  _SEL_FETCH_PLANE_BASE_1_A)
+#define PLANE_SEL_FETCH_OFFSET(dev_priv, pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(dev_priv, pipe, plane) + \
+							    _SEL_FETCH_PLANE_OFFSET_1_A - \
+							    _SEL_FETCH_PLANE_BASE_1_A)
 
 /* SKL new cursor registers */
 #define _CUR_BUF_CFG_A				0x7017c
-- 
2.29.0

Re: [Intel-gfx] [RFC 1/5] drm/i915/panelreplay: update plane selective fetch register definition

[Souza, Jose]

On Wed, 2021-09-08 at 14:45 +0530, Animesh Manna wrote:
> Panel replay can be enabled for all pipes driving DP 2.0 monitor,
> so updated the plane selective fetch register difinition accordingly.

It should mention that this changes are to accommodate differences in DG2.

Anyways, DG2 had PSR2 support dropped so we don't need this whole patch.

> 
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c |  8 +++---
>  drivers/gpu/drm/i915/i915_reg.h          | 32 +++++++++++++-----------
>  2 files changed, 22 insertions(+), 18 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 3f6fb7d67f84..5fa76b148f6d 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1445,7 +1445,7 @@ void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
>  
>  	val = plane_state ? plane_state->ctl : 0;
>  	val &= plane->id == PLANE_CURSOR ? val : PLANE_SEL_FETCH_CTL_ENABLE;
> -	intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), val);
> +	intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(dev_priv, pipe, plane->id), val);
>  	if (!val || plane->id == PLANE_CURSOR)
>  		return;
>  
> @@ -1453,19 +1453,19 @@ void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
>  
>  	val = (clip->y1 + plane_state->uapi.dst.y1) << 16;
>  	val |= plane_state->uapi.dst.x1;
> -	intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane->id), val);
> +	intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(dev_priv, pipe, plane->id), val);
>  
>  	/* TODO: consider auxiliary surfaces */
>  	x = plane_state->uapi.src.x1 >> 16;
>  	y = (plane_state->uapi.src.y1 >> 16) + clip->y1;
>  	val = y << 16 | x;
> -	intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane->id),
> +	intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(dev_priv, pipe, plane->id),
>  			  val);
>  
>  	/* Sizes are 0 based */
>  	val = (drm_rect_height(clip) - 1) << 16;
>  	val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1;
> -	intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane->id), val);
> +	intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(dev_priv, pipe, plane->id), val);
>  }
>  
>  void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c2853cc005ee..5bc8f22fa9a8 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7471,6 +7471,7 @@ enum {
>  #define _SEL_FETCH_PLANE_BASE_7_A		0x70960
>  #define _SEL_FETCH_PLANE_BASE_CUR_A		0x70880
>  #define _SEL_FETCH_PLANE_BASE_1_B		0x70990
> +#define _DG2_SEL_FETCH_PLANE_BASE_1_B		0x71890
>  
>  #define _SEL_FETCH_PLANE_BASE_A(plane) _PICK(plane, \
>  					     _SEL_FETCH_PLANE_BASE_1_A, \
> @@ -7481,31 +7482,34 @@ enum {
>  					     _SEL_FETCH_PLANE_BASE_6_A, \
>  					     _SEL_FETCH_PLANE_BASE_7_A, \
>  					     _SEL_FETCH_PLANE_BASE_CUR_A)
> -#define _SEL_FETCH_PLANE_BASE_1(pipe) _PIPE(pipe, _SEL_FETCH_PLANE_BASE_1_A, _SEL_FETCH_PLANE_BASE_1_B)
> -#define _SEL_FETCH_PLANE_BASE(pipe, plane) (_SEL_FETCH_PLANE_BASE_1(pipe) - \
> -					    _SEL_FETCH_PLANE_BASE_1_A + \
> -					    _SEL_FETCH_PLANE_BASE_A(plane))
> +#define _SEL_FETCH_PLANE_BASE_1(dev_priv, pipe) _PIPE(pipe, _SEL_FETCH_PLANE_BASE_1_A, \
> +						      DISPLAY_VER(dev_priv) > 12 ? \
> +						      _DG2_SEL_FETCH_PLANE_BASE_1_B : \
> +						      _SEL_FETCH_PLANE_BASE_1_B)
> +#define _SEL_FETCH_PLANE_BASE(dev_priv, pipe, plane) (_SEL_FETCH_PLANE_BASE_1(dev_priv, pipe) - \
> +						      _SEL_FETCH_PLANE_BASE_1_A + \
> +						      _SEL_FETCH_PLANE_BASE_A(plane))
>  
>  #define _SEL_FETCH_PLANE_CTL_1_A		0x70890
> -#define PLANE_SEL_FETCH_CTL(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
> +#define PLANE_SEL_FETCH_CTL(dev_priv, pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(dev_priv, pipe, plane) + \
>  					       _SEL_FETCH_PLANE_CTL_1_A - \
>  					       _SEL_FETCH_PLANE_BASE_1_A)
>  #define PLANE_SEL_FETCH_CTL_ENABLE		REG_BIT(31)
>  
>  #define _SEL_FETCH_PLANE_POS_1_A		0x70894
> -#define PLANE_SEL_FETCH_POS(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
> -					       _SEL_FETCH_PLANE_POS_1_A - \
> -					       _SEL_FETCH_PLANE_BASE_1_A)
> +#define PLANE_SEL_FETCH_POS(dev_priv, pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(dev_priv, pipe, plane) + \
> +							 _SEL_FETCH_PLANE_POS_1_A - \
> +							 _SEL_FETCH_PLANE_BASE_1_A)
>  
>  #define _SEL_FETCH_PLANE_SIZE_1_A		0x70898
> -#define PLANE_SEL_FETCH_SIZE(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
> -						_SEL_FETCH_PLANE_SIZE_1_A - \
> -						_SEL_FETCH_PLANE_BASE_1_A)
> +#define PLANE_SEL_FETCH_SIZE(dev_priv, pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(dev_priv, pipe, plane) + \
> +							  _SEL_FETCH_PLANE_SIZE_1_A - \
> +							  _SEL_FETCH_PLANE_BASE_1_A)
>  
>  #define _SEL_FETCH_PLANE_OFFSET_1_A		0x7089C
> -#define PLANE_SEL_FETCH_OFFSET(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
> -						  _SEL_FETCH_PLANE_OFFSET_1_A - \
> -						  _SEL_FETCH_PLANE_BASE_1_A)
> +#define PLANE_SEL_FETCH_OFFSET(dev_priv, pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(dev_priv, pipe, plane) + \
> +							    _SEL_FETCH_PLANE_OFFSET_1_A - \
> +							    _SEL_FETCH_PLANE_BASE_1_A)
>  
>  /* SKL new cursor registers */
>  #define _CUR_BUF_CFG_A				0x7017c

Re: [Intel-gfx] [RFC 1/5] drm/i915/panelreplay: update plane selective fetch register definition

[Manna, Animesh]

> -----Original Message-----
> From: Souza, Jose <jose.souza@intel.com>
> Sent: Thursday, September 9, 2021 12:57 AM
> To: Manna, Animesh <animesh.manna@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Mun, Gwan-gyeong <gwan-gyeong.mun@intel.com>; Nikula, Jani
> <jani.nikula@intel.com>; Kahola, Mika <mika.kahola@intel.com>; Navare,
> Manasi D <manasi.d.navare@intel.com>
> Subject: Re: [Intel-gfx] [RFC 1/5] drm/i915/panelreplay: update plane selective
> fetch register definition
> 
> On Wed, 2021-09-08 at 14:45 +0530, Animesh Manna wrote:
> > Panel replay can be enabled for all pipes driving DP 2.0 monitor, so
> > updated the plane selective fetch register difinition accordingly.
> 
> It should mention that this changes are to accommodate differences in DG2.
> 
> Anyways, DG2 had PSR2 support dropped so we don't need this whole patch.

Panel replay can also use selective fetch/update .. rt? 
DG2 will support panel replay if not PSR2.

Regards,
Animesh
> 
> >
> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_psr.c |  8 +++---
> >  drivers/gpu/drm/i915/i915_reg.h          | 32 +++++++++++++-----------
> >  2 files changed, 22 insertions(+), 18 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 3f6fb7d67f84..5fa76b148f6d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -1445,7 +1445,7 @@ void intel_psr2_program_plane_sel_fetch(struct
> > intel_plane *plane,
> >
> >  	val = plane_state ? plane_state->ctl : 0;
> >  	val &= plane->id == PLANE_CURSOR ? val :
> PLANE_SEL_FETCH_CTL_ENABLE;
> > -	intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id),
> val);
> > +	intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(dev_priv, pipe,
> > +plane->id), val);
> >  	if (!val || plane->id == PLANE_CURSOR)
> >  		return;
> >
> > @@ -1453,19 +1453,19 @@ void intel_psr2_program_plane_sel_fetch(struct
> > intel_plane *plane,
> >
> >  	val = (clip->y1 + plane_state->uapi.dst.y1) << 16;
> >  	val |= plane_state->uapi.dst.x1;
> > -	intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane->id),
> val);
> > +	intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(dev_priv, pipe,
> > +plane->id), val);
> >
> >  	/* TODO: consider auxiliary surfaces */
> >  	x = plane_state->uapi.src.x1 >> 16;
> >  	y = (plane_state->uapi.src.y1 >> 16) + clip->y1;
> >  	val = y << 16 | x;
> > -	intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane-
> >id),
> > +	intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(dev_priv, pipe,
> > +plane->id),
> >  			  val);
> >
> >  	/* Sizes are 0 based */
> >  	val = (drm_rect_height(clip) - 1) << 16;
> >  	val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1;
> > -	intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane->id),
> val);
> > +	intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(dev_priv, pipe,
> > +plane->id), val);
> >  }
> >
> >  void intel_psr2_program_trans_man_trk_ctl(const struct
> > intel_crtc_state *crtc_state) diff --git
> > a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index c2853cc005ee..5bc8f22fa9a8 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7471,6 +7471,7 @@ enum {
> >  #define _SEL_FETCH_PLANE_BASE_7_A		0x70960
> >  #define _SEL_FETCH_PLANE_BASE_CUR_A		0x70880
> >  #define _SEL_FETCH_PLANE_BASE_1_B		0x70990
> > +#define _DG2_SEL_FETCH_PLANE_BASE_1_B		0x71890
> >
> >  #define _SEL_FETCH_PLANE_BASE_A(plane) _PICK(plane, \
> >  					     _SEL_FETCH_PLANE_BASE_1_A, \
> @@ -7481,31 +7482,34 @@ enum {
> >  					     _SEL_FETCH_PLANE_BASE_6_A, \
> >  					     _SEL_FETCH_PLANE_BASE_7_A, \
> >  					     _SEL_FETCH_PLANE_BASE_CUR_A) -
> #define
> > _SEL_FETCH_PLANE_BASE_1(pipe) _PIPE(pipe,
> _SEL_FETCH_PLANE_BASE_1_A,
> > _SEL_FETCH_PLANE_BASE_1_B) -#define _SEL_FETCH_PLANE_BASE(pipe,
> plane) (_SEL_FETCH_PLANE_BASE_1(pipe) - \
> > -					    _SEL_FETCH_PLANE_BASE_1_A + \
> > -					    _SEL_FETCH_PLANE_BASE_A(plane))
> > +#define _SEL_FETCH_PLANE_BASE_1(dev_priv, pipe) _PIPE(pipe,
> _SEL_FETCH_PLANE_BASE_1_A, \
> > +						      DISPLAY_VER(dev_priv) >
> 12 ? \
> > +
> _DG2_SEL_FETCH_PLANE_BASE_1_B : \
> > +
> _SEL_FETCH_PLANE_BASE_1_B) #define
> > +_SEL_FETCH_PLANE_BASE(dev_priv, pipe, plane)
> (_SEL_FETCH_PLANE_BASE_1(dev_priv, pipe) - \
> > +
> _SEL_FETCH_PLANE_BASE_1_A + \
> > +
> _SEL_FETCH_PLANE_BASE_A(plane))
> >
> >  #define _SEL_FETCH_PLANE_CTL_1_A		0x70890
> > -#define PLANE_SEL_FETCH_CTL(pipe, plane)
> > _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
> > +#define PLANE_SEL_FETCH_CTL(dev_priv, pipe, plane)
> > +_MMIO(_SEL_FETCH_PLANE_BASE(dev_priv, pipe, plane) + \
> >  					       _SEL_FETCH_PLANE_CTL_1_A - \
> >  					       _SEL_FETCH_PLANE_BASE_1_A)
> >  #define PLANE_SEL_FETCH_CTL_ENABLE		REG_BIT(31)
> >
> >  #define _SEL_FETCH_PLANE_POS_1_A		0x70894
> > -#define PLANE_SEL_FETCH_POS(pipe, plane)
> _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
> > -					       _SEL_FETCH_PLANE_POS_1_A - \
> > -					       _SEL_FETCH_PLANE_BASE_1_A)
> > +#define PLANE_SEL_FETCH_POS(dev_priv, pipe, plane)
> _MMIO(_SEL_FETCH_PLANE_BASE(dev_priv, pipe, plane) + \
> > +
> _SEL_FETCH_PLANE_POS_1_A - \
> > +
> _SEL_FETCH_PLANE_BASE_1_A)
> >
> >  #define _SEL_FETCH_PLANE_SIZE_1_A		0x70898
> > -#define PLANE_SEL_FETCH_SIZE(pipe, plane)
> _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
> > -						_SEL_FETCH_PLANE_SIZE_1_A
> - \
> > -
> 	_SEL_FETCH_PLANE_BASE_1_A)
> > +#define PLANE_SEL_FETCH_SIZE(dev_priv, pipe, plane)
> _MMIO(_SEL_FETCH_PLANE_BASE(dev_priv, pipe, plane) + \
> > +
> _SEL_FETCH_PLANE_SIZE_1_A - \
> > +
> _SEL_FETCH_PLANE_BASE_1_A)
> >
> >  #define _SEL_FETCH_PLANE_OFFSET_1_A		0x7089C
> > -#define PLANE_SEL_FETCH_OFFSET(pipe, plane)
> _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
> > -
> _SEL_FETCH_PLANE_OFFSET_1_A - \
> > -
> _SEL_FETCH_PLANE_BASE_1_A)
> > +#define PLANE_SEL_FETCH_OFFSET(dev_priv, pipe, plane)
> _MMIO(_SEL_FETCH_PLANE_BASE(dev_priv, pipe, plane) + \
> > +
> _SEL_FETCH_PLANE_OFFSET_1_A - \
> > +
> _SEL_FETCH_PLANE_BASE_1_A)
> >
> >  /* SKL new cursor registers */
> >  #define _CUR_BUF_CFG_A				0x7017c

[Intel-gfx] [RFC 2/5] drm/i915/panelreplay: Feature flag added for panel replay

[Animesh Manna]

Platforms having Display 13 and above will support panel
replay feature of DP 2.0 monitor. Added a feature flag
for panel replay.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h          | 1 +
 drivers/gpu/drm/i915/i915_pci.c          | 1 +
 drivers/gpu/drm/i915/intel_device_info.h | 1 +
 3 files changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1fd3040b6771..5b26d7c09b2d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1645,6 +1645,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define HAS_DDI(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_ddi)
 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
 #define HAS_PSR(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_psr)
+#define HAS_PR(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_pr)
 #define HAS_PSR_HW_TRACKING(dev_priv) \
 	(INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
 #define HAS_PSR2_SEL_FETCH(dev_priv)	 (GRAPHICS_VER(dev_priv) >= 12)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index d4a6a9dcf182..c58bd19b5bdf 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -946,6 +946,7 @@ static const struct intel_device_info adl_s_info = {
 	.display.has_hotplug = 1,						\
 	.display.has_ipc = 1,							\
 	.display.has_psr = 1,							\
+	.display.has_pr = 1,						\
 	.display.ver = 13,							\
 	.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),	\
 	.pipe_offsets = {							\
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index d328bb95c49b..4552a1f88568 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -161,6 +161,7 @@ enum intel_ppgtt_type {
 	func(has_modular_fia); \
 	func(has_overlay); \
 	func(has_psr); \
+	func(has_pr); \
 	func(has_psr_hw_tracking); \
 	func(overlay_needs_physical); \
 	func(supports_tv);
-- 
2.29.0

Re: [Intel-gfx] [RFC 2/5] drm/i915/panelreplay: Feature flag added for panel replay

[Souza, Jose]

On Wed, 2021-09-08 at 14:45 +0530, Animesh Manna wrote:
> Platforms having Display 13 and above will support panel
> replay feature of DP 2.0 monitor. Added a feature flag
> for panel replay.

As all display 13 and newer platforms supports it would be better to have #define HAS_PR(i915) (DISPLAY_VER(i915) >= 13) instead of add one more
parameter to intel_device_info.

> 
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h          | 1 +
>  drivers/gpu/drm/i915/i915_pci.c          | 1 +
>  drivers/gpu/drm/i915/intel_device_info.h | 1 +
>  3 files changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 1fd3040b6771..5b26d7c09b2d 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1645,6 +1645,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>  #define HAS_DDI(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_ddi)
>  #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
>  #define HAS_PSR(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_psr)
> +#define HAS_PR(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_pr)
>  #define HAS_PSR_HW_TRACKING(dev_priv) \
>  	(INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
>  #define HAS_PSR2_SEL_FETCH(dev_priv)	 (GRAPHICS_VER(dev_priv) >= 12)
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index d4a6a9dcf182..c58bd19b5bdf 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -946,6 +946,7 @@ static const struct intel_device_info adl_s_info = {
>  	.display.has_hotplug = 1,						\
>  	.display.has_ipc = 1,							\
>  	.display.has_psr = 1,							\
> +	.display.has_pr = 1,						\
>  	.display.ver = 13,							\
>  	.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),	\
>  	.pipe_offsets = {							\
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index d328bb95c49b..4552a1f88568 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -161,6 +161,7 @@ enum intel_ppgtt_type {
>  	func(has_modular_fia); \
>  	func(has_overlay); \
>  	func(has_psr); \
> +	func(has_pr); \
>  	func(has_psr_hw_tracking); \
>  	func(overlay_needs_physical); \
>  	func(supports_tv);

[Intel-gfx] [RFC 3/5] drm/i915/panelreplay: Initializaton and compute config for panel replay

[Animesh Manna]

As panel replay feature similar to PSR feature of EDP panel, so currently
utilized existing psr framework for panel replay.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 .../drm/i915/display/intel_display_types.h    |  4 ++
 drivers/gpu/drm/i915/display/intel_dp.c       | 47 +++++++++++++++----
 drivers/gpu/drm/i915/display/intel_psr.c      | 43 +++++++++++++++++
 drivers/gpu/drm/i915/display/intel_psr.h      |  3 ++
 include/drm/drm_dp_helper.h                   |  3 ++
 5 files changed, 91 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index c7bcf9183447..6ca9fabb9333 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1066,6 +1066,7 @@ struct intel_crtc_state {
 	bool req_psr2_sdp_prior_scanline;
 	u32 dc3co_exitline;
 	u16 su_y_granularity;
+	bool has_panel_replay;
 
 	/*
 	 * Frequence the dpll for the port should run at. Differs from the
@@ -1526,6 +1527,8 @@ struct intel_psr {
 	bool irq_aux_error;
 	u16 su_w_granularity;
 	u16 su_y_granularity;
+	bool sink_pr_support;
+	bool pr_enabled;
 	u32 dc3co_exitline;
 	u32 dc3co_exit_delay;
 	struct delayed_work dc3co_work;
@@ -1552,6 +1555,7 @@ struct intel_dp {
 	u8 lttpr_phy_caps[DP_MAX_LTTPR_COUNT][DP_LTTPR_PHY_CAP_SIZE];
 	u8 fec_capable;
 	u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE];
+	u8 pr_dpcd;
 	/* source rates */
 	int num_source_rates;
 	const int *source_rates;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index d28bd8c4a8a5..90c708548811 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1560,12 +1560,22 @@ static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 
-	/*
-	 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
-	 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
-	 * Colorimetry Format indication.
-	 */
-	vsc->revision = 0x5;
+	if (crtc_state->has_panel_replay) {
+		/*
+		 * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
+		 * VSC SDP supporting 3D stereo, Panel Replay, and Pixel
+		 * Encoding/Colorimetry Format indication.
+		 */
+		vsc->revision = 0x7;
+	} else {
+		/*
+		 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
+		 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
+		 * Colorimetry Format indication.
+		 */
+		vsc->revision = 0x5;
+	}
+
 	vsc->length = 0x13;
 
 	/* DP 1.4a spec, Table 2-120 */
@@ -1674,6 +1684,22 @@ void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
 			vsc->revision = 0x4;
 			vsc->length = 0xe;
 		}
+	} else if (intel_dp->psr.pr_enabled) {
+		if (intel_dp->psr.colorimetry_support &&
+		    intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
+			/* [PR, +Colorimetry] */
+			intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
+							 vsc);
+		} else {
+			/*
+			 * [PR, -Colorimetry]
+			 * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
+			 * VSC SDP supporting 3D stereo + PR (applies to eDP v1.3 or
+			 * higher).
+			 */
+			vsc->revision = 0x6;
+			vsc->length = 0x10;
+		}
 	} else {
 		/*
 		 * [PSR1]
@@ -1814,6 +1840,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 
 	intel_vrr_compute_config(pipe_config, conn_state);
 	intel_psr_compute_config(intel_dp, pipe_config);
+	intel_panel_replay_compute_config(intel_dp, pipe_config);
 	intel_drrs_compute_config(intel_dp, pipe_config, output_bpp,
 				  constant_n);
 	intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
@@ -2719,10 +2746,10 @@ static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
 	sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
 
 	/*
-	 * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as
-	 * per DP 1.4a spec.
+	 * Revision 0x5 and 0x7 supports Pixel Encoding/Colorimetry Format as
+	 * per DP 1.4a spec and DP 2.0 spec respectively.
 	 */
-	if (vsc->revision != 0x5)
+	if (vsc->revision != 0x5 || vsc->revision != 0x7)
 		goto out;
 
 	/* VSC SDP Payload for DB16 through DB18 */
@@ -5017,6 +5044,8 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
 
 	intel_psr_init(intel_dp);
 
+	intel_panel_replay_init(intel_dp);
+
 	return true;
 
 fail:
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 5fa76b148f6d..660e19c10aa8 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -947,6 +947,21 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 	return true;
 }
 
+void intel_panel_replay_compute_config(struct intel_dp *intel_dp,
+				       struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+	if (!intel_dp->psr.sink_pr_support)
+		return;
+
+	crtc_state->has_panel_replay = true;
+	crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
+
+	if (HAS_PSR2_SEL_FETCH(dev_priv))
+		intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state);
+}
+
 void intel_psr_compute_config(struct intel_dp *intel_dp,
 			      struct intel_crtc_state *crtc_state)
 {
@@ -1177,6 +1192,7 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
 	drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);
 
 	intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
+	intel_dp->psr.pr_enabled = crtc_state->has_panel_replay;
 	intel_dp->psr.busy_frontbuffer_bits = 0;
 	intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
 	intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
@@ -2089,6 +2105,33 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
 	}
 }
 
+/**
+ * intel_panel_replay_init - Check for sink and source capability.
+ * @intel_dp: Intel DP
+ *
+ * This function is called after the initializing connector.
+ * (the initializing of connector treats the handling of connector capabilities)
+ * And it initializes basic panel replay stuff for each DP Encoder.
+ */
+void intel_panel_replay_init(struct intel_dp *intel_dp)
+{
+	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+	if (!HAS_PR(dev_priv))
+		return;
+
+	drm_dp_dpcd_read(&intel_dp->aux, DP_PANEL_REPLAY_SUPPORT, &intel_dp->pr_dpcd,
+			 sizeof(intel_dp->pr_dpcd));
+
+	if (!(intel_dp->pr_dpcd & PANEL_REPLAY_SUPPORT)) {
+		drm_dbg_kms(&dev_priv->drm,
+			    "Panel replay is not supported by panel\n");
+		return;
+	}
+
+	intel_dp->psr.sink_pr_support = true;
+}
+
 /**
  * intel_psr_init - Init basic PSR work and mutex.
  * @intel_dp: Intel DP
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index 641521b101c8..c190ec46a9fc 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -36,6 +36,7 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
 		     unsigned frontbuffer_bits,
 		     enum fb_op_origin origin);
 void intel_psr_init(struct intel_dp *intel_dp);
+void intel_panel_replay_init(struct intel_dp *intel_dp);
 void intel_psr_compute_config(struct intel_dp *intel_dp,
 			      struct intel_crtc_state *crtc_state);
 void intel_psr_get_config(struct intel_encoder *encoder,
@@ -53,5 +54,7 @@ void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
 					int color_plane);
 void intel_psr_pause(struct intel_dp *intel_dp);
 void intel_psr_resume(struct intel_dp *intel_dp);
+void intel_panel_replay_compute_config(struct intel_dp *intel_dp,
+				       struct intel_crtc_state *crtc_state);
 
 #endif /* __INTEL_PSR_H__ */
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 1d5b3dbb6e56..1b4dcee3b281 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -537,6 +537,9 @@ struct drm_panel;
 #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1  0x0a1
 #define DP_DSC_BRANCH_MAX_LINE_WIDTH        0x0a2
 
+#define DP_PANEL_REPLAY_SUPPORT             0x0b0
+# define PANEL_REPLAY_SUPPORT               (1 << 0)
+
 /* Link Configuration */
 #define	DP_LINK_BW_SET		            0x100
 # define DP_LINK_RATE_TABLE		    0x00    /* eDP 1.4 */
-- 
2.29.0

Re: [Intel-gfx] [RFC 3/5] drm/i915/panelreplay: Initializaton and compute config for panel replay

[Souza, Jose]

On Wed, 2021-09-08 at 14:45 +0530, Animesh Manna wrote:
> As panel replay feature similar to PSR feature of EDP panel, so currently
> utilized existing psr framework for panel replay.
> 
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  .../drm/i915/display/intel_display_types.h    |  4 ++
>  drivers/gpu/drm/i915/display/intel_dp.c       | 47 +++++++++++++++----
>  drivers/gpu/drm/i915/display/intel_psr.c      | 43 +++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_psr.h      |  3 ++
>  include/drm/drm_dp_helper.h                   |  3 ++
>  5 files changed, 91 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index c7bcf9183447..6ca9fabb9333 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1066,6 +1066,7 @@ struct intel_crtc_state {
>  	bool req_psr2_sdp_prior_scanline;
>  	u32 dc3co_exitline;
>  	u16 su_y_granularity;
> +	bool has_panel_replay;
>  
>  	/*
>  	 * Frequence the dpll for the port should run at. Differs from the
> @@ -1526,6 +1527,8 @@ struct intel_psr {
>  	bool irq_aux_error;
>  	u16 su_w_granularity;
>  	u16 su_y_granularity;
> +	bool sink_pr_support;
> +	bool pr_enabled;

Instead of all the above we could have a function that checks if displayPort is eDP or not, to know if is PSR or PR.
sink_support and all the others should be shared for PSR and PR.

>  	u32 dc3co_exitline;
>  	u32 dc3co_exit_delay;
>  	struct delayed_work dc3co_work;
> @@ -1552,6 +1555,7 @@ struct intel_dp {
>  	u8 lttpr_phy_caps[DP_MAX_LTTPR_COUNT][DP_LTTPR_PHY_CAP_SIZE];
>  	u8 fec_capable;
>  	u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE];
> +	u8 pr_dpcd;

Used once why cache it?

>  	/* source rates */
>  	int num_source_rates;
>  	const int *source_rates;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index d28bd8c4a8a5..90c708548811 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1560,12 +1560,22 @@ static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  
> -	/*
> -	 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> -	 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> -	 * Colorimetry Format indication.
> -	 */
> -	vsc->revision = 0x5;
> +	if (crtc_state->has_panel_replay) {
> +		/*
> +		 * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
> +		 * VSC SDP supporting 3D stereo, Panel Replay, and Pixel
> +		 * Encoding/Colorimetry Format indication.
> +		 */
> +		vsc->revision = 0x7;
> +	} else {
> +		/*
> +		 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> +		 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> +		 * Colorimetry Format indication.
> +		 */
> +		vsc->revision = 0x5;
> +	}
> +
>  	vsc->length = 0x13;
>  
>  	/* DP 1.4a spec, Table 2-120 */
> @@ -1674,6 +1684,22 @@ void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
>  			vsc->revision = 0x4;
>  			vsc->length = 0xe;
>  		}
> +	} else if (intel_dp->psr.pr_enabled) {
> +		if (intel_dp->psr.colorimetry_support &&
> +		    intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
> +			/* [PR, +Colorimetry] */
> +			intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
> +							 vsc);
> +		} else {
> +			/*
> +			 * [PR, -Colorimetry]
> +			 * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
> +			 * VSC SDP supporting 3D stereo + PR (applies to eDP v1.3 or
> +			 * higher).
> +			 */
> +			vsc->revision = 0x6;
> +			vsc->length = 0x10;
> +		}
>  	} else {
>  		/*
>  		 * [PSR1]
> @@ -1814,6 +1840,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>  
>  	intel_vrr_compute_config(pipe_config, conn_state);
>  	intel_psr_compute_config(intel_dp, pipe_config);
> +	intel_panel_replay_compute_config(intel_dp, pipe_config);
>  	intel_drrs_compute_config(intel_dp, pipe_config, output_bpp,
>  				  constant_n);
>  	intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
> @@ -2719,10 +2746,10 @@ static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
>  	sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
>  
>  	/*
> -	 * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as
> -	 * per DP 1.4a spec.
> +	 * Revision 0x5 and 0x7 supports Pixel Encoding/Colorimetry Format as
> +	 * per DP 1.4a spec and DP 2.0 spec respectively.
>  	 */
> -	if (vsc->revision != 0x5)
> +	if (vsc->revision != 0x5 || vsc->revision != 0x7)
>  		goto out;
>  
>  	/* VSC SDP Payload for DB16 through DB18 */
> @@ -5017,6 +5044,8 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
>  
>  	intel_psr_init(intel_dp);
>  
> +	intel_panel_replay_init(intel_dp);
> +
>  	return true;
>  
>  fail:
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 5fa76b148f6d..660e19c10aa8 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -947,6 +947,21 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
>  	return true;
>  }
>  
> +void intel_panel_replay_compute_config(struct intel_dp *intel_dp,
> +				       struct intel_crtc_state *crtc_state)
> +{
> +	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +
> +	if (!intel_dp->psr.sink_pr_support)
> +		return;
> +
> +	crtc_state->has_panel_replay = true;
> +	crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
> +
> +	if (HAS_PSR2_SEL_FETCH(dev_priv))
> +		intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state);
> +}
> +
>  void intel_psr_compute_config(struct intel_dp *intel_dp,
>  			      struct intel_crtc_state *crtc_state)
>  {
> @@ -1177,6 +1192,7 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
>  	drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);
>  
>  	intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
> +	intel_dp->psr.pr_enabled = crtc_state->has_panel_replay;
>  	intel_dp->psr.busy_frontbuffer_bits = 0;
>  	intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
>  	intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
> @@ -2089,6 +2105,33 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
>  	}
>  }
>  
> +/**
> + * intel_panel_replay_init - Check for sink and source capability.
> + * @intel_dp: Intel DP
> + *
> + * This function is called after the initializing connector.
> + * (the initializing of connector treats the handling of connector capabilities)
> + * And it initializes basic panel replay stuff for each DP Encoder.
> + */
> +void intel_panel_replay_init(struct intel_dp *intel_dp)
> +{
> +	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +
> +	if (!HAS_PR(dev_priv))
> +		return;
> +
> +	drm_dp_dpcd_read(&intel_dp->aux, DP_PANEL_REPLAY_SUPPORT, &intel_dp->pr_dpcd,
> +			 sizeof(intel_dp->pr_dpcd));
> +
> +	if (!(intel_dp->pr_dpcd & PANEL_REPLAY_SUPPORT)) {
> +		drm_dbg_kms(&dev_priv->drm,
> +			    "Panel replay is not supported by panel\n");
> +		return;
> +	}
> +
> +	intel_dp->psr.sink_pr_support = true;
> +}
> +
>  /**
>   * intel_psr_init - Init basic PSR work and mutex.
>   * @intel_dp: Intel DP
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
> index 641521b101c8..c190ec46a9fc 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> @@ -36,6 +36,7 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
>  		     unsigned frontbuffer_bits,
>  		     enum fb_op_origin origin);
>  void intel_psr_init(struct intel_dp *intel_dp);
> +void intel_panel_replay_init(struct intel_dp *intel_dp);
>  void intel_psr_compute_config(struct intel_dp *intel_dp,
>  			      struct intel_crtc_state *crtc_state);
>  void intel_psr_get_config(struct intel_encoder *encoder,
> @@ -53,5 +54,7 @@ void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
>  					int color_plane);
>  void intel_psr_pause(struct intel_dp *intel_dp);
>  void intel_psr_resume(struct intel_dp *intel_dp);
> +void intel_panel_replay_compute_config(struct intel_dp *intel_dp,
> +				       struct intel_crtc_state *crtc_state);
>  
>  #endif /* __INTEL_PSR_H__ */
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 1d5b3dbb6e56..1b4dcee3b281 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -537,6 +537,9 @@ struct drm_panel;
>  #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1  0x0a1
>  #define DP_DSC_BRANCH_MAX_LINE_WIDTH        0x0a2
>  
> +#define DP_PANEL_REPLAY_SUPPORT             0x0b0
> +# define PANEL_REPLAY_SUPPORT               (1 << 0)
> +
>  /* Link Configuration */
>  #define	DP_LINK_BW_SET		            0x100
>  # define DP_LINK_RATE_TABLE		    0x00    /* eDP 1.4 */

Re: [Intel-gfx] [RFC 3/5] drm/i915/panelreplay: Initializaton and compute config for panel replay

[Manna, Animesh]

> -----Original Message-----
> From: Souza, Jose <jose.souza@intel.com>
> Sent: Thursday, September 9, 2021 1:02 AM
> To: Manna, Animesh <animesh.manna@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Mun, Gwan-gyeong <gwan-gyeong.mun@intel.com>; Nikula, Jani
> <jani.nikula@intel.com>; Kahola, Mika <mika.kahola@intel.com>; Navare,
> Manasi D <manasi.d.navare@intel.com>
> Subject: Re: [Intel-gfx] [RFC 3/5] drm/i915/panelreplay: Initializaton and
> compute config for panel replay
> 
> On Wed, 2021-09-08 at 14:45 +0530, Animesh Manna wrote:
> > As panel replay feature similar to PSR feature of EDP panel, so
> > currently utilized existing psr framework for panel replay.
> >
> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > ---
> >  .../drm/i915/display/intel_display_types.h    |  4 ++
> >  drivers/gpu/drm/i915/display/intel_dp.c       | 47 +++++++++++++++----
> >  drivers/gpu/drm/i915/display/intel_psr.c      | 43 +++++++++++++++++
> >  drivers/gpu/drm/i915/display/intel_psr.h      |  3 ++
> >  include/drm/drm_dp_helper.h                   |  3 ++
> >  5 files changed, 91 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index c7bcf9183447..6ca9fabb9333 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1066,6 +1066,7 @@ struct intel_crtc_state {
> >  	bool req_psr2_sdp_prior_scanline;
> >  	u32 dc3co_exitline;
> >  	u16 su_y_granularity;
> > +	bool has_panel_replay;
> >
> >  	/*
> >  	 * Frequence the dpll for the port should run at. Differs from the
> > @@ -1526,6 +1527,8 @@ struct intel_psr {
> >  	bool irq_aux_error;
> >  	u16 su_w_granularity;
> >  	u16 su_y_granularity;
> > +	bool sink_pr_support;
> > +	bool pr_enabled;
> 
> Instead of all the above we could have a function that checks if displayPort is
> eDP or not, to know if is PSR or PR.
> sink_support and all the others should be shared for PSR and PR.

To get sink capability for panel replay dpcd address 0xb0 is read by the source. I feel PSR is using different dpcd address ...rt?
DP 2.0 display only support panel replay ... maybe need to add a check for DP 2.0 also here before reading about panel replay capability or I am missing anything.

Regards,
Animesh 
> 
> >  	u32 dc3co_exitline;
> >  	u32 dc3co_exit_delay;
> >  	struct delayed_work dc3co_work;
> > @@ -1552,6 +1555,7 @@ struct intel_dp {
> >  	u8
> lttpr_phy_caps[DP_MAX_LTTPR_COUNT][DP_LTTPR_PHY_CAP_SIZE];
> >  	u8 fec_capable;
> >  	u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE];
> > +	u8 pr_dpcd;
> 
> Used once why cache it?
> 
> >  	/* source rates */
> >  	int num_source_rates;
> >  	const int *source_rates;
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index d28bd8c4a8a5..90c708548811 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -1560,12 +1560,22 @@ static void
> intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc
> >  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> >  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >
> > -	/*
> > -	 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> > -	 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> > -	 * Colorimetry Format indication.
> > -	 */
> > -	vsc->revision = 0x5;
> > +	if (crtc_state->has_panel_replay) {
> > +		/*
> > +		 * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
> > +		 * VSC SDP supporting 3D stereo, Panel Replay, and Pixel
> > +		 * Encoding/Colorimetry Format indication.
> > +		 */
> > +		vsc->revision = 0x7;
> > +	} else {
> > +		/*
> > +		 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> > +		 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> > +		 * Colorimetry Format indication.
> > +		 */
> > +		vsc->revision = 0x5;
> > +	}
> > +
> >  	vsc->length = 0x13;
> >
> >  	/* DP 1.4a spec, Table 2-120 */
> > @@ -1674,6 +1684,22 @@ void intel_dp_compute_psr_vsc_sdp(struct
> intel_dp *intel_dp,
> >  			vsc->revision = 0x4;
> >  			vsc->length = 0xe;
> >  		}
> > +	} else if (intel_dp->psr.pr_enabled) {
> > +		if (intel_dp->psr.colorimetry_support &&
> > +		    intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
> > +			/* [PR, +Colorimetry] */
> > +			intel_dp_compute_vsc_colorimetry(crtc_state,
> conn_state,
> > +							 vsc);
> > +		} else {
> > +			/*
> > +			 * [PR, -Colorimetry]
> > +			 * Prepare VSC Header for SU as per DP 2.0 spec, Table
> 2-223
> > +			 * VSC SDP supporting 3D stereo + PR (applies to eDP
> v1.3 or
> > +			 * higher).
> > +			 */
> > +			vsc->revision = 0x6;
> > +			vsc->length = 0x10;
> > +		}
> >  	} else {
> >  		/*
> >  		 * [PSR1]
> > @@ -1814,6 +1840,7 @@ intel_dp_compute_config(struct intel_encoder
> > *encoder,
> >
> >  	intel_vrr_compute_config(pipe_config, conn_state);
> >  	intel_psr_compute_config(intel_dp, pipe_config);
> > +	intel_panel_replay_compute_config(intel_dp, pipe_config);
> >  	intel_drrs_compute_config(intel_dp, pipe_config, output_bpp,
> >  				  constant_n);
> >  	intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state); @@
> > -2719,10 +2746,10 @@ static ssize_t intel_dp_vsc_sdp_pack(const struct
> drm_dp_vsc_sdp *vsc,
> >  	sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
> >
> >  	/*
> > -	 * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as
> > -	 * per DP 1.4a spec.
> > +	 * Revision 0x5 and 0x7 supports Pixel Encoding/Colorimetry Format as
> > +	 * per DP 1.4a spec and DP 2.0 spec respectively.
> >  	 */
> > -	if (vsc->revision != 0x5)
> > +	if (vsc->revision != 0x5 || vsc->revision != 0x7)
> >  		goto out;
> >
> >  	/* VSC SDP Payload for DB16 through DB18 */ @@ -5017,6 +5044,8
> @@
> > intel_dp_init_connector(struct intel_digital_port *dig_port,
> >
> >  	intel_psr_init(intel_dp);
> >
> > +	intel_panel_replay_init(intel_dp);
> > +
> >  	return true;
> >
> >  fail:
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 5fa76b148f6d..660e19c10aa8 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -947,6 +947,21 @@ static bool intel_psr2_config_valid(struct intel_dp
> *intel_dp,
> >  	return true;
> >  }
> >
> > +void intel_panel_replay_compute_config(struct intel_dp *intel_dp,
> > +				       struct intel_crtc_state *crtc_state) {
> > +	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > +
> > +	if (!intel_dp->psr.sink_pr_support)
> > +		return;
> > +
> > +	crtc_state->has_panel_replay = true;
> > +	crtc_state->infoframes.enable |=
> > +intel_hdmi_infoframe_enable(DP_SDP_VSC);
> > +
> > +	if (HAS_PSR2_SEL_FETCH(dev_priv))
> > +		intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state); }
> > +
> >  void intel_psr_compute_config(struct intel_dp *intel_dp,
> >  			      struct intel_crtc_state *crtc_state)  { @@ -1177,6
> +1192,7
> > @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
> >  	drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);
> >
> >  	intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
> > +	intel_dp->psr.pr_enabled = crtc_state->has_panel_replay;
> >  	intel_dp->psr.busy_frontbuffer_bits = 0;
> >  	intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
> >  	intel_dp->psr.transcoder = crtc_state->cpu_transcoder; @@ -2089,6
> > +2105,33 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
> >  	}
> >  }
> >
> > +/**
> > + * intel_panel_replay_init - Check for sink and source capability.
> > + * @intel_dp: Intel DP
> > + *
> > + * This function is called after the initializing connector.
> > + * (the initializing of connector treats the handling of connector
> > +capabilities)
> > + * And it initializes basic panel replay stuff for each DP Encoder.
> > + */
> > +void intel_panel_replay_init(struct intel_dp *intel_dp) {
> > +	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > +
> > +	if (!HAS_PR(dev_priv))
> > +		return;
> > +
> > +	drm_dp_dpcd_read(&intel_dp->aux, DP_PANEL_REPLAY_SUPPORT,
> &intel_dp->pr_dpcd,
> > +			 sizeof(intel_dp->pr_dpcd));
> > +
> > +	if (!(intel_dp->pr_dpcd & PANEL_REPLAY_SUPPORT)) {
> > +		drm_dbg_kms(&dev_priv->drm,
> > +			    "Panel replay is not supported by panel\n");
> > +		return;
> > +	}
> > +
> > +	intel_dp->psr.sink_pr_support = true; }
> > +
> >  /**
> >   * intel_psr_init - Init basic PSR work and mutex.
> >   * @intel_dp: Intel DP
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> > b/drivers/gpu/drm/i915/display/intel_psr.h
> > index 641521b101c8..c190ec46a9fc 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.h
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> > @@ -36,6 +36,7 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
> >  		     unsigned frontbuffer_bits,
> >  		     enum fb_op_origin origin);
> >  void intel_psr_init(struct intel_dp *intel_dp);
> > +void intel_panel_replay_init(struct intel_dp *intel_dp);
> >  void intel_psr_compute_config(struct intel_dp *intel_dp,
> >  			      struct intel_crtc_state *crtc_state);  void
> > intel_psr_get_config(struct intel_encoder *encoder, @@ -53,5 +54,7 @@
> > void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
> >  					int color_plane);
> >  void intel_psr_pause(struct intel_dp *intel_dp);  void
> > intel_psr_resume(struct intel_dp *intel_dp);
> > +void intel_panel_replay_compute_config(struct intel_dp *intel_dp,
> > +				       struct intel_crtc_state *crtc_state);
> >
> >  #endif /* __INTEL_PSR_H__ */
> > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> > index 1d5b3dbb6e56..1b4dcee3b281 100644
> > --- a/include/drm/drm_dp_helper.h
> > +++ b/include/drm/drm_dp_helper.h
> > @@ -537,6 +537,9 @@ struct drm_panel;
> >  #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1  0x0a1
> >  #define DP_DSC_BRANCH_MAX_LINE_WIDTH        0x0a2
> >
> > +#define DP_PANEL_REPLAY_SUPPORT             0x0b0
> > +# define PANEL_REPLAY_SUPPORT               (1 << 0)
> > +
> >  /* Link Configuration */
> >  #define	DP_LINK_BW_SET		            0x100
> >  # define DP_LINK_RATE_TABLE		    0x00    /* eDP 1.4 */

Re: [Intel-gfx] [RFC 3/5] drm/i915/panelreplay: Initializaton and compute config for panel replay

[Souza, Jose]

On Thu, 2021-09-09 at 01:20 +0530, Manna, Animesh wrote:
> 
> > -----Original Message-----
> > From: Souza, Jose <jose.souza@intel.com>
> > Sent: Thursday, September 9, 2021 1:02 AM
> > To: Manna, Animesh <animesh.manna@intel.com>; intel-
> > gfx@lists.freedesktop.org
> > Cc: Mun, Gwan-gyeong <gwan-gyeong.mun@intel.com>; Nikula, Jani
> > <jani.nikula@intel.com>; Kahola, Mika <mika.kahola@intel.com>; Navare,
> > Manasi D <manasi.d.navare@intel.com>
> > Subject: Re: [Intel-gfx] [RFC 3/5] drm/i915/panelreplay: Initializaton and
> > compute config for panel replay
> > 
> > On Wed, 2021-09-08 at 14:45 +0530, Animesh Manna wrote:
> > > As panel replay feature similar to PSR feature of EDP panel, so
> > > currently utilized existing psr framework for panel replay.
> > > 
> > > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > > ---
> > >  .../drm/i915/display/intel_display_types.h    |  4 ++
> > >  drivers/gpu/drm/i915/display/intel_dp.c       | 47 +++++++++++++++----
> > >  drivers/gpu/drm/i915/display/intel_psr.c      | 43 +++++++++++++++++
> > >  drivers/gpu/drm/i915/display/intel_psr.h      |  3 ++
> > >  include/drm/drm_dp_helper.h                   |  3 ++
> > >  5 files changed, 91 insertions(+), 9 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > index c7bcf9183447..6ca9fabb9333 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > @@ -1066,6 +1066,7 @@ struct intel_crtc_state {
> > >  	bool req_psr2_sdp_prior_scanline;
> > >  	u32 dc3co_exitline;
> > >  	u16 su_y_granularity;
> > > +	bool has_panel_replay;
> > > 
> > >  	/*
> > >  	 * Frequence the dpll for the port should run at. Differs from the
> > > @@ -1526,6 +1527,8 @@ struct intel_psr {
> > >  	bool irq_aux_error;
> > >  	u16 su_w_granularity;
> > >  	u16 su_y_granularity;
> > > +	bool sink_pr_support;
> > > +	bool pr_enabled;
> > 
> > Instead of all the above we could have a function that checks if displayPort is
> > eDP or not, to know if is PSR or PR.
> > sink_support and all the others should be shared for PSR and PR.
> 
> To get sink capability for panel replay dpcd address 0xb0 is read by the source. I feel PSR is using different dpcd address ...rt?
> DP 2.0 display only support panel replay ... maybe need to add a check for DP 2.0 also here before reading about panel replay capability or I am missing anything.

I mean in the function that we check if sink supports PSR we could check if is DP 2.0 and if panel replay is supported and set sink_support to true.

From there we don't need those additional bools, if is eDP we know that PSR is supported if is DisplayPort we know that is panel replay.

> 
> Regards,
> Animesh 
> > 
> > >  	u32 dc3co_exitline;
> > >  	u32 dc3co_exit_delay;
> > >  	struct delayed_work dc3co_work;
> > > @@ -1552,6 +1555,7 @@ struct intel_dp {
> > >  	u8
> > lttpr_phy_caps[DP_MAX_LTTPR_COUNT][DP_LTTPR_PHY_CAP_SIZE];
> > >  	u8 fec_capable;
> > >  	u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE];
> > > +	u8 pr_dpcd;
> > 
> > Used once why cache it?
> > 
> > >  	/* source rates */
> > >  	int num_source_rates;
> > >  	const int *source_rates;
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > > b/drivers/gpu/drm/i915/display/intel_dp.c
> > > index d28bd8c4a8a5..90c708548811 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > @@ -1560,12 +1560,22 @@ static void
> > intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc
> > >  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > >  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > > 
> > > -	/*
> > > -	 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> > > -	 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> > > -	 * Colorimetry Format indication.
> > > -	 */
> > > -	vsc->revision = 0x5;
> > > +	if (crtc_state->has_panel_replay) {
> > > +		/*
> > > +		 * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
> > > +		 * VSC SDP supporting 3D stereo, Panel Replay, and Pixel
> > > +		 * Encoding/Colorimetry Format indication.
> > > +		 */
> > > +		vsc->revision = 0x7;
> > > +	} else {
> > > +		/*
> > > +		 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> > > +		 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> > > +		 * Colorimetry Format indication.
> > > +		 */
> > > +		vsc->revision = 0x5;
> > > +	}
> > > +
> > >  	vsc->length = 0x13;
> > > 
> > >  	/* DP 1.4a spec, Table 2-120 */
> > > @@ -1674,6 +1684,22 @@ void intel_dp_compute_psr_vsc_sdp(struct
> > intel_dp *intel_dp,
> > >  			vsc->revision = 0x4;
> > >  			vsc->length = 0xe;
> > >  		}
> > > +	} else if (intel_dp->psr.pr_enabled) {
> > > +		if (intel_dp->psr.colorimetry_support &&
> > > +		    intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
> > > +			/* [PR, +Colorimetry] */
> > > +			intel_dp_compute_vsc_colorimetry(crtc_state,
> > conn_state,
> > > +							 vsc);
> > > +		} else {
> > > +			/*
> > > +			 * [PR, -Colorimetry]
> > > +			 * Prepare VSC Header for SU as per DP 2.0 spec, Table
> > 2-223
> > > +			 * VSC SDP supporting 3D stereo + PR (applies to eDP
> > v1.3 or
> > > +			 * higher).
> > > +			 */
> > > +			vsc->revision = 0x6;
> > > +			vsc->length = 0x10;
> > > +		}
> > >  	} else {
> > >  		/*
> > >  		 * [PSR1]
> > > @@ -1814,6 +1840,7 @@ intel_dp_compute_config(struct intel_encoder
> > > *encoder,
> > > 
> > >  	intel_vrr_compute_config(pipe_config, conn_state);
> > >  	intel_psr_compute_config(intel_dp, pipe_config);
> > > +	intel_panel_replay_compute_config(intel_dp, pipe_config);
> > >  	intel_drrs_compute_config(intel_dp, pipe_config, output_bpp,
> > >  				  constant_n);
> > >  	intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state); @@
> > > -2719,10 +2746,10 @@ static ssize_t intel_dp_vsc_sdp_pack(const struct
> > drm_dp_vsc_sdp *vsc,
> > >  	sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
> > > 
> > >  	/*
> > > -	 * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as
> > > -	 * per DP 1.4a spec.
> > > +	 * Revision 0x5 and 0x7 supports Pixel Encoding/Colorimetry Format as
> > > +	 * per DP 1.4a spec and DP 2.0 spec respectively.
> > >  	 */
> > > -	if (vsc->revision != 0x5)
> > > +	if (vsc->revision != 0x5 || vsc->revision != 0x7)
> > >  		goto out;
> > > 
> > >  	/* VSC SDP Payload for DB16 through DB18 */ @@ -5017,6 +5044,8
> > @@
> > > intel_dp_init_connector(struct intel_digital_port *dig_port,
> > > 
> > >  	intel_psr_init(intel_dp);
> > > 
> > > +	intel_panel_replay_init(intel_dp);
> > > +
> > >  	return true;
> > > 
> > >  fail:
> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > index 5fa76b148f6d..660e19c10aa8 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > @@ -947,6 +947,21 @@ static bool intel_psr2_config_valid(struct intel_dp
> > *intel_dp,
> > >  	return true;
> > >  }
> > > 
> > > +void intel_panel_replay_compute_config(struct intel_dp *intel_dp,
> > > +				       struct intel_crtc_state *crtc_state) {
> > > +	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > > +
> > > +	if (!intel_dp->psr.sink_pr_support)
> > > +		return;
> > > +
> > > +	crtc_state->has_panel_replay = true;
> > > +	crtc_state->infoframes.enable |=
> > > +intel_hdmi_infoframe_enable(DP_SDP_VSC);
> > > +
> > > +	if (HAS_PSR2_SEL_FETCH(dev_priv))
> > > +		intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state); }
> > > +
> > >  void intel_psr_compute_config(struct intel_dp *intel_dp,
> > >  			      struct intel_crtc_state *crtc_state)  { @@ -1177,6
> > +1192,7
> > > @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
> > >  	drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);
> > > 
> > >  	intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
> > > +	intel_dp->psr.pr_enabled = crtc_state->has_panel_replay;
> > >  	intel_dp->psr.busy_frontbuffer_bits = 0;
> > >  	intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
> > >  	intel_dp->psr.transcoder = crtc_state->cpu_transcoder; @@ -2089,6
> > > +2105,33 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
> > >  	}
> > >  }
> > > 
> > > +/**
> > > + * intel_panel_replay_init - Check for sink and source capability.
> > > + * @intel_dp: Intel DP
> > > + *
> > > + * This function is called after the initializing connector.
> > > + * (the initializing of connector treats the handling of connector
> > > +capabilities)
> > > + * And it initializes basic panel replay stuff for each DP Encoder.
> > > + */
> > > +void intel_panel_replay_init(struct intel_dp *intel_dp) {
> > > +	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > > +
> > > +	if (!HAS_PR(dev_priv))
> > > +		return;
> > > +
> > > +	drm_dp_dpcd_read(&intel_dp->aux, DP_PANEL_REPLAY_SUPPORT,
> > &intel_dp->pr_dpcd,
> > > +			 sizeof(intel_dp->pr_dpcd));
> > > +
> > > +	if (!(intel_dp->pr_dpcd & PANEL_REPLAY_SUPPORT)) {
> > > +		drm_dbg_kms(&dev_priv->drm,
> > > +			    "Panel replay is not supported by panel\n");
> > > +		return;
> > > +	}
> > > +
> > > +	intel_dp->psr.sink_pr_support = true; }
> > > +
> > >  /**
> > >   * intel_psr_init - Init basic PSR work and mutex.
> > >   * @intel_dp: Intel DP
> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> > > b/drivers/gpu/drm/i915/display/intel_psr.h
> > > index 641521b101c8..c190ec46a9fc 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_psr.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> > > @@ -36,6 +36,7 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
> > >  		     unsigned frontbuffer_bits,
> > >  		     enum fb_op_origin origin);
> > >  void intel_psr_init(struct intel_dp *intel_dp);
> > > +void intel_panel_replay_init(struct intel_dp *intel_dp);
> > >  void intel_psr_compute_config(struct intel_dp *intel_dp,
> > >  			      struct intel_crtc_state *crtc_state);  void
> > > intel_psr_get_config(struct intel_encoder *encoder, @@ -53,5 +54,7 @@
> > > void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
> > >  					int color_plane);
> > >  void intel_psr_pause(struct intel_dp *intel_dp);  void
> > > intel_psr_resume(struct intel_dp *intel_dp);
> > > +void intel_panel_replay_compute_config(struct intel_dp *intel_dp,
> > > +				       struct intel_crtc_state *crtc_state);
> > > 
> > >  #endif /* __INTEL_PSR_H__ */
> > > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> > > index 1d5b3dbb6e56..1b4dcee3b281 100644
> > > --- a/include/drm/drm_dp_helper.h
> > > +++ b/include/drm/drm_dp_helper.h
> > > @@ -537,6 +537,9 @@ struct drm_panel;
> > >  #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1  0x0a1
> > >  #define DP_DSC_BRANCH_MAX_LINE_WIDTH        0x0a2
> > > 
> > > +#define DP_PANEL_REPLAY_SUPPORT             0x0b0
> > > +# define PANEL_REPLAY_SUPPORT               (1 << 0)
> > > +
> > >  /* Link Configuration */
> > >  #define	DP_LINK_BW_SET		            0x100
> > >  # define DP_LINK_RATE_TABLE		    0x00    /* eDP 1.4 */
> 

[Intel-gfx] [RFC 4/5] drm/i915/panelreplay: enable/disable panel replay

[Animesh Manna]

TRANS_DP2_CTL register is programmed to enable panel replay from source
and sink is enabled through panel replay dpcd configuration address.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 30 ++++++++++++++++++++----
 drivers/gpu/drm/i915/i915_reg.h          |  1 +
 include/drm/drm_dp_helper.h              |  3 +++
 3 files changed, 29 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 660e19c10aa8..1dc6b340d745 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -369,8 +369,12 @@ static void intel_psr_enable_sink(struct intel_dp *intel_dp)
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	u8 dpcd_val = DP_PSR_ENABLE;
 
-	/* Enable ALPM at sink for psr2 */
-	if (intel_dp->psr.psr2_enabled) {
+	if (intel_dp->psr.pr_enabled) {
+		drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG,
+				   PANEL_REPLAY_ENABLE);
+		return;
+	} else if (intel_dp->psr.psr2_enabled) {
+		/* Enable ALPM at sink for psr2 */
 		drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG,
 				   DP_ALPM_ENABLE |
 				   DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE);
@@ -497,6 +501,17 @@ static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp)
 	return val;
 }
 
+static void dg2_activate_panel_replay(struct intel_dp *intel_dp)
+{
+	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+	intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder),
+		       ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE);
+
+	intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0,
+		     TRANS_DP2_PANEL_REPLAY_ENABLE);
+}
+
 static void hsw_activate_psr2(struct intel_dp *intel_dp)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -1077,8 +1092,10 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
 	drm_WARN_ON(&dev_priv->drm, intel_dp->psr.active);
 	lockdep_assert_held(&intel_dp->psr.lock);
 
-	/* psr1 and psr2 are mutually exclusive.*/
-	if (intel_dp->psr.psr2_enabled)
+	/* psr1, psr2 and panel-replay are mutually exclusive.*/
+	if (intel_dp->psr.pr_enabled)
+		dg2_activate_panel_replay(intel_dp);
+	else if (intel_dp->psr.psr2_enabled)
 		hsw_activate_psr2(intel_dp);
 	else
 		hsw_activate_psr1(intel_dp);
@@ -1267,7 +1284,10 @@ static void intel_psr_exit(struct intel_dp *intel_dp)
 		return;
 	}
 
-	if (intel_dp->psr.psr2_enabled) {
+	if (intel_dp->psr.pr_enabled) {
+		intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder),
+			     TRANS_DP2_PANEL_REPLAY_ENABLE, 0);
+	} else if (intel_dp->psr.psr2_enabled) {
 		tgl_disallow_dc3co_on_psr2_exit(intel_dp);
 		val = intel_de_read(dev_priv,
 				    EDP_PSR2_CTL(intel_dp->psr.transcoder));
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5bc8f22fa9a8..9effbc6e5539 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4720,6 +4720,7 @@ enum {
 #define  PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME			REG_BIT(3)
 #define  PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME		REG_BIT(2)
 #define  PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE		REG_BIT(1)
+#define  ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE		REG_BIT(31)
 #define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK	REG_GENMASK(28, 16)
 #define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val)	REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
 #define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK		REG_GENMASK(12, 0)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 1b4dcee3b281..63face4e4f6f 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -707,6 +707,9 @@ struct drm_panel;
 #define DP_BRANCH_DEVICE_CTRL		    0x1a1
 # define DP_BRANCH_DEVICE_IRQ_HPD	    (1 << 0)
 
+#define PANEL_REPLAY_CONFIG                 0x1b0
+# define PANEL_REPLAY_ENABLE                (1 << 0)
+
 #define DP_PAYLOAD_ALLOCATE_SET		    0x1c0
 #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
 #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
-- 
2.29.0

Re: [Intel-gfx] [RFC 4/5] drm/i915/panelreplay: enable/disable panel replay

[Souza, Jose]

On Wed, 2021-09-08 at 14:45 +0530, Animesh Manna wrote:
> TRANS_DP2_CTL register is programmed to enable panel replay from source
> and sink is enabled through panel replay dpcd configuration address.
> 
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 30 ++++++++++++++++++++----
>  drivers/gpu/drm/i915/i915_reg.h          |  1 +
>  include/drm/drm_dp_helper.h              |  3 +++
>  3 files changed, 29 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 660e19c10aa8..1dc6b340d745 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -369,8 +369,12 @@ static void intel_psr_enable_sink(struct intel_dp *intel_dp)
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>  	u8 dpcd_val = DP_PSR_ENABLE;
>  
> -	/* Enable ALPM at sink for psr2 */
> -	if (intel_dp->psr.psr2_enabled) {
> +	if (intel_dp->psr.pr_enabled) {
> +		drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG,
> +				   PANEL_REPLAY_ENABLE);
> +		return;

If you are sure no other dpcd write is needed better separate this if + return from the other


if (intel_dp->psr.pr_enabled) {
	...
	return;
}

if (intel_dp->psr.psr2_enabled) {
	....
} else {
	...
}

....

> +	} else if (intel_dp->psr.psr2_enabled) {
> +		/* Enable ALPM at sink for psr2 */
>  		drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG,
>  				   DP_ALPM_ENABLE |
>  				   DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE);
> @@ -497,6 +501,17 @@ static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp)
>  	return val;
>  }
>  
> +static void dg2_activate_panel_replay(struct intel_dp *intel_dp)
> +{
> +	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +
> +	intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder),
> +		       ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE);
> +
> +	intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0,
> +		     TRANS_DP2_PANEL_REPLAY_ENABLE);

PSR2 is not supported in DG2 and I would believe that is the case for panel relay.

> +}
> +
>  static void hsw_activate_psr2(struct intel_dp *intel_dp)
>  {
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> @@ -1077,8 +1092,10 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
>  	drm_WARN_ON(&dev_priv->drm, intel_dp->psr.active);
>  	lockdep_assert_held(&intel_dp->psr.lock);
>  
> -	/* psr1 and psr2 are mutually exclusive.*/
> -	if (intel_dp->psr.psr2_enabled)
> +	/* psr1, psr2 and panel-replay are mutually exclusive.*/
> +	if (intel_dp->psr.pr_enabled)
> +		dg2_activate_panel_replay(intel_dp);
> +	else if (intel_dp->psr.psr2_enabled)
>  		hsw_activate_psr2(intel_dp);
>  	else
>  		hsw_activate_psr1(intel_dp);
> @@ -1267,7 +1284,10 @@ static void intel_psr_exit(struct intel_dp *intel_dp)
>  		return;
>  	}
>  
> -	if (intel_dp->psr.psr2_enabled) {
> +	if (intel_dp->psr.pr_enabled) {
> +		intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder),
> +			     TRANS_DP2_PANEL_REPLAY_ENABLE, 0);
> +	} else if (intel_dp->psr.psr2_enabled) {
>  		tgl_disallow_dc3co_on_psr2_exit(intel_dp);
>  		val = intel_de_read(dev_priv,
>  				    EDP_PSR2_CTL(intel_dp->psr.transcoder));
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 5bc8f22fa9a8..9effbc6e5539 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4720,6 +4720,7 @@ enum {
>  #define  PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME			REG_BIT(3)
>  #define  PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME		REG_BIT(2)
>  #define  PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE		REG_BIT(1)
> +#define  ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE		REG_BIT(31)
>  #define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK	REG_GENMASK(28, 16)
>  #define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val)	REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
>  #define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK		REG_GENMASK(12, 0)
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 1b4dcee3b281..63face4e4f6f 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -707,6 +707,9 @@ struct drm_panel;
>  #define DP_BRANCH_DEVICE_CTRL		    0x1a1
>  # define DP_BRANCH_DEVICE_IRQ_HPD	    (1 << 0)
>  
> +#define PANEL_REPLAY_CONFIG                 0x1b0
> +# define PANEL_REPLAY_ENABLE                (1 << 0)
> +
>  #define DP_PAYLOAD_ALLOCATE_SET		    0x1c0
>  #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
>  #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2

[Intel-gfx] [RFC 5/5] drm/i915/panelreplay: Added state checker for panel replay state

[Animesh Manna]

has_panel_replay flag is used to check panel replay state
which is part of crtc_state structure.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 1 +
 drivers/gpu/drm/i915/display/intel_psr.c     | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 134c792e1dbd..0dcfee8b459d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -8090,6 +8090,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 		PIPE_CONF_CHECK_BOOL(has_psr);
 		PIPE_CONF_CHECK_BOOL(has_psr2);
 		PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
+		PIPE_CONF_CHECK_BOOL(has_panel_replay);
 		PIPE_CONF_CHECK_I(dc3co_exitline);
 	}
 
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 1dc6b340d745..b5eb78e9397e 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1058,6 +1058,7 @@ void intel_psr_get_config(struct intel_encoder *encoder,
 	 */
 	pipe_config->has_psr = true;
 	pipe_config->has_psr2 = intel_dp->psr.psr2_enabled;
+	pipe_config->has_panel_replay = intel_dp->psr.pr_enabled;
 	pipe_config->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
 
 	if (!intel_dp->psr.psr2_enabled)
-- 
2.29.0

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Panel replay phase1 implementation

[Patchwork]

== Series Details ==

Series: Panel replay phase1 implementation
URL   : https://patchwork.freedesktop.org/series/94470/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
c7704eae2ab0 drm/i915/panelreplay: update plane selective fetch register definition
-:8: WARNING:TYPO_SPELLING: 'difinition' may be misspelled - perhaps 'definition'?
#8: 
so updated the plane selective fetch register difinition accordingly.
                                              ^^^^^^^^^^

-:78: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#78: FILE: drivers/gpu/drm/i915/i915_reg.h:7494:
+#define PLANE_SEL_FETCH_CTL(dev_priv, pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(dev_priv, pipe, plane) + \

-:87: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#87: FILE: drivers/gpu/drm/i915/i915_reg.h:7500:
+#define PLANE_SEL_FETCH_POS(dev_priv, pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(dev_priv, pipe, plane) + \

-:95: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#95: FILE: drivers/gpu/drm/i915/i915_reg.h:7505:
+#define PLANE_SEL_FETCH_SIZE(dev_priv, pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(dev_priv, pipe, plane) + \

-:103: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#103: FILE: drivers/gpu/drm/i915/i915_reg.h:7510:
+#define PLANE_SEL_FETCH_OFFSET(dev_priv, pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(dev_priv, pipe, plane) + \

total: 0 errors, 5 warnings, 0 checks, 85 lines checked
03948896e7b6 drm/i915/panelreplay: Feature flag added for panel replay
7d7858afd7c3 drm/i915/panelreplay: Initializaton and compute config for panel replay
9432d1630bf8 drm/i915/panelreplay: enable/disable panel replay
959cdcb164d3 drm/i915/panelreplay: Added state checker for panel replay state

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Panel replay phase1 implementation

[Patchwork]

== Series Details ==

Series: Panel replay phase1 implementation
URL   : https://patchwork.freedesktop.org/series/94470/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1345:25: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1345:25:    struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1345:25:    struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1346:17: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1346:17:    struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1346:17:    struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1405:17: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1405:17:    struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1405:17:    struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:354:16: error: incompatible types in comparison expression (different type sizes):
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:354:16:    unsigned long *
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:354:16:    unsigned long long *
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:4483:31: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:4483:31:    struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:4483:31:    struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:4485:33: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:4485:33:    struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:4485:33:    struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:294:25: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:294:25:    struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:294:25:    struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:295:17: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:295:17:    struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:295:17:    struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:344:17: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:344:17:    struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:344:17:    struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c:117:1: warning: no newline at end of file
+drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h:123:51: error: marked inline, but without a definition
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2p

[Intel-gfx] ✓ Fi.CI.BAT: success for Panel replay phase1 implementation

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 3867 bytes --]

== Series Details ==

Series: Panel replay phase1 implementation
URL   : https://patchwork.freedesktop.org/series/94470/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10562 -> Patchwork_20989
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/index.html

Known issues
------------

  Here are the changes found in Patchwork_20989 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@amdgpu/amd_cs_nop@sync-fork-compute0:
    - fi-snb-2600:        NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/fi-snb-2600/igt@amdgpu/amd_cs_nop@sync-fork-compute0.html

  * igt@gem_exec_suspend@basic-s3:
    - fi-tgl-1115g4:      [PASS][2] -> [FAIL][3] ([i915#1888])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10562/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s3.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s3.html

  * igt@i915_selftest@live@execlists:
    - fi-bsw-n3050:       [PASS][4] -> [INCOMPLETE][5] ([i915#2940])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10562/fi-bsw-n3050/igt@i915_selftest@live@execlists.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/fi-bsw-n3050/igt@i915_selftest@live@execlists.html

  * igt@i915_selftest@live@gt_timelines:
    - fi-rkl-guc:         [PASS][6] -> [INCOMPLETE][7] ([i915#4034])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10562/fi-rkl-guc/igt@i915_selftest@live@gt_timelines.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/fi-rkl-guc/igt@i915_selftest@live@gt_timelines.html

  * igt@runner@aborted:
    - fi-rkl-guc:         NOTRUN -> [FAIL][8] ([i915#3928])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/fi-rkl-guc/igt@runner@aborted.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@hangcheck:
    - fi-snb-2600:        [INCOMPLETE][9] ([i915#3921]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10562/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/fi-snb-2600/igt@i915_selftest@live@hangcheck.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
  [i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
  [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
  [i915#3928]: https://gitlab.freedesktop.org/drm/intel/issues/3928
  [i915#4034]: https://gitlab.freedesktop.org/drm/intel/issues/4034


Participating hosts (47 -> 39)
------------------------------

  Missing    (8): fi-ilk-m540 bat-adls-5 bat-dg1-6 fi-bsw-cyan bat-adlp-4 fi-ctg-p8600 fi-bdw-samus bat-jsl-1 


Build changes
-------------

  * Linux: CI_DRM_10562 -> Patchwork_20989

  CI-20190529: 20190529
  CI_DRM_10562: d38c3e456e48f3cc74f454615dedc5a82e258402 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6200: 3a6585c472dff11ece952b745244f05e4c93ede5 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_20989: 959cdcb164d3097c83def2762b1c4e25f7faf66d @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

959cdcb164d3 drm/i915/panelreplay: Added state checker for panel replay state
9432d1630bf8 drm/i915/panelreplay: enable/disable panel replay
7d7858afd7c3 drm/i915/panelreplay: Initializaton and compute config for panel replay
03948896e7b6 drm/i915/panelreplay: Feature flag added for panel replay
c7704eae2ab0 drm/i915/panelreplay: update plane selective fetch register definition

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/index.html

[-- Attachment #2: Type: text/html, Size: 4629 bytes --]

[Intel-gfx] ✗ Fi.CI.IGT: failure for Panel replay phase1 implementation

[Patchwork]

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== Series Details ==

Series: Panel replay phase1 implementation
URL   : https://patchwork.freedesktop.org/series/94470/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_10562_full -> Patchwork_20989_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_20989_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_20989_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_20989_full:

### IGT changes ###

#### Possible regressions ####

  * igt@syncobj_timeline@multi-wait-for-submit-signaled:
    - shard-skl:          [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10562/shard-skl7/igt@syncobj_timeline@multi-wait-for-submit-signaled.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-skl2/igt@syncobj_timeline@multi-wait-for-submit-signaled.html

  
Known issues
------------

  Here are the changes found in Patchwork_20989_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_create@create-massive:
    - shard-snb:          NOTRUN -> [DMESG-WARN][3] ([i915#3002])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-snb2/igt@gem_create@create-massive.html
    - shard-apl:          NOTRUN -> [DMESG-WARN][4] ([i915#3002])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-apl8/igt@gem_create@create-massive.html

  * igt@gem_ctx_isolation@preservation-s3@bcs0:
    - shard-kbl:          [PASS][5] -> [DMESG-WARN][6] ([i915#180]) +5 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10562/shard-kbl1/igt@gem_ctx_isolation@preservation-s3@bcs0.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-kbl4/igt@gem_ctx_isolation@preservation-s3@bcs0.html

  * igt@gem_ctx_persistence@engines-queued:
    - shard-snb:          NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#1099]) +2 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-snb7/igt@gem_ctx_persistence@engines-queued.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
    - shard-tglb:         NOTRUN -> [FAIL][8] ([i915#2842])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-tglb5/igt@gem_exec_fair@basic-none-solo@rcs0.html

  * igt@gem_exec_fair@basic-none@rcs0:
    - shard-glk:          [PASS][9] -> [FAIL][10] ([i915#2842])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10562/shard-glk6/igt@gem_exec_fair@basic-none@rcs0.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-glk6/igt@gem_exec_fair@basic-none@rcs0.html

  * igt@gem_exec_fair@basic-none@vcs0:
    - shard-kbl:          NOTRUN -> [FAIL][11] ([i915#2842])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-kbl6/igt@gem_exec_fair@basic-none@vcs0.html

  * igt@gem_exec_fair@basic-pace@bcs0:
    - shard-tglb:         [PASS][12] -> [FAIL][13] ([i915#2842]) +1 similar issue
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10562/shard-tglb5/igt@gem_exec_fair@basic-pace@bcs0.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-tglb7/igt@gem_exec_fair@basic-pace@bcs0.html

  * igt@gem_mmap_gtt@cpuset-big-copy-xy:
    - shard-iclb:         [PASS][14] -> [FAIL][15] ([i915#2428])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10562/shard-iclb1/igt@gem_mmap_gtt@cpuset-big-copy-xy.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-iclb2/igt@gem_mmap_gtt@cpuset-big-copy-xy.html

  * igt@gem_pwrite@basic-exhaustion:
    - shard-snb:          NOTRUN -> [WARN][16] ([i915#2658])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-snb2/igt@gem_pwrite@basic-exhaustion.html
    - shard-apl:          NOTRUN -> [WARN][17] ([i915#2658])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-apl8/igt@gem_pwrite@basic-exhaustion.html

  * igt@gem_userptr_blits@coherency-sync:
    - shard-tglb:         NOTRUN -> [SKIP][18] ([fdo#110542])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-tglb5/igt@gem_userptr_blits@coherency-sync.html

  * igt@gem_userptr_blits@create-destroy-unsync:
    - shard-tglb:         NOTRUN -> [SKIP][19] ([i915#3297]) +1 similar issue
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-tglb3/igt@gem_userptr_blits@create-destroy-unsync.html

  * igt@gem_userptr_blits@vma-merge:
    - shard-kbl:          NOTRUN -> [FAIL][20] ([i915#3318])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-kbl6/igt@gem_userptr_blits@vma-merge.html

  * igt@gem_workarounds@suspend-resume:
    - shard-apl:          NOTRUN -> [DMESG-WARN][21] ([i915#180])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-apl7/igt@gem_workarounds@suspend-resume.html

  * igt@gen3_render_mixed_blits:
    - shard-tglb:         NOTRUN -> [SKIP][22] ([fdo#109289]) +2 similar issues
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-tglb5/igt@gen3_render_mixed_blits.html

  * igt@gen9_exec_parse@bb-start-cmd:
    - shard-tglb:         NOTRUN -> [SKIP][23] ([i915#2856])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-tglb5/igt@gen9_exec_parse@bb-start-cmd.html

  * igt@i915_pm_rpm@dpms-non-lpsp:
    - shard-iclb:         NOTRUN -> [SKIP][24] ([fdo#110892])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-iclb8/igt@i915_pm_rpm@dpms-non-lpsp.html

  * igt@i915_pm_rpm@gem-execbuf-stress-pc8:
    - shard-tglb:         NOTRUN -> [SKIP][25] ([fdo#109506] / [i915#2411])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-tglb5/igt@i915_pm_rpm@gem-execbuf-stress-pc8.html

  * igt@i915_query@query-topology-unsupported:
    - shard-tglb:         NOTRUN -> [SKIP][26] ([fdo#109302])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-tglb5/igt@i915_query@query-topology-unsupported.html

  * igt@i915_suspend@sysfs-reader:
    - shard-apl:          [PASS][27] -> [DMESG-WARN][28] ([i915#180]) +4 similar issues
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10562/shard-apl2/igt@i915_suspend@sysfs-reader.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-apl7/igt@i915_suspend@sysfs-reader.html

  * igt@kms_big_fb@linear-32bpp-rotate-180:
    - shard-glk:          [PASS][29] -> [DMESG-WARN][30] ([i915#118] / [i915#95]) +3 similar issues
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10562/shard-glk5/igt@kms_big_fb@linear-32bpp-rotate-180.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-glk4/igt@kms_big_fb@linear-32bpp-rotate-180.html

  * igt@kms_big_fb@x-tiled-8bpp-rotate-90:
    - shard-tglb:         NOTRUN -> [SKIP][31] ([fdo#111614]) +1 similar issue
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-tglb3/igt@kms_big_fb@x-tiled-8bpp-rotate-90.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-apl:          NOTRUN -> [SKIP][32] ([fdo#109271] / [i915#3777])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-apl2/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
    - shard-skl:          NOTRUN -> [FAIL][33] ([i915#3722]) +2 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-skl1/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-kbl:          NOTRUN -> [SKIP][34] ([fdo#109271] / [i915#3777]) +1 similar issue
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-kbl1/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_big_fb@yf-tiled-32bpp-rotate-270:
    - shard-tglb:         NOTRUN -> [SKIP][35] ([fdo#111615]) +4 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-tglb3/igt@kms_big_fb@yf-tiled-32bpp-rotate-270.html

  * igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
    - shard-apl:          NOTRUN -> [SKIP][36] ([fdo#109271] / [i915#3886]) +9 similar issues
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-apl8/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_mc_ccs:
    - shard-kbl:          NOTRUN -> [SKIP][37] ([fdo#109271] / [i915#3886]) +5 similar issues
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-kbl6/igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_rc_ccs_cc:
    - shard-skl:          NOTRUN -> [SKIP][38] ([fdo#109271] / [i915#3886]) +4 similar issues
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-skl1/igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_mc_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][39] ([i915#3689] / [i915#3886]) +1 similar issue
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-tglb5/igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_mc_ccs:
    - shard-iclb:         NOTRUN -> [SKIP][40] ([fdo#109278] / [i915#3886])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-iclb8/igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-c-missing-ccs-buffer-yf_tiled_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][41] ([i915#3689]) +9 similar issues
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-tglb5/igt@kms_ccs@pipe-c-missing-ccs-buffer-yf_tiled_ccs.html

  * igt@kms_chamelium@dp-crc-multiple:
    - shard-skl:          NOTRUN -> [SKIP][42] ([fdo#109271] / [fdo#111827]) +10 similar issues
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-skl4/igt@kms_chamelium@dp-crc-multiple.html

  * igt@kms_chamelium@vga-hpd-for-each-pipe:
    - shard-kbl:          NOTRUN -> [SKIP][43] ([fdo#109271] / [fdo#111827]) +10 similar issues
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-kbl6/igt@kms_chamelium@vga-hpd-for-each-pipe.html

  * igt@kms_color_chamelium@pipe-a-ctm-blue-to-red:
    - shard-snb:          NOTRUN -> [SKIP][44] ([fdo#109271] / [fdo#111827]) +19 similar issues
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-snb5/igt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html

  * igt@kms_color_chamelium@pipe-b-gamma:
    - shard-apl:          NOTRUN -> [SKIP][45] ([fdo#109271] / [fdo#111827]) +20 similar issues
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-apl8/igt@kms_color_chamelium@pipe-b-gamma.html

  * igt@kms_color_chamelium@pipe-c-ctm-0-25:
    - shard-tglb:         NOTRUN -> [SKIP][46] ([fdo#109284] / [fdo#111827]) +7 similar issues
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-tglb5/igt@kms_color_chamelium@pipe-c-ctm-0-25.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-tglb:         NOTRUN -> [SKIP][47] ([fdo#111828])
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-tglb5/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@dp-mst-lic-type-1:
    - shard-tglb:         NOTRUN -> [SKIP][48] ([i915#3116])
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-tglb3/igt@kms_content_protection@dp-mst-lic-type-1.html

  * igt@kms_cursor_crc@pipe-a-cursor-512x512-random:
    - shard-tglb:         NOTRUN -> [SKIP][49] ([fdo#109279] / [i915#3359]) +2 similar issues
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-tglb3/igt@kms_cursor_crc@pipe-a-cursor-512x512-random.html

  * igt@kms_cursor_crc@pipe-b-cursor-32x32-onscreen:
    - shard-skl:          NOTRUN -> [SKIP][50] ([fdo#109271]) +99 similar issues
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-skl3/igt@kms_cursor_crc@pipe-b-cursor-32x32-onscreen.html
    - shard-tglb:         NOTRUN -> [SKIP][51] ([i915#3319])
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-tglb5/igt@kms_cursor_crc@pipe-b-cursor-32x32-onscreen.html

  * igt@kms_cursor_crc@pipe-c-cursor-max-size-offscreen:
    - shard-tglb:         NOTRUN -> [SKIP][52] ([i915#3359]) +2 similar issues
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-tglb5/igt@kms_cursor_crc@pipe-c-cursor-max-size-offscreen.html

  * igt@kms_cursor_crc@pipe-d-cursor-256x256-onscreen:
    - shard-kbl:          NOTRUN -> [SKIP][53] ([fdo#109271]) +105 similar issues
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-kbl1/igt@kms_cursor_crc@pipe-d-cursor-256x256-onscreen.html

  * igt@kms_cursor_edge_walk@pipe-d-128x128-bottom-edge:
    - shard-iclb:         NOTRUN -> [SKIP][54] ([fdo#109278])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-iclb8/igt@kms_cursor_edge_walk@pipe-d-128x128-bottom-edge.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
    - shard-skl:          [PASS][55] -> [FAIL][56] ([i915#2346])
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10562/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-skl2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html

  * igt@kms_dither@fb-8bpc-vs-panel-8bpc@edp-1-pipe-a:
    - shard-tglb:         NOTRUN -> [SKIP][57] ([i915#3788])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-tglb3/igt@kms_dither@fb-8bpc-vs-panel-8bpc@edp-1-pipe-a.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-kbl:          [PASS][58] -> [INCOMPLETE][59] ([i915#155] / [i915#180] / [i915#636])
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10562/shard-kbl1/igt@kms_fbcon_fbt@fbc-suspend.html
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-kbl4/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs:
    - shard-skl:          NOTRUN -> [INCOMPLETE][60] ([i915#3699])
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-skl1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile:
    - shard-tglb:         NOTRUN -> [SKIP][61] ([i915#2587])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-tglb5/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs:
    - shard-apl:          NOTRUN -> [SKIP][62] ([fdo#109271] / [i915#2672])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-apl3/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-fullscreen:
    - shard-iclb:         NOTRUN -> [SKIP][63] ([fdo#109280])
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-fullscreen.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-onoff:
    - shard-tglb:         NOTRUN -> [SKIP][64] ([fdo#111825]) +26 similar issues
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-plflip-blt:
    - shard-snb:          NOTRUN -> [SKIP][65] ([fdo#109271]) +291 similar issues
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-snb7/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-onoff:
    - shard-skl:          [PASS][66] -> [FAIL][67] ([i915#1888])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10562/shard-skl7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-onoff.html
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-skl2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@psr-suspend:
    - shard-tglb:         [PASS][68] -> [INCOMPLETE][69] ([i915#456])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10562/shard-tglb5/igt@kms_frontbuffer_tracking@psr-suspend.html
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-tglb7/igt@kms_frontbuffer_tracking@psr-suspend.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence:
    - shard-kbl:          NOTRUN -> [SKIP][70] ([fdo#109271] / [i915#533]) +1 similar issue
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-kbl1/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence.html

  * igt@kms_plane_alpha_blend@pipe-a-alpha-basic:
    - shard-apl:          NOTRUN -> [FAIL][71] ([fdo#108145] / [i915#265]) +1 similar issue
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-apl2/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html

  * igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
    - shard-kbl:          NOTRUN -> [FAIL][72] ([fdo#108145] / [i915#265])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-kbl3/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html

  * igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb:
    - shard-skl:          NOTRUN -> [FAIL][73] ([i915#265])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html

  * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max:
    - shard-skl:          NOTRUN -> [FAIL][74] ([fdo#108145] / [i915#265])
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max.html

  * igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
    - shard-apl:          NOTRUN -> [FAIL][75] ([i915#265])
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-apl3/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [PASS][76] -> [FAIL][77] ([fdo#108145] / [i915#265]) +1 similar issue
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10562/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_plane_lowres@pipe-a-tiling-none:
    - shard-tglb:         NOTRUN -> [SKIP][78] ([i915#3536]) +1 similar issue
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-tglb3/igt@kms_plane_lowres@pipe-a-tiling-none.html

  * igt@kms_plane_multiple@atomic-pipe-b-tiling-yf:
    - shard-tglb:         NOTRUN -> [SKIP][79] ([fdo#112054])
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-tglb5/igt@kms_plane_multiple@atomic-pipe-b-tiling-yf.html

  * igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping:
    - shard-apl:          NOTRUN -> [SKIP][80] ([fdo#109271] / [i915#2733])
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-apl2/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html

  * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4:
    - shard-kbl:          NOTRUN -> [SKIP][81] ([fdo#109271] / [i915#658])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-kbl6/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4.html

  * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4:
    - shard-apl:          NOTRUN -> [SKIP][82] ([fdo#109271] / [i915#658]) +5 similar issues
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-apl7/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4.html

  * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-3:
    - shard-tglb:         NOTRUN -> [SKIP][83] ([i915#2920]) +1 similar issue
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-tglb5/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-3.html
    - shard-skl:          NOTRUN -> [SKIP][84] ([fdo#109271] / [i915#658])
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-skl3/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-3.html

  * igt@kms_psr@psr2_cursor_plane_onoff:
    - shard-tglb:         NOTRUN -> [FAIL][85] ([i915#132] / [i915#3467]) +2 similar issues
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-tglb5/igt@kms_psr@psr2_cursor_plane_onoff.html

  * igt@kms_psr@psr2_cursor_render:
    - shard-iclb:         [PASS][86] -> [SKIP][87] ([fdo#109441]) +1 similar issue
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10562/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-iclb1/igt@kms_psr@psr2_cursor_render.html

  * igt@kms_vblank@pipe-d-ts-continuation-idle:
    - shard-apl:          NOTRUN -> [SKIP][88] ([fdo#109271]) +192 similar issues
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-apl2/igt@kms_vblank@pipe-d-ts-continuation-idle.html

  * igt@kms_vblank@pipe-d-wait-idle:
    - shard-apl:          NOTRUN -> [SKIP][89] ([fdo#109271] / [i915#533]) +4 similar issues
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-apl8/igt@kms_vblank@pipe-d-wait-idle.html

  * igt@kms_writeback@writeback-check-output:
    - shard-apl:          NOTRUN -> [SKIP][90] ([fdo#109271] / [i915#2437])
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-apl2/igt@kms_writeback@writeback-check-output.html

  * igt@nouveau_crc@pipe-a-ctx-flip-detection:
    - shard-tglb:         NOTRUN -> [SKIP][91] ([i915#2530]) +3 similar issues
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-tglb3/igt@nouveau_crc@pipe-a-ctx-flip-detection.html

  * igt@prime_nv_api@i915_nv_reimport_twice_check_flink_name:
    - shard-tglb:         NOTRUN -> [SKIP][92] ([fdo#109291]) +3 similar issues
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-tglb3/igt@prime_nv_api@i915_nv_reimport_twice_check_flink_name.html

  * igt@prime_vgem@coherency-gtt:
    - shard-tglb:         NOTRUN -> [SKIP][93] ([fdo#111656])
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-tglb3/igt@prime_vgem@coherency-gtt.html

  * igt@sysfs_clients@busy:
    - shard-iclb:         NOTRUN -> [SKIP][94] ([i915#2994])
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-iclb8/igt@sysfs_clients@busy.html

  * igt@sysfs_clients@fair-0:
    - shard-apl:          NOTRUN -> [SKIP][95] ([fdo#109271] / [i915#2994]) +2 similar issues
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-apl2/igt@sysfs_clients@fair-0.html

  * igt@sysfs_clients@sema-25:
    - shard-kbl:          NOTRUN -> [SKIP][96] ([fdo#109271] / [i915#2994]) +2 similar issues
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-kbl1/igt@sysfs_clients@sema-25.html

  * igt@sysfs_clients@split-50:
    - shard-skl:          NOTRUN -> [SKIP][97] ([fdo#109271] / [i915#2994])
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-skl1/igt@sysfs_clients@split-50.html

  
#### Possible fixes ####

  * igt@feature_discovery@psr2:
    - shard-iclb:         [SKIP][98] ([i915#658]) -> [PASS][99]
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10562/shard-iclb1/igt@feature_discovery@psr2.html
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-iclb2/igt@feature_discovery@psr2.html

  * igt@gem_ctx_isolation@preservation-s3@rcs0:
    - shard-tglb:         [INCOMPLETE][100] ([i915#1373]) -> [PASS][101]
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10562/shard-tglb7/igt@gem_ctx_isolation@preservation-s3@rcs0.html
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-tglb3/igt@gem_ctx_isolation@preservation-s3@rcs0.html

  * igt@gem_exec_capture@pi@vecs0:
    - shard-skl:          [INCOMPLETE][102] ([i915#198] / [i915#2624]) -> [PASS][103]
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10562/shard-skl1/igt@gem_exec_capture@pi@vecs0.html
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-skl10/igt@gem_exec_capture@pi@vecs0.html

  * igt@gem_exec_fair@basic-deadline:
    - shard-kbl:          [FAIL][104] ([i915#2846]) -> [PASS][105]
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10562/shard-kbl4/igt@gem_exec_fair@basic-deadline.html
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-kbl7/igt@gem_exec_fair@basic-deadline.html

  * igt@gem_exec_fair@basic-none-vip@rcs0:
    - shard-glk:          [FAIL][106] ([i915#2842]) -> [PASS][107]
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10562/shard-glk3/igt@gem_exec_fair@basic-none-vip@rcs0.html
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-glk5/igt@gem_exec_fair@basic-none-vip@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs0:
    - shard-kbl:          [FAIL][108] ([i915#2842]) -> [PASS][109] +1 similar issue
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10562/shard-kbl3/igt@gem_exec_fair@basic-pace@vcs0.html
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-kbl2/igt@gem_exec_fair@basic-pace@vcs0.html

  * igt@gem_mmap_gtt@cpuset-big-copy-odd:
    - shard-iclb:         [FAIL][110] ([i915#307]) -> [PASS][111]
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10562/shard-iclb8/igt@gem_mmap_gtt@cpuset-big-copy-odd.html
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-iclb5/igt@gem_mmap_gtt@cpuset-big-copy-odd.html

  * igt@i915_pm_backlight@fade_with_suspend:
    - shard-tglb:         [INCOMPLETE][112] ([i915#456]) -> [PASS][113]
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10562/shard-tglb7/igt@i915_pm_backlight@fade_with_suspend.html
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-tglb5/igt@i915_pm_backlight@fade_with_suspend.html

  * igt@i915_pm_dc@dc6-dpms:
    - shard-iclb:         [FAIL][114] ([i915#454]) -> [PASS][115]
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10562/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-iclb4/igt@i915_pm_dc@dc6-dpms.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-tglb:         [INCOMPLETE][116] ([i915#2411] / [i915#456]) -> [PASS][117]
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10562/shard-tglb7/igt@kms_fbcon_fbt@fbc-suspend.html
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-tglb3/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_flip@flip-vs-suspend@a-dp1:
    - shard-apl:          [DMESG-WARN][118] ([i915#180]) -> [PASS][119]
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10562/shard-apl7/igt@kms_flip@flip-vs-suspend@a-dp1.html
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-apl8/igt@kms_flip@flip-vs-suspend@a-dp1.html

  * igt@kms_flip@plain-flip-ts-check@a-edp1:
    - shard-skl:          [FAIL][120] ([i915#2122]) -> [PASS][121]
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10562/shard-skl7/igt@kms_flip@plain-flip-ts-check@a-edp1.html
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-skl2/igt@kms_flip@plain-flip-ts-check@a-edp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile:
    - shard-iclb:         [SKIP][122] -> [PASS][123]
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10562/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile.html
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-iclb7/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile.html

  * igt@kms_hdr@bpc-switch-dpms:
    - shard-skl:          [FAIL][124] ([i915#1188]) -> [PASS][125]
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10562/shard-skl1/igt@kms_hdr@bpc-switch-dpms.html
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-skl4/igt@kms_hdr@bpc-switch-dpms.html

  * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes:
    - shard-skl:          [INCOMPLETE][126] ([i915#198]) -> [PASS][127]
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10562/shard-skl9/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-skl3/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html

  * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes:
    - shard-tglb:         [INCOMPLETE][128] -> [PASS][129]
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10562/shard-tglb7/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-tglb5/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html

  * igt@kms_psr@psr2_cursor_mmap_cpu:
    - shard-iclb:         [SKIP][130] ([fdo#109441]) -> [PASS][131] +1 similar issue
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10562/shard-iclb4/igt@kms_psr@psr2_cursor_mmap_cpu.html
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html

  * igt@kms_vblank@pipe-c-ts-continuation-suspend:
    - shard-kbl:          [DMESG-WARN][132] ([i915#180]) -> [PASS][133] +2 similar issues
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10562/shard-kbl4/igt@kms_vblank@pipe-c-ts

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/index.html

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