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From: "Souza, Jose" <jose.souza@intel.com>
To: "ville.syrjala@linux.intel.com" <ville.syrjala@linux.intel.com>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH 13/16] drm/i915: Use intel_de_rmw() for tgl dkl phy programming
Date: Fri, 29 Oct 2021 22:01:34 +0000	[thread overview]
Message-ID: <1fb440194b8a69f5de47b37c3f4e281a268da58e.camel@intel.com> (raw)
In-Reply-To: <20211006204937.30774-14-ville.syrjala@linux.intel.com>

On Wed, 2021-10-06 at 23:49 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Streamline the code by using intel_de_rmw().

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 36 +++++++++++-------------
>  1 file changed, 16 insertions(+), 20 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 85247744e9dd..3c1b289df2c0 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1307,7 +1307,6 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
>  
>  	for (ln = 0; ln < 2; ln++) {
>  		int level;
> -		u32 val;
>  
>  		intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
>  			       HIP_INDEX_VAL(tc_port, ln));
> @@ -1316,29 +1315,26 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
>  
>  		level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
>  
> -		val = intel_de_read(dev_priv, DKL_TX_DPCNTL0(tc_port));
> -		val &= ~(DKL_TX_PRESHOOT_COEFF_MASK |
> -			 DKL_TX_DE_EMPAHSIS_COEFF_MASK |
> -			 DKL_TX_VSWING_CONTROL_MASK);
> -		val |= DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing) |
> -			DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) |
> -			DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot);
> -		intel_de_write(dev_priv, DKL_TX_DPCNTL0(tc_port), val);
> +		intel_de_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port),
> +			     DKL_TX_PRESHOOT_COEFF_MASK |
> +			     DKL_TX_DE_EMPAHSIS_COEFF_MASK |
> +			     DKL_TX_VSWING_CONTROL_MASK,
> +			     DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing) |
> +			     DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) |
> +			     DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot));
>  
>  		level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
>  
> -		val = intel_de_read(dev_priv, DKL_TX_DPCNTL1(tc_port));
> -		val &= ~(DKL_TX_PRESHOOT_COEFF_MASK |
> -			 DKL_TX_DE_EMPAHSIS_COEFF_MASK |
> -			 DKL_TX_VSWING_CONTROL_MASK);
> -		val |= DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing) |
> -			DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) |
> -			DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot);
> -		intel_de_write(dev_priv, DKL_TX_DPCNTL1(tc_port), val);
> +		intel_de_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port),
> +			     DKL_TX_PRESHOOT_COEFF_MASK |
> +			     DKL_TX_DE_EMPAHSIS_COEFF_MASK |
> +			     DKL_TX_VSWING_CONTROL_MASK,
> +			     DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing) |
> +			     DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) |
> +			     DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot));
>  
> -		val = intel_de_read(dev_priv, DKL_TX_DPCNTL2(tc_port));
> -		val &= ~DKL_TX_DP20BITMODE;
> -		intel_de_write(dev_priv, DKL_TX_DPCNTL2(tc_port), val);
> +		intel_de_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port),
> +			     DKL_TX_DP20BITMODE, 0);
>  	}
>  }
>  


  reply	other threads:[~2021-10-29 22:02 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-06 20:49 [Intel-gfx] [PATCH 00/16] drm/i915: DP per-lane drive settings for icl+ Ville Syrjala
2021-10-06 20:49 ` [Intel-gfx] [PATCH 01/16] drm/i915: Remove pointless extra namespace from dkl/snps buf trans structs Ville Syrjala
2021-10-08 10:18   ` Jani Nikula
2021-10-06 20:49 ` [Intel-gfx] [PATCH 02/16] drm/i915: Shrink {icl_mg, tgl_dkl}_phy_ddi_buf_trans Ville Syrjala
2021-10-08 10:19   ` Jani Nikula
2021-10-06 20:49 ` [Intel-gfx] [PATCH 03/16] drm/i915: Use standard form terminating condition for lane for loops Ville Syrjala
2021-10-08 10:19   ` Jani Nikula
2021-10-06 20:49 ` [Intel-gfx] [PATCH 04/16] drm/i915: Add all per-lane register definitions for icl combo phy Ville Syrjala
2021-10-08 10:21   ` Jani Nikula
2021-10-08 10:29     ` Ville Syrjälä
2021-10-06 20:49 ` [Intel-gfx] [PATCH 05/16] drm/i915: Remove dead DKL_TX_LOADGEN_SHARING_PMD_DISABLE stuff Ville Syrjala
2021-10-08 10:23   ` Jani Nikula
2021-10-06 20:49 ` [Intel-gfx] [PATCH 06/16] drm/i915: Extract icl_combo_phy_loadgen_select() Ville Syrjala
2021-10-08 10:25   ` Jani Nikula
2021-10-06 20:49 ` [Intel-gfx] [PATCH 07/16] drm/i915: Stop using group access when progrmming icl combo phy TX Ville Syrjala
2021-10-29 21:53   ` Souza, Jose
2021-10-06 20:49 ` [Intel-gfx] [PATCH 08/16] drm/i915: Query the vswing levels per-lane for icl combo phy Ville Syrjala
2021-10-29 21:57   ` Souza, Jose
2021-11-01 10:11     ` Ville Syrjälä
2021-11-01 17:36       ` Souza, Jose
2021-10-06 20:49 ` [Intel-gfx] [PATCH 09/16] drm/i915: Query the vswing levels per-lane for icl mg phy Ville Syrjala
2021-10-29 21:59   ` Souza, Jose
2021-11-01  9:56     ` Ville Syrjälä
2021-10-06 20:49 ` [Intel-gfx] [PATCH 10/16] drm/i915: Query the vswing levels per-lane for tgl dkl phy Ville Syrjala
2021-10-29 21:59   ` Souza, Jose
2021-10-06 20:49 ` [Intel-gfx] [PATCH 11/16] drm/i915: Query the vswing levels per-lane for snps phy Ville Syrjala
2021-10-29 22:00   ` Souza, Jose
2021-10-06 20:49 ` [Intel-gfx] [PATCH 12/16] drm/i915: Enable per-lane drive settings for icl+ Ville Syrjala
2021-10-29 22:04   ` Souza, Jose
2021-10-06 20:49 ` [Intel-gfx] [PATCH 13/16] drm/i915: Use intel_de_rmw() for tgl dkl phy programming Ville Syrjala
2021-10-29 22:01   ` Souza, Jose [this message]
2021-10-06 20:49 ` [Intel-gfx] [PATCH 14/16] drm/i915: Use intel_de_rmw() for icl mg " Ville Syrjala
2021-10-29 22:02   ` Souza, Jose
2021-10-06 20:49 ` [Intel-gfx] [PATCH 15/16] drm/i915: Use intel_de_rmw() for icl combo " Ville Syrjala
2021-10-29 22:02   ` Souza, Jose
2021-10-06 20:49 ` [Intel-gfx] [PATCH 16/16] drm/i915: Fix icl+ combo phy static lane power down setup Ville Syrjala
2021-10-28 13:25   ` Imre Deak
2021-10-28 17:43   ` Jani Nikula
2021-10-07  0:18 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: DP per-lane drive settings for icl+ Patchwork
2021-10-07  0:20 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-10-07  0:52 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-10-07  3:08 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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