From: Jani Nikula <jani.nikula@linux.intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>,
intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 05/16] drm/i915: Remove dead DKL_TX_LOADGEN_SHARING_PMD_DISABLE stuff
Date: Fri, 08 Oct 2021 13:23:30 +0300 [thread overview]
Message-ID: <87v927x1b1.fsf@intel.com> (raw)
In-Reply-To: <20211006204937.30774-6-ville.syrjala@linux.intel.com>
On Wed, 06 Oct 2021, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> DKL_TX_LOADGEN_SHARING_PMD_DISABLE doesn't even seem to exist,
> also the spec says to skip all loadgen stuff.
>
> The code was dead anyway since it wasn't actually writing the value
> anywhere.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
I admit not looking this up in spec, but this is dead code removal
anyway...
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 8 --------
> drivers/gpu/drm/i915/i915_reg.h | 1 -
> 2 files changed, 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 0c9ed705af47..b8ec53d9e3b0 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1309,14 +1309,6 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
> val = intel_de_read(dev_priv, DKL_TX_DPCNTL2(tc_port));
> val &= ~DKL_TX_DP20BITMODE;
> intel_de_write(dev_priv, DKL_TX_DPCNTL2(tc_port), val);
> -
> - if ((intel_crtc_has_dp_encoder(crtc_state) &&
> - crtc_state->port_clock == 162000) ||
> - (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
> - crtc_state->port_clock == 594000))
> - val |= DKL_TX_LOADGEN_SHARING_PMD_DISABLE;
> - else
> - val &= ~DKL_TX_LOADGEN_SHARING_PMD_DISABLE;
> }
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 5e7a55e6ef50..8c8152de643f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -11022,7 +11022,6 @@ enum skl_power_gate {
> _DKL_TX_DPCNTL1)
>
> #define _DKL_TX_DPCNTL2 0x2C8
> -#define DKL_TX_LOADGEN_SHARING_PMD_DISABLE REG_BIT(12)
> #define DKL_TX_DP20BITMODE (1 << 2)
> #define DKL_TX_DPCNTL2(tc_port) _MMIO(_PORT(tc_port, \
> _DKL_PHY1_BASE, \
--
Jani Nikula, Intel Open Source Graphics Center
next prev parent reply other threads:[~2021-10-08 10:23 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-06 20:49 [Intel-gfx] [PATCH 00/16] drm/i915: DP per-lane drive settings for icl+ Ville Syrjala
2021-10-06 20:49 ` [Intel-gfx] [PATCH 01/16] drm/i915: Remove pointless extra namespace from dkl/snps buf trans structs Ville Syrjala
2021-10-08 10:18 ` Jani Nikula
2021-10-06 20:49 ` [Intel-gfx] [PATCH 02/16] drm/i915: Shrink {icl_mg, tgl_dkl}_phy_ddi_buf_trans Ville Syrjala
2021-10-08 10:19 ` Jani Nikula
2021-10-06 20:49 ` [Intel-gfx] [PATCH 03/16] drm/i915: Use standard form terminating condition for lane for loops Ville Syrjala
2021-10-08 10:19 ` Jani Nikula
2021-10-06 20:49 ` [Intel-gfx] [PATCH 04/16] drm/i915: Add all per-lane register definitions for icl combo phy Ville Syrjala
2021-10-08 10:21 ` Jani Nikula
2021-10-08 10:29 ` Ville Syrjälä
2021-10-06 20:49 ` [Intel-gfx] [PATCH 05/16] drm/i915: Remove dead DKL_TX_LOADGEN_SHARING_PMD_DISABLE stuff Ville Syrjala
2021-10-08 10:23 ` Jani Nikula [this message]
2021-10-06 20:49 ` [Intel-gfx] [PATCH 06/16] drm/i915: Extract icl_combo_phy_loadgen_select() Ville Syrjala
2021-10-08 10:25 ` Jani Nikula
2021-10-06 20:49 ` [Intel-gfx] [PATCH 07/16] drm/i915: Stop using group access when progrmming icl combo phy TX Ville Syrjala
2021-10-29 21:53 ` Souza, Jose
2021-10-06 20:49 ` [Intel-gfx] [PATCH 08/16] drm/i915: Query the vswing levels per-lane for icl combo phy Ville Syrjala
2021-10-29 21:57 ` Souza, Jose
2021-11-01 10:11 ` Ville Syrjälä
2021-11-01 17:36 ` Souza, Jose
2021-10-06 20:49 ` [Intel-gfx] [PATCH 09/16] drm/i915: Query the vswing levels per-lane for icl mg phy Ville Syrjala
2021-10-29 21:59 ` Souza, Jose
2021-11-01 9:56 ` Ville Syrjälä
2021-10-06 20:49 ` [Intel-gfx] [PATCH 10/16] drm/i915: Query the vswing levels per-lane for tgl dkl phy Ville Syrjala
2021-10-29 21:59 ` Souza, Jose
2021-10-06 20:49 ` [Intel-gfx] [PATCH 11/16] drm/i915: Query the vswing levels per-lane for snps phy Ville Syrjala
2021-10-29 22:00 ` Souza, Jose
2021-10-06 20:49 ` [Intel-gfx] [PATCH 12/16] drm/i915: Enable per-lane drive settings for icl+ Ville Syrjala
2021-10-29 22:04 ` Souza, Jose
2021-10-06 20:49 ` [Intel-gfx] [PATCH 13/16] drm/i915: Use intel_de_rmw() for tgl dkl phy programming Ville Syrjala
2021-10-29 22:01 ` Souza, Jose
2021-10-06 20:49 ` [Intel-gfx] [PATCH 14/16] drm/i915: Use intel_de_rmw() for icl mg " Ville Syrjala
2021-10-29 22:02 ` Souza, Jose
2021-10-06 20:49 ` [Intel-gfx] [PATCH 15/16] drm/i915: Use intel_de_rmw() for icl combo " Ville Syrjala
2021-10-29 22:02 ` Souza, Jose
2021-10-06 20:49 ` [Intel-gfx] [PATCH 16/16] drm/i915: Fix icl+ combo phy static lane power down setup Ville Syrjala
2021-10-28 13:25 ` Imre Deak
2021-10-28 17:43 ` Jani Nikula
2021-10-07 0:18 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: DP per-lane drive settings for icl+ Patchwork
2021-10-07 0:20 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-10-07 0:52 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-10-07 3:08 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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