From: Jesse Barnes <jbarnes@virtuousgeek.org>
To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: render p-state support for Sandybridge
Date: Fri, 10 Dec 2010 09:46:45 -0800 [thread overview]
Message-ID: <20101210094645.1d76cef6@jbarnes-desktop> (raw)
In-Reply-To: <b9dded$hbdo2a@orsmga002.jf.intel.com>
On Fri, 10 Dec 2010 09:37:00 +0000
Chris Wilson <chris@chris-wilson.co.uk> wrote:
> On Thu, 9 Dec 2010 15:00:46 -0800, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> > Note: this patch is just for comments/testing, it should not be
> > integrated at this time.
>
> So that's what drps stands for: dynamic render P-states! Jesse, at the
> very least shouldn't we apply the s/HAS_PCH_SPLIT/IS_GEN5/ in order not
> to be poking gen5 registers on gen6?
> -Chris
Or add an IS_IRONLAKE macro; that's what I was really looking for.
Will fix.
--
Jesse Barnes, Intel Open Source Technology Center
prev parent reply other threads:[~2010-12-10 17:46 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-12-09 23:00 [PATCH] drm/i915: render p-state support for Sandybridge Jesse Barnes
2010-12-10 9:37 ` Chris Wilson
2010-12-10 17:46 ` Jesse Barnes [this message]
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