Re: WIP POSTING_READ fix series

[Jesse Barnes <jbarnes@virtuousgeek.org>]

On Fri,  3 Jun 2011 12:20:18 -0700
Eric Anholt <eric@anholt.net> wrote:

> Here's what I've been talking about on IRC today.  Patch 3 appears to
> make things work.  Patch 4 should work, but re-breaks things (hangs
> but no dmesg complaints).  I want to understand why, but I'm running
> out of theories.  Perhaps there's some period of time where a write
> has been PCI write posted but has not yet appeared in the GT FIFO?  Or
> perhaps there's some time after GT FIFO but before it's really handled
> by hardware?  Note that I was also able to fix the problem without
> this series by just POSTING_READing 4 times instead of 1.

The fact that patch 4 re-introduces the issue makes me think we still
have a timing issue separate from the FIFO depth or force wake
handling.  How long does the function take to complete in both cases?
Does simply delaying the posting_read to match the approximate force
wake get/put time also get rid of the missed interrupts?  If so, maybe
we're missing some other aspect of the interrupt masking dance instead?

-- 
Jesse Barnes, Intel Open Source Technology Center