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From: Eric Anholt <eric@anholt.net>
To: intel-gfx@lists.freedesktop.org
Subject: WIP POSTING_READ fix series
Date: Fri,  3 Jun 2011 12:20:18 -0700	[thread overview]
Message-ID: <1307128822-9709-1-git-send-email-eric@anholt.net> (raw)

Here's what I've been talking about on IRC today.  Patch 3 appears to
make things work.  Patch 4 should work, but re-breaks things (hangs
but no dmesg complaints).  I want to understand why, but I'm running
out of theories.  Perhaps there's some period of time where a write
has been PCI write posted but has not yet appeared in the GT FIFO?  Or
perhaps there's some time after GT FIFO but before it's really handled
by hardware?  Note that I was also able to fix the problem without
this series by just POSTING_READing 4 times instead of 1.

             reply	other threads:[~2011-06-03 19:20 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-06-03 19:20 Eric Anholt [this message]
2011-06-03 19:20 ` [PATCH 1/4] drm/i915: Control gen6 ring interrupts through a single mask field Eric Anholt
2011-06-03 19:20 ` [PATCH 2/4] drm/i915: Move the forcewake refcounting to a spinlock Eric Anholt
2011-06-03 19:20 ` [PATCH 3/4] drm/i915: Fix missed IRQs on gen6 Eric Anholt
2011-06-03 19:20 ` [PATCH 4/4] drm/i915: Try removing the forcewake get/put around the fifo counting Eric Anholt
2011-06-03 21:05 ` WIP POSTING_READ fix series Jesse Barnes

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