From: Ben Widawsky <ben@bwidawsk.net>
To: Daniel Vetter <daniel@ffwll.ch>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>,
intel-gfx <intel-gfx@lists.freedesktop.org>
Subject: Re: [PATCH 2/3] drm/i915: Rename PIPE_CONTROL bit defines to be less terse.
Date: Sat, 15 Oct 2011 12:26:19 -0700 [thread overview]
Message-ID: <20111015122619.0e5c0380@bwidawsk.net> (raw)
In-Reply-To: <20111015140117.GB2819@phenom.ffwll.local>
On Sat, 15 Oct 2011 16:01:17 +0200
Daniel Vetter <daniel@ffwll.ch> wrote:
> On Tue, Oct 11, 2011 at 04:51:16PM -0700, Ben Widawsky wrote:
> > I thought we all agreed that "PIPE_CONTROL_WRITE_FLUSH" doesn't make
> > sense for Gen6? Or was that just me agreeing with myself?
>
> I couldn't find any comment of yours to that effect ... :p You'd be much
> happier if I add a RENDER_CACHE_FLUSH for gen6+?
>
> Cheers, Daniel
I really want to make these things match the docs as closely as
possible. Especially PIPE_CONTROL which I know I will refer to over and
over. Like I said, r-b from me either way, but if you redo the series
anyway for some reason, I would prefer that.
Ben
next prev parent reply other threads:[~2011-10-15 19:26 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-10-11 21:41 [PATCH 1/3] drm/i915: Remove implied length of 2 from GFX_OP_PIPE_CONTROL #define Daniel Vetter
2011-10-11 21:41 ` [PATCH 2/3] drm/i915: Rename PIPE_CONTROL bit defines to be less terse Daniel Vetter
2011-10-11 23:51 ` Ben Widawsky
2011-10-15 14:01 ` Daniel Vetter
2011-10-15 19:26 ` Ben Widawsky [this message]
2011-10-11 21:41 ` [PATCH 3/3] drm/i915: Use PIPE_CONTROL for flushing on gen6+ Daniel Vetter
2011-10-16 8:23 ` [PATCH] " Daniel Vetter
2011-10-17 1:27 ` Ben Widawsky
2011-10-11 23:11 ` [PATCH 1/3] drm/i915: Remove implied length of 2 from GFX_OP_PIPE_CONTROL #define Kenneth Graunke
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