[PATCH] drm/i915: enable cacheable objects on Ivybridge

[PATCH] drm/i915: enable cacheable objects on Ivybridge

[Jesse Barnes]

IVB supports these bits as well.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_gem.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index d18b07a..c0d26b1 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3613,7 +3613,7 @@ struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
 	obj->base.write_domain = I915_GEM_DOMAIN_CPU;
 	obj->base.read_domains = I915_GEM_DOMAIN_CPU;
 
-	if (IS_GEN6(dev)) {
+	if (IS_GEN6(dev) || IS_GEN7(dev)) {
 		/* On Gen6, we can have the GPU use the LLC (the CPU
 		 * cache) for about a 10% performance improvement
 		 * compared to uncached.  Graphics requests other than
-- 
1.7.4.1

Re: [PATCH] drm/i915: enable cacheable objects on Ivybridge

[Daniel Vetter]

On Thu, Nov 03, 2011 at 02:15:13PM -0700, Jesse Barnes wrote:
> IVB supports these bits as well.
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Oh dear, collective blindness ....

Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: [PATCH] drm/i915: enable cacheable objects on Ivybridge

[Eugeni Dodonov]

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On Thu, Nov 3, 2011 at 19:15, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:

> IVB supports these bits as well.
>
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
>

Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>

-- 
Eugeni Dodonov
<http://eugeni.dodonov.net/>

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