* i915 SNB: hotplug events when charging causing poor interactivity
[not found] <CAMVG2suPthuTLfpWH0PJ9uFibNtGAJk5U8BA6RK4x7JcSZP-Ww@mail.gmail.com>
@ 2012-02-16 11:44 ` Daniel J Blueman
2012-02-16 13:07 ` Daniel Vetter
0 siblings, 1 reply; 5+ messages in thread
From: Daniel J Blueman @ 2012-02-16 11:44 UTC (permalink / raw)
To: Eric Anholt, Keith Packard; +Cc: intel-gfx
Keith, Eric,
When charging Dell E5420 laptops, I see the Sandy Bridge South Display
Engine port C hotplug interrupt fire consistently at around 20Hz. Each
scan on the connectors results in ~100ms hold time for the mode_config
mutex which blocks eg the cursor set ioctl (due to the I2C read
timeouts across the connectors), resulting in terrible GUI
interactivity.
Notably, when only using battery or only using AC, the port C
interrupts don't fire. It feels like the platform is using South
Display Port C for GPIO/I2C; setting the port C pulse duration from
2ms to 100ms doesn't change the behaviour. I'll dump off the GPIO
settings, but what else is good to debug this?
Also, have you come across this kind of pattern before, eg a platform
using these GPIO ports for the something (in this case, feels like the
EC/battery)? Judging by the lack of a quirks, I'd say not. Perhaps
also I should dump off the SDE port C IIR mask register before we
reset it, in case the BIOS intentionally masks out port C hotplug
events.
Thanks,
Daniel
--
Daniel J Blueman
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: i915 SNB: hotplug events when charging causing poor interactivity
2012-02-16 11:44 ` i915 SNB: hotplug events when charging causing poor interactivity Daniel J Blueman
@ 2012-02-16 13:07 ` Daniel Vetter
2012-02-21 13:37 ` Daniel J Blueman
0 siblings, 1 reply; 5+ messages in thread
From: Daniel Vetter @ 2012-02-16 13:07 UTC (permalink / raw)
To: Daniel J Blueman; +Cc: intel-gfx
On Thu, Feb 16, 2012 at 11:44:46AM +0000, Daniel J Blueman wrote:
> When charging Dell E5420 laptops, I see the Sandy Bridge South Display
> Engine port C hotplug interrupt fire consistently at around 20Hz. Each
> scan on the connectors results in ~100ms hold time for the mode_config
> mutex which blocks eg the cursor set ioctl (due to the I2C read
> timeouts across the connectors), resulting in terrible GUI
> interactivity.
We know about this locking issue - it's much worse on platforms where we
need to do load-detect hotplug detection or if for whatever reasons it
takes ages to grab the edid from your screen. The Great Plan (tm) is to
add a per-crtc mutex so that cursor updates and pageflips can continue
while someone else is holding the config_mutex to do background stuff like
hotplug handling. Unfortunately there's tons of other important stuff on
my todo :(
> Notably, when only using battery or only using AC, the port C
> interrupts don't fire. It feels like the platform is using South
> Display Port C for GPIO/I2C; setting the port C pulse duration from
> 2ms to 100ms doesn't change the behaviour. I'll dump off the GPIO
> settings, but what else is good to debug this?
Yep, dumping the register state (intel_reg_dumper from intel-gpu-tools is
handy for that) in the different situations sounds useful.
> Also, have you come across this kind of pattern before, eg a platform
> using these GPIO ports for the something (in this case, feels like the
> EC/battery)? Judging by the lack of a quirks, I'd say not. Perhaps
> also I should dump off the SDE port C IIR mask register before we
> reset it, in case the BIOS intentionally masks out port C hotplug
> events.
If this is indeed the bios we need to quirk this away. But I think we
should check first whether we don't butcher something else accidently.
-Daniel
--
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: i915 SNB: hotplug events when charging causing poor interactivity
2012-02-16 13:07 ` Daniel Vetter
@ 2012-02-21 13:37 ` Daniel J Blueman
2012-02-21 20:02 ` Daniel Vetter
0 siblings, 1 reply; 5+ messages in thread
From: Daniel J Blueman @ 2012-02-21 13:37 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 1403 bytes --]
On 16 February 2012 13:07, Daniel Vetter <daniel@ffwll.ch> wrote:
> On Thu, Feb 16, 2012 at 11:44:46AM +0000, Daniel J Blueman wrote:
>> When charging Dell E5420 laptops, I see the Sandy Bridge South Display
>> Engine port C hotplug interrupt fire consistently at around 20Hz. Each
[]
>> Notably, when only using battery or only using AC, the port C
>> interrupts don't fire. It feels like the platform is using South
>> Display Port C for GPIO/I2C; setting the port C pulse duration from
>> 2ms to 100ms doesn't change the behaviour. I'll dump off the GPIO
>> settings, but what else is good to debug this?
>
> Yep, dumping the register state (intel_reg_dumper from intel-gpu-tools is
> handy for that) in the different situations sounds useful.
[]
> If this is indeed the bios we need to quirk this away. But I think we
> should check first whether we don't butcher something else accidently.
When charging the battery, I see the SDE_PORTB_HOTPLUG, PORTC, PORTD
and SDE_AUX_MASK bits set (sometimes at different times) at ~20Hz
until the battery is charged, which is disconcerting.
Hotplugging a HDMI cable, SDE_PORTB_HOTPLUG and SDE_AUX_MASK bits are
set once, so we can't mask these on this platform.
Attached are the reg dumps. We see the backlight register
(BLC_PWM_CPU_CTL) and the A surface register (DSPASURF) vary across
multiple reads as expected.
Any ideas?
Daniel
--
Daniel J Blueman
[-- Attachment #2: i915-regs-ac.txt --]
[-- Type: text/plain, Size: 11538 bytes --]
PGETBL_CTL: 0x00000000
GEN6_INSTDONE_1: 0xfffffffe
GEN6_INSTDONE_2: 0xffffffff
CPU_VGACNTRL: 0x80000000 (disabled)
DIGITAL_PORT_HOTPLUG_CNTRL: 0x00000000
RR_HW_CTL: 0x00000000 (low 0, high 0)
FDI_PLL_BIOS_0: 0xffffffff
FDI_PLL_BIOS_1: 0xffffffff
FDI_PLL_BIOS_2: 0xffffffff
DISPLAY_PORT_PLL_BIOS_0: 0xffffffff
DISPLAY_PORT_PLL_BIOS_1: 0xffffffff
DISPLAY_PORT_PLL_BIOS_2: 0xffffffff
FDI_PLL_FREQ_CTL: 0xffffffff
PIPEACONF: 0xc0000050 (enabled, active, 6bpc)
HTOTAL_A: 0x080d063f (1600 active, 2062 total)
HBLANK_A: 0x080d063f (1600 start, 2062 end)
HSYNC_A: 0x06a9067f (1664 start, 1706 end)
VTOTAL_A: 0x039b0383 (900 active, 924 total)
VBLANK_A: 0x039b0383 (900 start, 924 end)
VSYNC_A: 0x03890386 (903 start, 906 end)
VSYNCSHIFT_A: 0x00000000
PIPEASRC: 0x063f0383 (1600, 900)
PIPEA_DATA_M1: 0x7e1f6bc0 (TU 64, val 0x1f6bc0 2059200)
PIPEA_DATA_N1: 0x0041eb00 (val 0x41eb00 4320000)
PIPEA_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
PIPEA_DATA_N2: 0x00000000 (val 0x0 0)
PIPEA_LINK_M1: 0x0001bee0 (val 0x1bee0 114400)
PIPEA_LINK_N1: 0x00041eb0 (val 0x41eb0 270000)
PIPEA_LINK_M2: 0x00000000 (val 0x0 0)
PIPEA_LINK_N2: 0x00000000 (val 0x0 0)
DSPACNTR: 0xd8004400 (enabled)
DSPABASE: 0x00000000
DSPASTRIDE: 0x00001a00 (104)
DSPASURF: 0x005e7000
DSPATILEOFF: 0x00000000 (0, 0)
PIPEBCONF: 0x00000000 (disabled, inactive, 8bpc)
HTOTAL_B: 0x00000000 (1 active, 1 total)
HBLANK_B: 0x00000000 (1 start, 1 end)
HSYNC_B: 0x00000000 (1 start, 1 end)
VTOTAL_B: 0x00000000 (1 active, 1 total)
VBLANK_B: 0x00000000 (1 start, 1 end)
VSYNC_B: 0x00000000 (1 start, 1 end)
VSYNCSHIFT_B: 0x00000000
DSPBCNTR: 0x00004000 (disabled)
DSPBBASE: 0x00000000
DSPBSTRIDE: 0x00000000 (0)
DSPBSURF: 0x00000000
DSPBTILEOFF: 0x00000000 (0, 0)
PIPEBSRC: 0x00000000 (1, 1)
PIPEB_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
PIPEB_DATA_N1: 0x00000000 (val 0x0 0)
PIPEB_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
PIPEB_DATA_N2: 0x00000000 (val 0x0 0)
PIPEB_LINK_M1: 0x00000000 (val 0x0 0)
PIPEB_LINK_N1: 0x00000000 (val 0x0 0)
PIPEB_LINK_M2: 0x00000000 (val 0x0 0)
PIPEB_LINK_N2: 0x00000000 (val 0x0 0)
PFA_CTL_1: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1)
PFA_CTL_2: 0x00007e3e (vscale 0.986267)
PFA_CTL_3: 0x00003f1f (vscale initial phase 0.493134)
PFA_CTL_4: 0x00007ce0 (hscale 0.975586)
PFA_WIN_POS: 0x00000000 (0, 0)
PFA_WIN_SIZE: 0x00000000 (0, 0)
PFB_CTL_1: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1)
PFB_CTL_2: 0x00000000 (vscale 0.000000)
PFB_CTL_3: 0x00000000 (vscale initial phase 0.000000)
PFB_CTL_4: 0x00000000 (hscale 0.000000)
PFB_WIN_POS: 0x00000000 (0, 0)
PFB_WIN_SIZE: 0x00000000 (0, 0)
PCH_DREF_CONTROL: 0x00001402 (cpu source disable, ssc_source enable, nonspread_source enable, superspread_source disable, ssc4_mode downspread, ssc1 enable, ssc4 disable)
PCH_RAWCLK_FREQ: 0x0000007d (FDL_TP1 timer 0.5us, FDL_TP2 timer 1.5us, freq 125)
PCH_DPLL_TMR_CFG: 0x0271186a
PCH_SSC4_PARMS: 0x01204860
PCH_SSC4_AUX_PARMS: 0x000029c5
PCH_DPLL_SEL: 0x00000008 (TransA DPLL enable (DPLL A), TransB DPLL disable (DPLL (null)))
PCH_DPLL_ANALOG_CTL: 0x00008000
PCH_DPLL_A: 0x89086008 (enable, sdvo high speed no, mode LVDS, p2 Div 7, FPA0 P1 4, FPA1 P1 4, refclk SSC, sdvo/hdmi mul 1)
PCH_DPLL_B: 0x04800080 (disable, sdvo high speed no, mode (null), p2 (null), FPA0 P1 8, FPA1 P1 8, refclk default 120Mhz, sdvo/hdmi mul 1)
PCH_FPA0: 0x00010c08 (n = 1, m1 = 12, m2 = 8)
PCH_FPA1: 0x00010c08 (n = 1, m1 = 12, m2 = 8)
PCH_FPB0: 0x00030d07 (n = 3, m1 = 13, m2 = 7)
PCH_FPB1: 0x00030d07 (n = 3, m1 = 13, m2 = 7)
TRANS_HTOTAL_A: 0x080d063f (1600 active, 2062 total)
TRANS_HBLANK_A: 0x080d063f (1600 start, 2062 end)
TRANS_HSYNC_A: 0x06a9067f (1664 start, 1706 end)
TRANS_VTOTAL_A: 0x039b0383 (900 active, 924 total)
TRANS_VBLANK_A: 0x039b0383 (900 start, 924 end)
TRANS_VSYNC_A: 0x03890386 (903 start, 906 end)
TRANSA_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
TRANSA_DATA_N1: 0x00000000 (val 0x0 0)
TRANSA_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
TRANSA_DATA_N2: 0x00000000 (val 0x0 0)
TRANSA_DP_LINK_M1: 0x00000000 (val 0x0 0)
TRANSA_DP_LINK_N1: 0x00000000 (val 0x0 0)
TRANSA_DP_LINK_M2: 0x00000000 (val 0x0 0)
TRANSA_DP_LINK_N2: 0x00000000 (val 0x0 0)
TRANS_HTOTAL_B: 0x00000000 (1 active, 1 total)
TRANS_HBLANK_B: 0x00000000 (1 start, 1 end)
TRANS_HSYNC_B: 0x00000000 (1 start, 1 end)
TRANS_VTOTAL_B: 0x00000000 (1 active, 1 total)
TRANS_VBLANK_B: 0x00000000 (1 start, 1 end)
TRANS_VSYNC_B: 0x00000000 (1 start, 1 end)
TRANSB_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
TRANSB_DATA_N1: 0x00000000 (val 0x0 0)
TRANSB_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
TRANSB_DATA_N2: 0x00000000 (val 0x0 0)
TRANSB_DP_LINK_M1: 0x00000000 (val 0x0 0)
TRANSB_DP_LINK_N1: 0x00000000 (val 0x0 0)
TRANSB_DP_LINK_M2: 0x00000000 (val 0x0 0)
TRANSB_DP_LINK_N2: 0x00000000 (val 0x0 0)
TRANS_HTOTAL_C: 0x00000000 (1 active, 1 total)
TRANS_HBLANK_C: 0x00000000 (1 start, 1 end)
TRANS_HSYNC_C: 0x00000000 (1 start, 1 end)
TRANS_VTOTAL_C: 0x00000000 (1 active, 1 total)
TRANS_VBLANK_C: 0x00000000 (1 start, 1 end)
TRANS_VSYNC_C: 0x00000000 (1 start, 1 end)
TRANSC_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
TRANSC_DATA_N1: 0x00000000 (val 0x0 0)
TRANSC_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
TRANSC_DATA_N2: 0x00000000 (val 0x0 0)
TRANSC_DP_LINK_M1: 0x00000000 (val 0x0 0)
TRANSC_DP_LINK_N1: 0x00000000 (val 0x0 0)
TRANSC_DP_LINK_M2: 0x00000000 (val 0x0 0)
TRANSC_DP_LINK_N2: 0x00000000 (val 0x0 0)
TRANSACONF: 0xc0000000 (enable, active)
TRANSBCONF: 0x00000000 (disable, inactive)
TRANSCCONF: 0x00000000 (disable, inactive)
FDI_TXA_CTL: 0xb00c4000 (enable, train pattern not train, voltage swing 0.4V,pre-emphasis 0dB, port width X2, enhanced framing enable, FDI PLL enable, scrambing enable, master mode disable)
FDI_TXB_CTL: 0x00040000 (disable, train pattern pattern_1, voltage swing 0.4V,pre-emphasis 0dB, port width X1, enhanced framing enable, FDI PLL disable, scrambing enable, master mode disable)
FDI_TXC_CTL: 0x00000000 (disable, train pattern pattern_1, voltage swing 0.4V,pre-emphasis 0dB, port width X1, enhanced framing disable, FDI PLL disable, scrambing enable, master mode disable)
FDI_RXA_CTL: 0x800a2350 (enable, train pattern not train, port width X2, 6bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL enable,FS ecc disable, FE ecc disable, FS err report enable, FE err report enable,scrambing enable, enhanced framing enable, PCDClk)
FDI_RXB_CTL: 0x00000040 (disable, train pattern pattern_1, port width X1, 8bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL disable,FS ecc disable, FE ecc disable, FS err report disable, FE err report disable,scrambing enable, enhanced framing enable, RawClk)
FDI_RXC_CTL: 0x00000040 (disable, train pattern pattern_1, port width X1, 8bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL disable,FS ecc disable, FE ecc disable, FS err report disable, FE err report disable,scrambing enable, enhanced framing enable, RawClk)
FDI_RXA_MISC: 0x00000080 (FDI Delay 128)
FDI_RXB_MISC: 0x00000080 (FDI Delay 128)
FDI_RXC_MISC: 0x00000080 (FDI Delay 128)
FDI_RXA_TUSIZE1: 0x7e000000
FDI_RXA_TUSIZE2: 0x7e000000
FDI_RXB_TUSIZE1: 0x7e000000
FDI_RXB_TUSIZE2: 0x7e000000
FDI_RXC_TUSIZE1: 0x7e000000
FDI_RXC_TUSIZE2: 0x7e000000
FDI_PLL_CTL_1: 0x7e000000
FDI_PLL_CTL_2: 0x7e000000
FDI_RXA_IIR: 0x00000000
FDI_RXA_IMR: 0x000008ff
FDI_RXB_IIR: 0x00000000
FDI_RXB_IMR: 0x000008ff
PCH_ADPA: 0x00f40000 (disabled, transcoder A, -hsync, -vsync)
HDMIB: 0x0000001c (disabled pipe A 8bpc SDVO DVI audio disabled +vsync +hsync detected)
HDMIC: 0x0000001c (disabled pipe A 8bpc SDVO DVI audio disabled +vsync +hsync detected)
HDMID: 0x0000001c (disabled pipe A 8bpc SDVO DVI audio disabled +vsync +hsync detected)
PCH_LVDS: 0x8020033e (enabled, pipe A, 18 bit, 2 channels)
CPU_eDP_A: 0x00000018
PCH_DP_B: 0x00000004
PCH_DP_C: 0x00000004
PCH_DP_D: 0x00000004
TRANS_DP_CTL_A: 0x60000418 (disable port none 6bpc +vsync +hsync)
TRANS_DP_CTL_B: 0x60000018 (disable port none 8bpc +vsync +hsync)
TRANS_DP_CTL_C: 0x60000018 (disable port none 8bpc +vsync +hsync)
BLC_PWM_CPU_CTL2: 0x80000000
BLC_PWM_CPU_CTL: 0x00001312
BLC_PWM_PCH_CTL1: 0x80000000
BLC_PWM_PCH_CTL2: 0x13121312
PCH_PP_STATUS: 0xc0000008 (on, ready, sequencing idle)
PCH_PP_CONTROL: 0xabcd0003 (blacklight disabled, power down on reset, panel on)
PCH_PP_ON_DELAYS: 0x019008fc
PCH_PP_OFF_DELAYS: 0x019008fc
PCH_PP_DIVISOR: 0x00186906
[-- Attachment #3: i915-regs-charge.txt --]
[-- Type: text/plain, Size: 11538 bytes --]
PGETBL_CTL: 0x00000000
GEN6_INSTDONE_1: 0xfffffffe
GEN6_INSTDONE_2: 0xffffffff
CPU_VGACNTRL: 0x80000000 (disabled)
DIGITAL_PORT_HOTPLUG_CNTRL: 0x00000000
RR_HW_CTL: 0x00000000 (low 0, high 0)
FDI_PLL_BIOS_0: 0xffffffff
FDI_PLL_BIOS_1: 0xffffffff
FDI_PLL_BIOS_2: 0xffffffff
DISPLAY_PORT_PLL_BIOS_0: 0xffffffff
DISPLAY_PORT_PLL_BIOS_1: 0xffffffff
DISPLAY_PORT_PLL_BIOS_2: 0xffffffff
FDI_PLL_FREQ_CTL: 0xffffffff
PIPEACONF: 0xc0000050 (enabled, active, 6bpc)
HTOTAL_A: 0x080d063f (1600 active, 2062 total)
HBLANK_A: 0x080d063f (1600 start, 2062 end)
HSYNC_A: 0x06a9067f (1664 start, 1706 end)
VTOTAL_A: 0x039b0383 (900 active, 924 total)
VBLANK_A: 0x039b0383 (900 start, 924 end)
VSYNC_A: 0x03890386 (903 start, 906 end)
VSYNCSHIFT_A: 0x00000000
PIPEASRC: 0x063f0383 (1600, 900)
PIPEA_DATA_M1: 0x7e1f6bc0 (TU 64, val 0x1f6bc0 2059200)
PIPEA_DATA_N1: 0x0041eb00 (val 0x41eb00 4320000)
PIPEA_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
PIPEA_DATA_N2: 0x00000000 (val 0x0 0)
PIPEA_LINK_M1: 0x0001bee0 (val 0x1bee0 114400)
PIPEA_LINK_N1: 0x00041eb0 (val 0x41eb0 270000)
PIPEA_LINK_M2: 0x00000000 (val 0x0 0)
PIPEA_LINK_N2: 0x00000000 (val 0x0 0)
DSPACNTR: 0xd8004400 (enabled)
DSPABASE: 0x00000000
DSPASTRIDE: 0x00001a00 (104)
DSPASURF: 0x05391000
DSPATILEOFF: 0x00000000 (0, 0)
PIPEBCONF: 0x00000000 (disabled, inactive, 8bpc)
HTOTAL_B: 0x00000000 (1 active, 1 total)
HBLANK_B: 0x00000000 (1 start, 1 end)
HSYNC_B: 0x00000000 (1 start, 1 end)
VTOTAL_B: 0x00000000 (1 active, 1 total)
VBLANK_B: 0x00000000 (1 start, 1 end)
VSYNC_B: 0x00000000 (1 start, 1 end)
VSYNCSHIFT_B: 0x00000000
DSPBCNTR: 0x00004000 (disabled)
DSPBBASE: 0x00000000
DSPBSTRIDE: 0x00000000 (0)
DSPBSURF: 0x00000000
DSPBTILEOFF: 0x00000000 (0, 0)
PIPEBSRC: 0x00000000 (1, 1)
PIPEB_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
PIPEB_DATA_N1: 0x00000000 (val 0x0 0)
PIPEB_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
PIPEB_DATA_N2: 0x00000000 (val 0x0 0)
PIPEB_LINK_M1: 0x00000000 (val 0x0 0)
PIPEB_LINK_N1: 0x00000000 (val 0x0 0)
PIPEB_LINK_M2: 0x00000000 (val 0x0 0)
PIPEB_LINK_N2: 0x00000000 (val 0x0 0)
PFA_CTL_1: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1)
PFA_CTL_2: 0x00007e3e (vscale 0.986267)
PFA_CTL_3: 0x00003f1f (vscale initial phase 0.493134)
PFA_CTL_4: 0x00007ce0 (hscale 0.975586)
PFA_WIN_POS: 0x00000000 (0, 0)
PFA_WIN_SIZE: 0x00000000 (0, 0)
PFB_CTL_1: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1)
PFB_CTL_2: 0x00000000 (vscale 0.000000)
PFB_CTL_3: 0x00000000 (vscale initial phase 0.000000)
PFB_CTL_4: 0x00000000 (hscale 0.000000)
PFB_WIN_POS: 0x00000000 (0, 0)
PFB_WIN_SIZE: 0x00000000 (0, 0)
PCH_DREF_CONTROL: 0x00001402 (cpu source disable, ssc_source enable, nonspread_source enable, superspread_source disable, ssc4_mode downspread, ssc1 enable, ssc4 disable)
PCH_RAWCLK_FREQ: 0x0000007d (FDL_TP1 timer 0.5us, FDL_TP2 timer 1.5us, freq 125)
PCH_DPLL_TMR_CFG: 0x0271186a
PCH_SSC4_PARMS: 0x01204860
PCH_SSC4_AUX_PARMS: 0x000029c5
PCH_DPLL_SEL: 0x00000008 (TransA DPLL enable (DPLL A), TransB DPLL disable (DPLL (null)))
PCH_DPLL_ANALOG_CTL: 0x00008000
PCH_DPLL_A: 0x89086008 (enable, sdvo high speed no, mode LVDS, p2 Div 7, FPA0 P1 4, FPA1 P1 4, refclk SSC, sdvo/hdmi mul 1)
PCH_DPLL_B: 0x04800080 (disable, sdvo high speed no, mode (null), p2 (null), FPA0 P1 8, FPA1 P1 8, refclk default 120Mhz, sdvo/hdmi mul 1)
PCH_FPA0: 0x00010c08 (n = 1, m1 = 12, m2 = 8)
PCH_FPA1: 0x00010c08 (n = 1, m1 = 12, m2 = 8)
PCH_FPB0: 0x00030d07 (n = 3, m1 = 13, m2 = 7)
PCH_FPB1: 0x00030d07 (n = 3, m1 = 13, m2 = 7)
TRANS_HTOTAL_A: 0x080d063f (1600 active, 2062 total)
TRANS_HBLANK_A: 0x080d063f (1600 start, 2062 end)
TRANS_HSYNC_A: 0x06a9067f (1664 start, 1706 end)
TRANS_VTOTAL_A: 0x039b0383 (900 active, 924 total)
TRANS_VBLANK_A: 0x039b0383 (900 start, 924 end)
TRANS_VSYNC_A: 0x03890386 (903 start, 906 end)
TRANSA_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
TRANSA_DATA_N1: 0x00000000 (val 0x0 0)
TRANSA_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
TRANSA_DATA_N2: 0x00000000 (val 0x0 0)
TRANSA_DP_LINK_M1: 0x00000000 (val 0x0 0)
TRANSA_DP_LINK_N1: 0x00000000 (val 0x0 0)
TRANSA_DP_LINK_M2: 0x00000000 (val 0x0 0)
TRANSA_DP_LINK_N2: 0x00000000 (val 0x0 0)
TRANS_HTOTAL_B: 0x00000000 (1 active, 1 total)
TRANS_HBLANK_B: 0x00000000 (1 start, 1 end)
TRANS_HSYNC_B: 0x00000000 (1 start, 1 end)
TRANS_VTOTAL_B: 0x00000000 (1 active, 1 total)
TRANS_VBLANK_B: 0x00000000 (1 start, 1 end)
TRANS_VSYNC_B: 0x00000000 (1 start, 1 end)
TRANSB_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
TRANSB_DATA_N1: 0x00000000 (val 0x0 0)
TRANSB_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
TRANSB_DATA_N2: 0x00000000 (val 0x0 0)
TRANSB_DP_LINK_M1: 0x00000000 (val 0x0 0)
TRANSB_DP_LINK_N1: 0x00000000 (val 0x0 0)
TRANSB_DP_LINK_M2: 0x00000000 (val 0x0 0)
TRANSB_DP_LINK_N2: 0x00000000 (val 0x0 0)
TRANS_HTOTAL_C: 0x00000000 (1 active, 1 total)
TRANS_HBLANK_C: 0x00000000 (1 start, 1 end)
TRANS_HSYNC_C: 0x00000000 (1 start, 1 end)
TRANS_VTOTAL_C: 0x00000000 (1 active, 1 total)
TRANS_VBLANK_C: 0x00000000 (1 start, 1 end)
TRANS_VSYNC_C: 0x00000000 (1 start, 1 end)
TRANSC_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
TRANSC_DATA_N1: 0x00000000 (val 0x0 0)
TRANSC_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
TRANSC_DATA_N2: 0x00000000 (val 0x0 0)
TRANSC_DP_LINK_M1: 0x00000000 (val 0x0 0)
TRANSC_DP_LINK_N1: 0x00000000 (val 0x0 0)
TRANSC_DP_LINK_M2: 0x00000000 (val 0x0 0)
TRANSC_DP_LINK_N2: 0x00000000 (val 0x0 0)
TRANSACONF: 0xc0000000 (enable, active)
TRANSBCONF: 0x00000000 (disable, inactive)
TRANSCCONF: 0x00000000 (disable, inactive)
FDI_TXA_CTL: 0xb00c4000 (enable, train pattern not train, voltage swing 0.4V,pre-emphasis 0dB, port width X2, enhanced framing enable, FDI PLL enable, scrambing enable, master mode disable)
FDI_TXB_CTL: 0x00040000 (disable, train pattern pattern_1, voltage swing 0.4V,pre-emphasis 0dB, port width X1, enhanced framing enable, FDI PLL disable, scrambing enable, master mode disable)
FDI_TXC_CTL: 0x00000000 (disable, train pattern pattern_1, voltage swing 0.4V,pre-emphasis 0dB, port width X1, enhanced framing disable, FDI PLL disable, scrambing enable, master mode disable)
FDI_RXA_CTL: 0x800a2350 (enable, train pattern not train, port width X2, 6bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL enable,FS ecc disable, FE ecc disable, FS err report enable, FE err report enable,scrambing enable, enhanced framing enable, PCDClk)
FDI_RXB_CTL: 0x00000040 (disable, train pattern pattern_1, port width X1, 8bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL disable,FS ecc disable, FE ecc disable, FS err report disable, FE err report disable,scrambing enable, enhanced framing enable, RawClk)
FDI_RXC_CTL: 0x00000040 (disable, train pattern pattern_1, port width X1, 8bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL disable,FS ecc disable, FE ecc disable, FS err report disable, FE err report disable,scrambing enable, enhanced framing enable, RawClk)
FDI_RXA_MISC: 0x00000080 (FDI Delay 128)
FDI_RXB_MISC: 0x00000080 (FDI Delay 128)
FDI_RXC_MISC: 0x00000080 (FDI Delay 128)
FDI_RXA_TUSIZE1: 0x7e000000
FDI_RXA_TUSIZE2: 0x7e000000
FDI_RXB_TUSIZE1: 0x7e000000
FDI_RXB_TUSIZE2: 0x7e000000
FDI_RXC_TUSIZE1: 0x7e000000
FDI_RXC_TUSIZE2: 0x7e000000
FDI_PLL_CTL_1: 0x7e000000
FDI_PLL_CTL_2: 0x7e000000
FDI_RXA_IIR: 0x00000000
FDI_RXA_IMR: 0x000008ff
FDI_RXB_IIR: 0x00000000
FDI_RXB_IMR: 0x000008ff
PCH_ADPA: 0x00f40000 (disabled, transcoder A, -hsync, -vsync)
HDMIB: 0x0000001c (disabled pipe A 8bpc SDVO DVI audio disabled +vsync +hsync detected)
HDMIC: 0x0000001c (disabled pipe A 8bpc SDVO DVI audio disabled +vsync +hsync detected)
HDMID: 0x0000001c (disabled pipe A 8bpc SDVO DVI audio disabled +vsync +hsync detected)
PCH_LVDS: 0x8020033e (enabled, pipe A, 18 bit, 2 channels)
CPU_eDP_A: 0x00000018
PCH_DP_B: 0x00000004
PCH_DP_C: 0x00000004
PCH_DP_D: 0x00000004
TRANS_DP_CTL_A: 0x60000418 (disable port none 6bpc +vsync +hsync)
TRANS_DP_CTL_B: 0x60000018 (disable port none 8bpc +vsync +hsync)
TRANS_DP_CTL_C: 0x60000018 (disable port none 8bpc +vsync +hsync)
BLC_PWM_CPU_CTL2: 0x80000000
BLC_PWM_CPU_CTL: 0x00001312
BLC_PWM_PCH_CTL1: 0x80000000
BLC_PWM_PCH_CTL2: 0x13121312
PCH_PP_STATUS: 0xc0000008 (on, ready, sequencing idle)
PCH_PP_CONTROL: 0xabcd0003 (blacklight disabled, power down on reset, panel on)
PCH_PP_ON_DELAYS: 0x019008fc
PCH_PP_OFF_DELAYS: 0x019008fc
PCH_PP_DIVISOR: 0x00186906
[-- Attachment #4: i915-regs-dc.txt --]
[-- Type: text/plain, Size: 11538 bytes --]
PGETBL_CTL: 0x00000000
GEN6_INSTDONE_1: 0xfffffffe
GEN6_INSTDONE_2: 0xffffffff
CPU_VGACNTRL: 0x80000000 (disabled)
DIGITAL_PORT_HOTPLUG_CNTRL: 0x00000000
RR_HW_CTL: 0x00000000 (low 0, high 0)
FDI_PLL_BIOS_0: 0xffffffff
FDI_PLL_BIOS_1: 0xffffffff
FDI_PLL_BIOS_2: 0xffffffff
DISPLAY_PORT_PLL_BIOS_0: 0xffffffff
DISPLAY_PORT_PLL_BIOS_1: 0xffffffff
DISPLAY_PORT_PLL_BIOS_2: 0xffffffff
FDI_PLL_FREQ_CTL: 0xffffffff
PIPEACONF: 0xc0000050 (enabled, active, 6bpc)
HTOTAL_A: 0x080d063f (1600 active, 2062 total)
HBLANK_A: 0x080d063f (1600 start, 2062 end)
HSYNC_A: 0x06a9067f (1664 start, 1706 end)
VTOTAL_A: 0x039b0383 (900 active, 924 total)
VBLANK_A: 0x039b0383 (900 start, 924 end)
VSYNC_A: 0x03890386 (903 start, 906 end)
VSYNCSHIFT_A: 0x00000000
PIPEASRC: 0x063f0383 (1600, 900)
PIPEA_DATA_M1: 0x7e1f6bc0 (TU 64, val 0x1f6bc0 2059200)
PIPEA_DATA_N1: 0x0041eb00 (val 0x41eb00 4320000)
PIPEA_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
PIPEA_DATA_N2: 0x00000000 (val 0x0 0)
PIPEA_LINK_M1: 0x0001bee0 (val 0x1bee0 114400)
PIPEA_LINK_N1: 0x00041eb0 (val 0x41eb0 270000)
PIPEA_LINK_M2: 0x00000000 (val 0x0 0)
PIPEA_LINK_N2: 0x00000000 (val 0x0 0)
DSPACNTR: 0xd8004400 (enabled)
DSPABASE: 0x00000000
DSPASTRIDE: 0x00001a00 (104)
DSPASURF: 0x05391000
DSPATILEOFF: 0x00000000 (0, 0)
PIPEBCONF: 0x00000000 (disabled, inactive, 8bpc)
HTOTAL_B: 0x00000000 (1 active, 1 total)
HBLANK_B: 0x00000000 (1 start, 1 end)
HSYNC_B: 0x00000000 (1 start, 1 end)
VTOTAL_B: 0x00000000 (1 active, 1 total)
VBLANK_B: 0x00000000 (1 start, 1 end)
VSYNC_B: 0x00000000 (1 start, 1 end)
VSYNCSHIFT_B: 0x00000000
DSPBCNTR: 0x00004000 (disabled)
DSPBBASE: 0x00000000
DSPBSTRIDE: 0x00000000 (0)
DSPBSURF: 0x00000000
DSPBTILEOFF: 0x00000000 (0, 0)
PIPEBSRC: 0x00000000 (1, 1)
PIPEB_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
PIPEB_DATA_N1: 0x00000000 (val 0x0 0)
PIPEB_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
PIPEB_DATA_N2: 0x00000000 (val 0x0 0)
PIPEB_LINK_M1: 0x00000000 (val 0x0 0)
PIPEB_LINK_N1: 0x00000000 (val 0x0 0)
PIPEB_LINK_M2: 0x00000000 (val 0x0 0)
PIPEB_LINK_N2: 0x00000000 (val 0x0 0)
PFA_CTL_1: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1)
PFA_CTL_2: 0x00007e3e (vscale 0.986267)
PFA_CTL_3: 0x00003f1f (vscale initial phase 0.493134)
PFA_CTL_4: 0x00007ce0 (hscale 0.975586)
PFA_WIN_POS: 0x00000000 (0, 0)
PFA_WIN_SIZE: 0x00000000 (0, 0)
PFB_CTL_1: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1)
PFB_CTL_2: 0x00000000 (vscale 0.000000)
PFB_CTL_3: 0x00000000 (vscale initial phase 0.000000)
PFB_CTL_4: 0x00000000 (hscale 0.000000)
PFB_WIN_POS: 0x00000000 (0, 0)
PFB_WIN_SIZE: 0x00000000 (0, 0)
PCH_DREF_CONTROL: 0x00001402 (cpu source disable, ssc_source enable, nonspread_source enable, superspread_source disable, ssc4_mode downspread, ssc1 enable, ssc4 disable)
PCH_RAWCLK_FREQ: 0x0000007d (FDL_TP1 timer 0.5us, FDL_TP2 timer 1.5us, freq 125)
PCH_DPLL_TMR_CFG: 0x0271186a
PCH_SSC4_PARMS: 0x01204860
PCH_SSC4_AUX_PARMS: 0x000029c5
PCH_DPLL_SEL: 0x00000008 (TransA DPLL enable (DPLL A), TransB DPLL disable (DPLL (null)))
PCH_DPLL_ANALOG_CTL: 0x00008000
PCH_DPLL_A: 0x89086008 (enable, sdvo high speed no, mode LVDS, p2 Div 7, FPA0 P1 4, FPA1 P1 4, refclk SSC, sdvo/hdmi mul 1)
PCH_DPLL_B: 0x04800080 (disable, sdvo high speed no, mode (null), p2 (null), FPA0 P1 8, FPA1 P1 8, refclk default 120Mhz, sdvo/hdmi mul 1)
PCH_FPA0: 0x00010c08 (n = 1, m1 = 12, m2 = 8)
PCH_FPA1: 0x00010c08 (n = 1, m1 = 12, m2 = 8)
PCH_FPB0: 0x00030d07 (n = 3, m1 = 13, m2 = 7)
PCH_FPB1: 0x00030d07 (n = 3, m1 = 13, m2 = 7)
TRANS_HTOTAL_A: 0x080d063f (1600 active, 2062 total)
TRANS_HBLANK_A: 0x080d063f (1600 start, 2062 end)
TRANS_HSYNC_A: 0x06a9067f (1664 start, 1706 end)
TRANS_VTOTAL_A: 0x039b0383 (900 active, 924 total)
TRANS_VBLANK_A: 0x039b0383 (900 start, 924 end)
TRANS_VSYNC_A: 0x03890386 (903 start, 906 end)
TRANSA_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
TRANSA_DATA_N1: 0x00000000 (val 0x0 0)
TRANSA_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
TRANSA_DATA_N2: 0x00000000 (val 0x0 0)
TRANSA_DP_LINK_M1: 0x00000000 (val 0x0 0)
TRANSA_DP_LINK_N1: 0x00000000 (val 0x0 0)
TRANSA_DP_LINK_M2: 0x00000000 (val 0x0 0)
TRANSA_DP_LINK_N2: 0x00000000 (val 0x0 0)
TRANS_HTOTAL_B: 0x00000000 (1 active, 1 total)
TRANS_HBLANK_B: 0x00000000 (1 start, 1 end)
TRANS_HSYNC_B: 0x00000000 (1 start, 1 end)
TRANS_VTOTAL_B: 0x00000000 (1 active, 1 total)
TRANS_VBLANK_B: 0x00000000 (1 start, 1 end)
TRANS_VSYNC_B: 0x00000000 (1 start, 1 end)
TRANSB_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
TRANSB_DATA_N1: 0x00000000 (val 0x0 0)
TRANSB_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
TRANSB_DATA_N2: 0x00000000 (val 0x0 0)
TRANSB_DP_LINK_M1: 0x00000000 (val 0x0 0)
TRANSB_DP_LINK_N1: 0x00000000 (val 0x0 0)
TRANSB_DP_LINK_M2: 0x00000000 (val 0x0 0)
TRANSB_DP_LINK_N2: 0x00000000 (val 0x0 0)
TRANS_HTOTAL_C: 0x00000000 (1 active, 1 total)
TRANS_HBLANK_C: 0x00000000 (1 start, 1 end)
TRANS_HSYNC_C: 0x00000000 (1 start, 1 end)
TRANS_VTOTAL_C: 0x00000000 (1 active, 1 total)
TRANS_VBLANK_C: 0x00000000 (1 start, 1 end)
TRANS_VSYNC_C: 0x00000000 (1 start, 1 end)
TRANSC_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
TRANSC_DATA_N1: 0x00000000 (val 0x0 0)
TRANSC_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
TRANSC_DATA_N2: 0x00000000 (val 0x0 0)
TRANSC_DP_LINK_M1: 0x00000000 (val 0x0 0)
TRANSC_DP_LINK_N1: 0x00000000 (val 0x0 0)
TRANSC_DP_LINK_M2: 0x00000000 (val 0x0 0)
TRANSC_DP_LINK_N2: 0x00000000 (val 0x0 0)
TRANSACONF: 0xc0000000 (enable, active)
TRANSBCONF: 0x00000000 (disable, inactive)
TRANSCCONF: 0x00000000 (disable, inactive)
FDI_TXA_CTL: 0xb00c4000 (enable, train pattern not train, voltage swing 0.4V,pre-emphasis 0dB, port width X2, enhanced framing enable, FDI PLL enable, scrambing enable, master mode disable)
FDI_TXB_CTL: 0x00040000 (disable, train pattern pattern_1, voltage swing 0.4V,pre-emphasis 0dB, port width X1, enhanced framing enable, FDI PLL disable, scrambing enable, master mode disable)
FDI_TXC_CTL: 0x00000000 (disable, train pattern pattern_1, voltage swing 0.4V,pre-emphasis 0dB, port width X1, enhanced framing disable, FDI PLL disable, scrambing enable, master mode disable)
FDI_RXA_CTL: 0x800a2350 (enable, train pattern not train, port width X2, 6bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL enable,FS ecc disable, FE ecc disable, FS err report enable, FE err report enable,scrambing enable, enhanced framing enable, PCDClk)
FDI_RXB_CTL: 0x00000040 (disable, train pattern pattern_1, port width X1, 8bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL disable,FS ecc disable, FE ecc disable, FS err report disable, FE err report disable,scrambing enable, enhanced framing enable, RawClk)
FDI_RXC_CTL: 0x00000040 (disable, train pattern pattern_1, port width X1, 8bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL disable,FS ecc disable, FE ecc disable, FS err report disable, FE err report disable,scrambing enable, enhanced framing enable, RawClk)
FDI_RXA_MISC: 0x00000080 (FDI Delay 128)
FDI_RXB_MISC: 0x00000080 (FDI Delay 128)
FDI_RXC_MISC: 0x00000080 (FDI Delay 128)
FDI_RXA_TUSIZE1: 0x7e000000
FDI_RXA_TUSIZE2: 0x7e000000
FDI_RXB_TUSIZE1: 0x7e000000
FDI_RXB_TUSIZE2: 0x7e000000
FDI_RXC_TUSIZE1: 0x7e000000
FDI_RXC_TUSIZE2: 0x7e000000
FDI_PLL_CTL_1: 0x7e000000
FDI_PLL_CTL_2: 0x7e000000
FDI_RXA_IIR: 0x00000000
FDI_RXA_IMR: 0x000008ff
FDI_RXB_IIR: 0x00000000
FDI_RXB_IMR: 0x000008ff
PCH_ADPA: 0x00f40000 (disabled, transcoder A, -hsync, -vsync)
HDMIB: 0x0000001c (disabled pipe A 8bpc SDVO DVI audio disabled +vsync +hsync detected)
HDMIC: 0x0000001c (disabled pipe A 8bpc SDVO DVI audio disabled +vsync +hsync detected)
HDMID: 0x0000001c (disabled pipe A 8bpc SDVO DVI audio disabled +vsync +hsync detected)
PCH_LVDS: 0x8020033e (enabled, pipe A, 18 bit, 2 channels)
CPU_eDP_A: 0x00000018
PCH_DP_B: 0x00000004
PCH_DP_C: 0x00000004
PCH_DP_D: 0x00000004
TRANS_DP_CTL_A: 0x60000418 (disable port none 6bpc +vsync +hsync)
TRANS_DP_CTL_B: 0x60000018 (disable port none 8bpc +vsync +hsync)
TRANS_DP_CTL_C: 0x60000018 (disable port none 8bpc +vsync +hsync)
BLC_PWM_CPU_CTL2: 0x80000000
BLC_PWM_CPU_CTL: 0x00000218
BLC_PWM_PCH_CTL1: 0x80000000
BLC_PWM_PCH_CTL2: 0x13121312
PCH_PP_STATUS: 0xc0000008 (on, ready, sequencing idle)
PCH_PP_CONTROL: 0xabcd0003 (blacklight disabled, power down on reset, panel on)
PCH_PP_ON_DELAYS: 0x019008fc
PCH_PP_OFF_DELAYS: 0x019008fc
PCH_PP_DIVISOR: 0x00186906
[-- Attachment #5: Type: text/plain, Size: 159 bytes --]
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^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: i915 SNB: hotplug events when charging causing poor interactivity
2012-02-21 13:37 ` Daniel J Blueman
@ 2012-02-21 20:02 ` Daniel Vetter
2012-02-21 20:30 ` Andrew Lutomirski
0 siblings, 1 reply; 5+ messages in thread
From: Daniel Vetter @ 2012-02-21 20:02 UTC (permalink / raw)
To: Daniel J Blueman; +Cc: intel-gfx
On Tue, Feb 21, 2012 at 01:37:37PM +0000, Daniel J Blueman wrote:
> On 16 February 2012 13:07, Daniel Vetter <daniel@ffwll.ch> wrote:
> > On Thu, Feb 16, 2012 at 11:44:46AM +0000, Daniel J Blueman wrote:
> >> When charging Dell E5420 laptops, I see the Sandy Bridge South Display
> >> Engine port C hotplug interrupt fire consistently at around 20Hz. Each
> []
> >> Notably, when only using battery or only using AC, the port C
> >> interrupts don't fire. It feels like the platform is using South
> >> Display Port C for GPIO/I2C; setting the port C pulse duration from
> >> 2ms to 100ms doesn't change the behaviour. I'll dump off the GPIO
> >> settings, but what else is good to debug this?
> >
> > Yep, dumping the register state (intel_reg_dumper from intel-gpu-tools is
> > handy for that) in the different situations sounds useful.
> []
> > If this is indeed the bios we need to quirk this away. But I think we
> > should check first whether we don't butcher something else accidently.
>
> When charging the battery, I see the SDE_PORTB_HOTPLUG, PORTC, PORTD
> and SDE_AUX_MASK bits set (sometimes at different times) at ~20Hz
> until the battery is charged, which is disconcerting.
>
> Hotplugging a HDMI cable, SDE_PORTB_HOTPLUG and SDE_AUX_MASK bits are
> set once, so we can't mask these on this platform.
>
> Attached are the reg dumps. We see the backlight register
> (BLC_PWM_CPU_CTL) and the A surface register (DSPASURF) vary across
> multiple reads as expected.
>
> Any ideas?
Nope, as in absolutely no idea. The only idea I have is that the expects
us to do something with either acpi or opregion that we currently don't,
but that's just handwaving.
So I think you're left with filing a bug report with all the things you've
gathered and hoping that we stumble over the missing piece of
documentation :(
-Daniel
--
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: i915 SNB: hotplug events when charging causing poor interactivity
2012-02-21 20:02 ` Daniel Vetter
@ 2012-02-21 20:30 ` Andrew Lutomirski
0 siblings, 0 replies; 5+ messages in thread
From: Andrew Lutomirski @ 2012-02-21 20:30 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx
On Tue, Feb 21, 2012 at 12:02 PM, Daniel Vetter <daniel@ffwll.ch> wrote:
> On Tue, Feb 21, 2012 at 01:37:37PM +0000, Daniel J Blueman wrote:
>> On 16 February 2012 13:07, Daniel Vetter <daniel@ffwll.ch> wrote:
>> > On Thu, Feb 16, 2012 at 11:44:46AM +0000, Daniel J Blueman wrote:
>> >> When charging Dell E5420 laptops, I see the Sandy Bridge South Display
>> >> Engine port C hotplug interrupt fire consistently at around 20Hz. Each
>> []
>> >> Notably, when only using battery or only using AC, the port C
>> >> interrupts don't fire. It feels like the platform is using South
>> >> Display Port C for GPIO/I2C; setting the port C pulse duration from
>> >> 2ms to 100ms doesn't change the behaviour. I'll dump off the GPIO
>> >> settings, but what else is good to debug this?
>> >
>> > Yep, dumping the register state (intel_reg_dumper from intel-gpu-tools is
>> > handy for that) in the different situations sounds useful.
>> []
>> > If this is indeed the bios we need to quirk this away. But I think we
>> > should check first whether we don't butcher something else accidently.
>>
>> When charging the battery, I see the SDE_PORTB_HOTPLUG, PORTC, PORTD
>> and SDE_AUX_MASK bits set (sometimes at different times) at ~20Hz
>> until the battery is charged, which is disconcerting.
>>
>> Hotplugging a HDMI cable, SDE_PORTB_HOTPLUG and SDE_AUX_MASK bits are
>> set once, so we can't mask these on this platform.
>>
>> Attached are the reg dumps. We see the backlight register
>> (BLC_PWM_CPU_CTL) and the A surface register (DSPASURF) vary across
>> multiple reads as expected.
>>
>> Any ideas?
>
> Nope, as in absolutely no idea. The only idea I have is that the expects
> us to do something with either acpi or opregion that we currently don't,
> but that's just handwaving.
>
> So I think you're left with filing a bug report with all the things you've
> gathered and hoping that we stumble over the missing piece of
> documentation :(
There used to be a bug on GM45 that would cause digital outputs that
weren't connected to occasionally generate bogus hotplug interrupts.
I wonder if there's a pin that's floating that picks up noise or stray
charge depending on what the battery charger is doing. IIRC there's
something in vbios that the driver could use to detect and disable
unwired ports.
Do you actually have a port C?
--Andy
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2012-02-21 20:30 UTC | newest]
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2012-02-16 11:44 ` i915 SNB: hotplug events when charging causing poor interactivity Daniel J Blueman
2012-02-16 13:07 ` Daniel Vetter
2012-02-21 13:37 ` Daniel J Blueman
2012-02-21 20:02 ` Daniel Vetter
2012-02-21 20:30 ` Andrew Lutomirski
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