Intel-GFX Archive on lore.kernel.org
 help / color / mirror / Atom feed
From: Daniel Vetter <daniel@ffwll.ch>
To: Eugeni Dodonov <eugeni.dodonov@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 03/29] drm/i915: add Haswell DIP controls registers
Date: Tue, 17 Apr 2012 12:12:38 +0200	[thread overview]
Message-ID: <20120417101238.GE4104@phenom.ffwll.local> (raw)
In-Reply-To: <1334347745-11743-4-git-send-email-eugeni.dodonov@intel.com>

On Fri, Apr 13, 2012 at 05:08:39PM -0300, Eugeni Dodonov wrote:
> Haswell has different DIP control registers and offsets.
> 
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>

I've read a bit through Bspec wrt dip writing and it looks like hsw is
rather differen from previous chips:
- with have a data reg for every type of dip
- the bits in the ctl reg moved around completely

... so I guess this patch and the follow-on one are pretty bogus. One
thing I've noticed is that intel_infoframe_index and intel_infoframe_flags
have way too generic names, they're only useful to frob the dip ctl reg on
pre-hsw afaics. I think we should rename them to i9xx_infoframe_ctl_inde
and _flags or something similar.

-Daniel
> ---
>  drivers/gpu/drm/i915/i915_reg.h |   16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 05d98f2..8cc53fb 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3488,6 +3488,22 @@
>  #define VLV_TVIDEO_DIP_GCP(pipe) \
>  	_PIPE(pipe, VLV_VIDEO_DIP_GDCP_PAYLOAD_A, VLV_VIDEO_DIP_GDCP_PAYLOAD_B)
>  
> +/* Haswell DIP controls */
> +#define HSW_VIDEO_DIP_CTL_A			0x60200
> +#define HSW_VIDEO_DIP_AVI_DATA_A	0x60220
> +#define HSW_VIDEO_DIP_GCP_A			0x60210
> +
> +#define HSW_VIDEO_DIP_CTL_B			0x61200
> +#define HSW_VIDEO_DIP_AVI_DATA_B	0x61220
> +#define HSW_VIDEO_DIP_GCP_B			0x61210
> +
> +#define HSW_TVIDEO_DIP_CTL(pipe) \
> +	 _PIPE(pipe, HSW_VIDEO_DIP_CTL_A, HSW_VIDEO_DIP_CTL_B)
> +#define HSW_TVIDEO_DIP_AVI_DATA(pipe) \
> +	 _PIPE(pipe, HSW_VIDEO_DIP_AVI_DATA_A, HSW_VIDEO_DIP_AVI_DATA_B)
> +#define HSW_TVIDEO_DIP_GCP(pipe) \
> +	_PIPE(pipe, HSW_VIDEO_DIP_GCP_A, HSW_VIDEO_DIP_GCP_B)
> +
>  #define _TRANS_HTOTAL_B          0xe1000
>  #define _TRANS_HBLANK_B          0xe1004
>  #define _TRANS_HSYNC_B           0xe1008
> -- 
> 1.7.10
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

  reply	other threads:[~2012-04-17 10:11 UTC|newest]

Thread overview: 63+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-04-13 20:08 [PATCH 00/29] Haswell round 3 Eugeni Dodonov
2012-04-13 20:08 ` [PATCH 01/29] drm/i915: add definition of LPT FDI port width registers Eugeni Dodonov
2012-04-13 20:08 ` [PATCH 02/29] drm/i915: add WRPLL divider programming bits Eugeni Dodonov
2012-04-13 20:08 ` [PATCH 03/29] drm/i915: add Haswell DIP controls registers Eugeni Dodonov
2012-04-17 10:12   ` Daniel Vetter [this message]
2012-04-17 12:02     ` Eugeni Dodonov
2012-04-13 20:08 ` [PATCH 04/29] drm/i915: support infoframes on Haswell Eugeni Dodonov
2012-04-13 20:08 ` [PATCH 05/29] drm/i915: prevent NULL pointer exception when using gmbus Eugeni Dodonov
2012-04-13 20:18   ` Chris Wilson
2012-04-14  0:26     ` Eugeni Dodonov
2012-04-14 15:58       ` Daniel Vetter
2012-04-14 16:01         ` Chris Wilson
2012-04-13 20:08 ` [PATCH 06/29] drm/i915: add support for SBI ops Eugeni Dodonov
2012-04-13 20:26   ` Chris Wilson
2012-04-14  0:28     ` Eugeni Dodonov
2012-04-13 20:08 ` [PATCH 07/29] drm/i915: calculate same watermarks on Haswell as on Ivy Bridge Eugeni Dodonov
2012-04-13 20:27   ` Chris Wilson
2012-04-13 20:08 ` [PATCH 08/29] drm/i915: share forcewaking code between IVB and HSW Eugeni Dodonov
2012-04-13 20:08 ` [PATCH 09/29] drm/i915: haswell has 3 pipes as well Eugeni Dodonov
2012-04-13 20:08 ` [PATCH 10/29] drm/i915: reuse Ivybridge interrupts code for Haswell Eugeni Dodonov
2012-04-15 23:29   ` Daniel Vetter
2012-04-13 20:08 ` [PATCH 11/29] drm/i915: share pipe count handling with Ivybridge Eugeni Dodonov
2012-04-17 10:19   ` Daniel Vetter
2012-04-17 10:36     ` Chris Wilson
2012-04-17 11:26       ` Daniel Vetter
2012-04-17 11:38         ` Chris Wilson
2012-04-13 20:08 ` [PATCH 12/29] drm/i915: share IVB cursor routine with Haswell Eugeni Dodonov
2012-04-13 20:08 ` [PATCH 13/29] drm/i915: show unknown sdvox registers on hdmi init Eugeni Dodonov
2012-04-17 10:20   ` Daniel Vetter
2012-04-13 20:08 ` [PATCH 14/29] drm/i915: do not use fdi_normal_train on haswell Eugeni Dodonov
2012-04-13 20:08 ` [PATCH 15/29] drm/i915: do not enable PCH PLL on pre-haswell Eugeni Dodonov
2012-04-13 20:55   ` Chris Wilson
2012-04-14  0:31     ` Eugeni Dodonov
2012-04-15 23:52   ` Daniel Vetter
2012-04-13 20:08 ` [PATCH 16/29] drm/i915: detect PCH encoders on Haswell Eugeni Dodonov
2012-04-17 10:21   ` Daniel Vetter
2012-04-13 20:08 ` [PATCH 17/29] drm/i915: enable power wells on haswell init Eugeni Dodonov
2012-04-13 21:03   ` Chris Wilson
2012-04-14  1:26     ` Eugeni Dodonov
2012-04-13 20:08 ` [PATCH 18/29] drm/i915: disable rc6 on haswell for now Eugeni Dodonov
2012-04-13 20:08 ` [PATCH 19/29] drm/i915: program WM_LINETIME on Haswell Eugeni Dodonov
2012-04-13 20:08 ` [PATCH 20/29] drm/i915: do not use old code paths " Eugeni Dodonov
2012-04-13 20:08 ` [PATCH 21/29] drm/i915: initialize DDI buffer translations Eugeni Dodonov
2012-04-13 21:05   ` Chris Wilson
2012-04-13 21:11   ` Chris Wilson
2012-04-14  1:32     ` Eugeni Dodonov
2012-04-13 20:08 ` [PATCH 22/29] drm/i915: perform Haswell DDI link training in FDI mode Eugeni Dodonov
2012-04-13 20:08 ` [PATCH 23/29] drm/i915: disable pipe DDI function when disabling pipe Eugeni Dodonov
2012-04-13 20:09 ` [PATCH 24/29] drm/i915: program iCLKIP on Lynx Point Eugeni Dodonov
2012-04-15 23:49   ` Daniel Vetter
2012-04-16  0:44     ` Eugeni Dodonov
2012-04-16  8:26       ` Chris Wilson
2012-04-16  8:56         ` Daniel Vetter
2012-04-13 20:09 ` [PATCH 25/29] drm/i915: detect digital outputs on Haswell Eugeni Dodonov
2012-04-13 21:17   ` Chris Wilson
2012-04-14  0:37     ` Eugeni Dodonov
2012-04-15 23:36       ` Daniel Vetter
2012-04-13 20:09 ` [PATCH 26/29] drm/i915: add support for DDI-controlled digital outputs Eugeni Dodonov
2012-04-13 20:09 ` [PATCH 27/29] drm/i915: add WR PLL programming table Eugeni Dodonov
2012-04-13 20:09 ` [PATCH 28/29] drm/i915: prepare HDMI link for Haswell Eugeni Dodonov
2012-04-13 20:09 ` [PATCH 29/29] drm/i915: hook Haswell devices in place Eugeni Dodonov
2012-04-17 10:49 ` [PATCH 00/29] Haswell round 3 Daniel Vetter
2012-04-17 11:58   ` Eugeni Dodonov

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20120417101238.GE4104@phenom.ffwll.local \
    --to=daniel@ffwll.ch \
    --cc=eugeni.dodonov@intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox