* [PATCH 1/3] drm/i915: replace intel_infoframe_freq with VIDEO_DIP_FREQ_VSYNC @ 2012-05-08 12:41 Daniel Vetter 2012-05-08 12:41 ` [PATCH 2/3] drm/i915: s/i9xx_/gm45_ for the gm45 write_infoframe function Daniel Vetter 2012-05-08 12:41 ` [PATCH 3/3] drm/i915: s/intel_infoframe/gm45_infoframe Daniel Vetter 0 siblings, 2 replies; 7+ messages in thread From: Daniel Vetter @ 2012-05-08 12:41 UTC (permalink / raw) To: Intel Graphics Development; +Cc: Daniel Vetter Simplifies things because for all the infoframes we care about, we always send them on each vblank. Also, this gets rid of one of the hw specific functions mislabelled with the intel_ prefix - hsw will completely change how this works! Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> --- drivers/gpu/drm/i915/intel_hdmi.c | 25 ++++--------------------- 1 file changed, 4 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 9902904..4c822e1 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -113,23 +113,6 @@ static u32 intel_infoframe_enable(struct dip_infoframe *frame) return flags; } -static u32 intel_infoframe_frequency(struct dip_infoframe *frame) -{ - u32 flags = 0; - - switch (frame->type) { - case DIP_TYPE_AVI: - case DIP_TYPE_SPD: - flags |= VIDEO_DIP_FREQ_VSYNC; - break; - default: - DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); - break; - } - - return flags; -} - static void i9xx_write_infoframe(struct drm_encoder *encoder, struct dip_infoframe *frame) { @@ -165,7 +148,7 @@ static void i9xx_write_infoframe(struct drm_encoder *encoder, val |= intel_infoframe_enable(frame); val &= ~VIDEO_DIP_FREQ_MASK; - val |= intel_infoframe_frequency(frame); + val |= VIDEO_DIP_FREQ_VSYNC; I915_WRITE(VIDEO_DIP_CTL, val); } @@ -215,7 +198,7 @@ static void ibx_write_infoframe(struct drm_encoder *encoder, val |= intel_infoframe_enable(frame); val &= ~VIDEO_DIP_FREQ_MASK; - val |= intel_infoframe_frequency(frame); + val |= VIDEO_DIP_FREQ_VSYNC; I915_WRITE(reg, val); } @@ -255,7 +238,7 @@ static void cpt_write_infoframe(struct drm_encoder *encoder, val |= intel_infoframe_enable(frame); val &= ~VIDEO_DIP_FREQ_MASK; - val |= intel_infoframe_frequency(frame); + val |= VIDEO_DIP_FREQ_VSYNC; I915_WRITE(reg, val); } @@ -289,7 +272,7 @@ static void vlv_write_infoframe(struct drm_encoder *encoder, val |= intel_infoframe_enable(frame); val &= ~VIDEO_DIP_FREQ_MASK; - val |= intel_infoframe_frequency(frame); + val |= VIDEO_DIP_FREQ_VSYNC; I915_WRITE(reg, val); } -- 1.7.10 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/3] drm/i915: s/i9xx_/gm45_ for the gm45 write_infoframe function 2012-05-08 12:41 [PATCH 1/3] drm/i915: replace intel_infoframe_freq with VIDEO_DIP_FREQ_VSYNC Daniel Vetter @ 2012-05-08 12:41 ` Daniel Vetter 2012-05-08 13:15 ` Daniel Vetter 2012-05-08 13:19 ` [PATCH] " Daniel Vetter 2012-05-08 12:41 ` [PATCH 3/3] drm/i915: s/intel_infoframe/gm45_infoframe Daniel Vetter 1 sibling, 2 replies; 7+ messages in thread From: Daniel Vetter @ 2012-05-08 12:41 UTC (permalink / raw) To: Intel Graphics Development; +Cc: Daniel Vetter Generally we call stuff with i9xx_ when it's valid for gen3+. But gen3 and early gen4 only support hdmi with sdvo cards, and writing infoframes works completely different there. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> --- drivers/gpu/drm/i915/intel_hdmi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 4c822e1..65e033a 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -113,7 +113,7 @@ static u32 intel_infoframe_enable(struct dip_infoframe *frame) return flags; } -static void i9xx_write_infoframe(struct drm_encoder *encoder, +static void gm45_write_infoframe(struct drm_encoder *encoder, struct dip_infoframe *frame) { uint32_t *data = (uint32_t *)frame; @@ -654,7 +654,7 @@ void intel_hdmi_init(struct drm_device *dev, int sdvox_reg) intel_hdmi->sdvox_reg = sdvox_reg; if (!HAS_PCH_SPLIT(dev)) { - intel_hdmi->write_infoframe = i9xx_write_infoframe; + intel_hdmi->write_infoframe = gm45_write_infoframe; I915_WRITE(VIDEO_DIP_CTL, 0); } else if (IS_VALLEYVIEW(dev)) { intel_hdmi->write_infoframe = vlv_write_infoframe; -- 1.7.10 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 2/3] drm/i915: s/i9xx_/gm45_ for the gm45 write_infoframe function 2012-05-08 12:41 ` [PATCH 2/3] drm/i915: s/i9xx_/gm45_ for the gm45 write_infoframe function Daniel Vetter @ 2012-05-08 13:15 ` Daniel Vetter 2012-05-08 13:19 ` [PATCH] " Daniel Vetter 1 sibling, 0 replies; 7+ messages in thread From: Daniel Vetter @ 2012-05-08 13:15 UTC (permalink / raw) To: Intel Graphics Development; +Cc: Daniel Vetter On Tue, May 08, 2012 at 02:41:01PM +0200, Daniel Vetter wrote: > Generally we call stuff with i9xx_ when it's valid for gen3+. But > gen3 and early gen4 only support hdmi with sdvo cards, and writing > infoframes works completely different there. > > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Bikeshed fail, the usual prefix for gen4.5 is actually g4x ... I'll redo the patches. -Daniel > --- > drivers/gpu/drm/i915/intel_hdmi.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c > index 4c822e1..65e033a 100644 > --- a/drivers/gpu/drm/i915/intel_hdmi.c > +++ b/drivers/gpu/drm/i915/intel_hdmi.c > @@ -113,7 +113,7 @@ static u32 intel_infoframe_enable(struct dip_infoframe *frame) > return flags; > } > > -static void i9xx_write_infoframe(struct drm_encoder *encoder, > +static void gm45_write_infoframe(struct drm_encoder *encoder, > struct dip_infoframe *frame) > { > uint32_t *data = (uint32_t *)frame; > @@ -654,7 +654,7 @@ void intel_hdmi_init(struct drm_device *dev, int sdvox_reg) > intel_hdmi->sdvox_reg = sdvox_reg; > > if (!HAS_PCH_SPLIT(dev)) { > - intel_hdmi->write_infoframe = i9xx_write_infoframe; > + intel_hdmi->write_infoframe = gm45_write_infoframe; > I915_WRITE(VIDEO_DIP_CTL, 0); > } else if (IS_VALLEYVIEW(dev)) { > intel_hdmi->write_infoframe = vlv_write_infoframe; > -- > 1.7.10 > -- Daniel Vetter Mail: daniel@ffwll.ch Mobile: +41 (0)79 365 57 48 ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH] drm/i915: s/i9xx_/gm45_ for the gm45 write_infoframe function 2012-05-08 12:41 ` [PATCH 2/3] drm/i915: s/i9xx_/gm45_ for the gm45 write_infoframe function Daniel Vetter 2012-05-08 13:15 ` Daniel Vetter @ 2012-05-08 13:19 ` Daniel Vetter 1 sibling, 0 replies; 7+ messages in thread From: Daniel Vetter @ 2012-05-08 13:19 UTC (permalink / raw) To: Intel Graphics Development; +Cc: Daniel Vetter Generally we call stuff with i9xx_ when it's valid for gen3+. But gen3 and early gen4 only support hdmi with sdvo cards, and writing infoframes works completely different there. v2: Use g4x instead of gm45 - it applies to the desktop variant, too. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> --- drivers/gpu/drm/i915/intel_hdmi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 4c822e1..1d428fe 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -113,7 +113,7 @@ static u32 intel_infoframe_enable(struct dip_infoframe *frame) return flags; } -static void i9xx_write_infoframe(struct drm_encoder *encoder, +static void g4x_write_infoframe(struct drm_encoder *encoder, struct dip_infoframe *frame) { uint32_t *data = (uint32_t *)frame; @@ -654,7 +654,7 @@ void intel_hdmi_init(struct drm_device *dev, int sdvox_reg) intel_hdmi->sdvox_reg = sdvox_reg; if (!HAS_PCH_SPLIT(dev)) { - intel_hdmi->write_infoframe = i9xx_write_infoframe; + intel_hdmi->write_infoframe = g4x_write_infoframe; I915_WRITE(VIDEO_DIP_CTL, 0); } else if (IS_VALLEYVIEW(dev)) { intel_hdmi->write_infoframe = vlv_write_infoframe; -- 1.7.10 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 3/3] drm/i915: s/intel_infoframe/gm45_infoframe 2012-05-08 12:41 [PATCH 1/3] drm/i915: replace intel_infoframe_freq with VIDEO_DIP_FREQ_VSYNC Daniel Vetter 2012-05-08 12:41 ` [PATCH 2/3] drm/i915: s/i9xx_/gm45_ for the gm45 write_infoframe function Daniel Vetter @ 2012-05-08 12:41 ` Daniel Vetter 2012-05-08 13:18 ` [PATCH] " Daniel Vetter 1 sibling, 1 reply; 7+ messages in thread From: Daniel Vetter @ 2012-05-08 12:41 UTC (permalink / raw) To: Intel Graphics Development; +Cc: Daniel Vetter These two functions are actually hw-specific and only valid for gm45 thru gen7. HSW completely changes how this works, so label them accordingly. Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch> --- drivers/gpu/drm/i915/intel_hdmi.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 65e033a..c27a624 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -75,7 +75,7 @@ void intel_dip_infoframe_csum(struct dip_infoframe *frame) frame->checksum = 0x100 - sum; } -static u32 intel_infoframe_index(struct dip_infoframe *frame) +static u32 gm45_infoframe_index(struct dip_infoframe *frame) { u32 flags = 0; @@ -94,7 +94,7 @@ static u32 intel_infoframe_index(struct dip_infoframe *frame) return flags; } -static u32 intel_infoframe_enable(struct dip_infoframe *frame) +static u32 gm45_infoframe_enable(struct dip_infoframe *frame) { u32 flags = 0; @@ -134,9 +134,9 @@ static void gm45_write_infoframe(struct drm_encoder *encoder, return; val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ - val |= intel_infoframe_index(frame); + val |= gm45_infoframe_index(frame); - val &= ~intel_infoframe_enable(frame); + val &= ~gm45_infoframe_enable(frame); val |= VIDEO_DIP_ENABLE; I915_WRITE(VIDEO_DIP_CTL, val); @@ -146,7 +146,7 @@ static void gm45_write_infoframe(struct drm_encoder *encoder, data++; } - val |= intel_infoframe_enable(frame); + val |= gm45_infoframe_enable(frame); val &= ~VIDEO_DIP_FREQ_MASK; val |= VIDEO_DIP_FREQ_VSYNC; @@ -184,9 +184,9 @@ static void ibx_write_infoframe(struct drm_encoder *encoder, intel_wait_for_vblank(dev, intel_crtc->pipe); val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ - val |= intel_infoframe_index(frame); + val |= gm45_infoframe_index(frame); - val &= ~intel_infoframe_enable(frame); + val &= ~gm45_infoframe_enable(frame); val |= VIDEO_DIP_ENABLE; I915_WRITE(reg, val); @@ -196,7 +196,7 @@ static void ibx_write_infoframe(struct drm_encoder *encoder, data++; } - val |= intel_infoframe_enable(frame); + val |= gm45_infoframe_enable(frame); val &= ~VIDEO_DIP_FREQ_MASK; val |= VIDEO_DIP_FREQ_VSYNC; @@ -218,14 +218,14 @@ static void cpt_write_infoframe(struct drm_encoder *encoder, intel_wait_for_vblank(dev, intel_crtc->pipe); val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ - val |= intel_infoframe_index(frame); + val |= gm45_infoframe_index(frame); /* The DIP control register spec says that we need to update the AVI * infoframe without clearing its enable bit */ if (frame->type == DIP_TYPE_AVI) val |= VIDEO_DIP_ENABLE_AVI; else - val &= ~intel_infoframe_enable(frame); + val &= ~gm45_infoframe_enable(frame); val |= VIDEO_DIP_ENABLE; @@ -236,7 +236,7 @@ static void cpt_write_infoframe(struct drm_encoder *encoder, data++; } - val |= intel_infoframe_enable(frame); + val |= gm45_infoframe_enable(frame); val &= ~VIDEO_DIP_FREQ_MASK; val |= VIDEO_DIP_FREQ_VSYNC; @@ -258,9 +258,9 @@ static void vlv_write_infoframe(struct drm_encoder *encoder, intel_wait_for_vblank(dev, intel_crtc->pipe); val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ - val |= intel_infoframe_index(frame); + val |= gm45_infoframe_index(frame); - val &= ~intel_infoframe_enable(frame); + val &= ~gm45_infoframe_enable(frame); val |= VIDEO_DIP_ENABLE; I915_WRITE(reg, val); @@ -270,7 +270,7 @@ static void vlv_write_infoframe(struct drm_encoder *encoder, data++; } - val |= intel_infoframe_enable(frame); + val |= gm45_infoframe_enable(frame); val &= ~VIDEO_DIP_FREQ_MASK; val |= VIDEO_DIP_FREQ_VSYNC; -- 1.7.10 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH] drm/i915: s/intel_infoframe/gm45_infoframe 2012-05-08 12:41 ` [PATCH 3/3] drm/i915: s/intel_infoframe/gm45_infoframe Daniel Vetter @ 2012-05-08 13:18 ` Daniel Vetter 2012-05-08 13:38 ` Daniel Vetter 0 siblings, 1 reply; 7+ messages in thread From: Daniel Vetter @ 2012-05-08 13:18 UTC (permalink / raw) To: Intel Graphics Development; +Cc: Daniel Vetter These two functions are actually hw-specific and only valid for gm45 thru gen7. HSW completely changes how this works, so label them accordingly. v2: s/gm45/g4x/ like for the previous patch. Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch> --- drivers/gpu/drm/i915/intel_hdmi.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 1d428fe..a71abb7 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -75,7 +75,7 @@ void intel_dip_infoframe_csum(struct dip_infoframe *frame) frame->checksum = 0x100 - sum; } -static u32 intel_infoframe_index(struct dip_infoframe *frame) +static u32 g4x_infoframe_index(struct dip_infoframe *frame) { u32 flags = 0; @@ -94,7 +94,7 @@ static u32 intel_infoframe_index(struct dip_infoframe *frame) return flags; } -static u32 intel_infoframe_enable(struct dip_infoframe *frame) +static u32 g4x_infoframe_enable(struct dip_infoframe *frame) { u32 flags = 0; @@ -134,9 +134,9 @@ static void g4x_write_infoframe(struct drm_encoder *encoder, return; val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ - val |= intel_infoframe_index(frame); + val |= g4x_infoframe_index(frame); - val &= ~intel_infoframe_enable(frame); + val &= ~g4x_infoframe_enable(frame); val |= VIDEO_DIP_ENABLE; I915_WRITE(VIDEO_DIP_CTL, val); @@ -146,7 +146,7 @@ static void g4x_write_infoframe(struct drm_encoder *encoder, data++; } - val |= intel_infoframe_enable(frame); + val |= g4x_infoframe_enable(frame); val &= ~VIDEO_DIP_FREQ_MASK; val |= VIDEO_DIP_FREQ_VSYNC; @@ -184,9 +184,9 @@ static void ibx_write_infoframe(struct drm_encoder *encoder, intel_wait_for_vblank(dev, intel_crtc->pipe); val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ - val |= intel_infoframe_index(frame); + val |= g4x_infoframe_index(frame); - val &= ~intel_infoframe_enable(frame); + val &= ~g4x_infoframe_enable(frame); val |= VIDEO_DIP_ENABLE; I915_WRITE(reg, val); @@ -196,7 +196,7 @@ static void ibx_write_infoframe(struct drm_encoder *encoder, data++; } - val |= intel_infoframe_enable(frame); + val |= g4x_infoframe_enable(frame); val &= ~VIDEO_DIP_FREQ_MASK; val |= VIDEO_DIP_FREQ_VSYNC; @@ -218,14 +218,14 @@ static void cpt_write_infoframe(struct drm_encoder *encoder, intel_wait_for_vblank(dev, intel_crtc->pipe); val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ - val |= intel_infoframe_index(frame); + val |= g4x_infoframe_index(frame); /* The DIP control register spec says that we need to update the AVI * infoframe without clearing its enable bit */ if (frame->type == DIP_TYPE_AVI) val |= VIDEO_DIP_ENABLE_AVI; else - val &= ~intel_infoframe_enable(frame); + val &= ~g4x_infoframe_enable(frame); val |= VIDEO_DIP_ENABLE; @@ -236,7 +236,7 @@ static void cpt_write_infoframe(struct drm_encoder *encoder, data++; } - val |= intel_infoframe_enable(frame); + val |= g4x_infoframe_enable(frame); val &= ~VIDEO_DIP_FREQ_MASK; val |= VIDEO_DIP_FREQ_VSYNC; @@ -258,9 +258,9 @@ static void vlv_write_infoframe(struct drm_encoder *encoder, intel_wait_for_vblank(dev, intel_crtc->pipe); val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ - val |= intel_infoframe_index(frame); + val |= g4x_infoframe_index(frame); - val &= ~intel_infoframe_enable(frame); + val &= ~g4x_infoframe_enable(frame); val |= VIDEO_DIP_ENABLE; I915_WRITE(reg, val); @@ -270,7 +270,7 @@ static void vlv_write_infoframe(struct drm_encoder *encoder, data++; } - val |= intel_infoframe_enable(frame); + val |= g4x_infoframe_enable(frame); val &= ~VIDEO_DIP_FREQ_MASK; val |= VIDEO_DIP_FREQ_VSYNC; -- 1.7.10 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH] drm/i915: s/intel_infoframe/gm45_infoframe 2012-05-08 13:18 ` [PATCH] " Daniel Vetter @ 2012-05-08 13:38 ` Daniel Vetter 0 siblings, 0 replies; 7+ messages in thread From: Daniel Vetter @ 2012-05-08 13:38 UTC (permalink / raw) To: Intel Graphics Development; +Cc: Daniel Vetter On Tue, May 08, 2012 at 03:18:32PM +0200, Daniel Vetter wrote: > These two functions are actually hw-specific and only valid for gm45 > thru gen7. HSW completely changes how this works, so label them > accordingly. > > v2: s/gm45/g4x/ like for the previous patch. > > Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch> I've merged these 3 patches to dinq with Paulo's irc ack. -Daniel -- Daniel Vetter Mail: daniel@ffwll.ch Mobile: +41 (0)79 365 57 48 ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2012-05-08 13:37 UTC | newest] Thread overview: 7+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2012-05-08 12:41 [PATCH 1/3] drm/i915: replace intel_infoframe_freq with VIDEO_DIP_FREQ_VSYNC Daniel Vetter 2012-05-08 12:41 ` [PATCH 2/3] drm/i915: s/i9xx_/gm45_ for the gm45 write_infoframe function Daniel Vetter 2012-05-08 13:15 ` Daniel Vetter 2012-05-08 13:19 ` [PATCH] " Daniel Vetter 2012-05-08 12:41 ` [PATCH 3/3] drm/i915: s/intel_infoframe/gm45_infoframe Daniel Vetter 2012-05-08 13:18 ` [PATCH] " Daniel Vetter 2012-05-08 13:38 ` Daniel Vetter
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