From: Daniel Vetter <daniel@ffwll.ch>
To: Ben Widawsky <ben@bwidawsk.net>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH intel-gpu-tools] tools: Added intel_dpio_read and intel_dpio_write
Date: Mon, 6 Aug 2012 09:16:52 +0200 [thread overview]
Message-ID: <20120806071652.GE5502@phenom.ffwll.local> (raw)
In-Reply-To: <25e00d42d0c3a1f04db332d79a69b63d@bwidawsk.net>
On Thu, Aug 02, 2012 at 09:06:48AM -0700, Ben Widawsky wrote:
> On 2012-08-02 05:07, Vijay Purushothaman wrote:
> >In Valleyview the DPLL and lane control registers are accessible only
> >through side band fabric called DPIO. Added two tools to read and
> >write
> >registers residing in this space.
>
> Could I convince you to use the centralized read/write mmio functions?
> Otherwise, everything seems fine to me here.
I wonder whether we need some kernel interface for this, after all if the
kernel touches this, too, things will blow up. Otoh the kernel only uses
the dpio sideband regs at modeset time, so I guess the risk is minimal.
-Daniel
--
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48
next prev parent reply other threads:[~2012-08-06 7:16 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-08-02 12:07 [PATCH intel-gpu-tools] tools: Added intel_dpio_read and intel_dpio_write Vijay Purushothaman
2012-08-02 16:06 ` Ben Widawsky
2012-08-03 7:05 ` Jani Nikula
2012-08-06 7:45 ` Vijay Purushothaman
2012-08-06 7:16 ` Daniel Vetter [this message]
2012-08-06 21:21 ` Ben Widawsky
2012-08-06 7:40 ` Vijay Purushothaman
2012-08-06 21:26 ` Ben Widawsky
-- strict thread matches above, loose matches on Subject: below --
2012-08-17 12:36 Vijay Purushothaman
2012-08-21 7:31 ` Daniel Vetter
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