[PATCH] drm/i915: enable lvds pin pairs before dpll on gen2

[PATCH] drm/i915: enable lvds pin pairs before dpll on gen2

[Daniel Vetter]

Otherwise things migt not work too well.

Breakage introduced in

commit eb1cbe4848b01f9f073064377875bc7d71eb401b
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date:   Wed Mar 28 23:12:16 2012 +0200

    drm/i915: split PLL update code out of i9xx_crtc_mode_set

Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: stable@vger.kernel.org (for 3.5 only)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 6be59cf..4c4a88b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4227,12 +4227,6 @@ static void i8xx_update_pll(struct drm_crtc *crtc,
 	POSTING_READ(DPLL(pipe));
 	udelay(150);
 
-	I915_WRITE(DPLL(pipe), dpll);
-
-	/* Wait for the clocks to stabilize. */
-	POSTING_READ(DPLL(pipe));
-	udelay(150);
-
 	/* The LVDS pin pair needs to be on before the DPLLs are enabled.
 	 * This is an exception to the general rule that mode_set doesn't turn
 	 * things on.
@@ -4240,6 +4234,12 @@ static void i8xx_update_pll(struct drm_crtc *crtc,
 	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 		intel_update_lvds(crtc, clock, adjusted_mode);
 
+	I915_WRITE(DPLL(pipe), dpll);
+
+	/* Wait for the clocks to stabilize. */
+	POSTING_READ(DPLL(pipe));
+	udelay(150);
+
 	/* The pixel multiplier can only be updated once the
 	 * DPLL is enabled and the clocks are stable.
 	 *
-- 
1.7.11.2

Re: [PATCH] drm/i915: enable lvds pin pairs before dpll on gen2

[Jesse Barnes]

On Tue, 11 Sep 2012 12:37:55 +0200
Daniel Vetter <daniel.vetter@ffwll.ch> wrote:

> Otherwise things migt not work too well.
> 
> Breakage introduced in
> 
> commit eb1cbe4848b01f9f073064377875bc7d71eb401b
> Author: Daniel Vetter <daniel.vetter@ffwll.ch>
> Date:   Wed Mar 28 23:12:16 2012 +0200
> 
>     drm/i915: split PLL update code out of i9xx_crtc_mode_set
> 
> Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
> Cc: stable@vger.kernel.org (for 3.5 only)
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 6be59cf..4c4a88b 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4227,12 +4227,6 @@ static void i8xx_update_pll(struct drm_crtc *crtc,
>  	POSTING_READ(DPLL(pipe));
>  	udelay(150);
>  
> -	I915_WRITE(DPLL(pipe), dpll);
> -
> -	/* Wait for the clocks to stabilize. */
> -	POSTING_READ(DPLL(pipe));
> -	udelay(150);
> -
>  	/* The LVDS pin pair needs to be on before the DPLLs are enabled.
>  	 * This is an exception to the general rule that mode_set doesn't turn
>  	 * things on.
> @@ -4240,6 +4234,12 @@ static void i8xx_update_pll(struct drm_crtc *crtc,
>  	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
>  		intel_update_lvds(crtc, clock, adjusted_mode);
>  
> +	I915_WRITE(DPLL(pipe), dpll);
> +
> +	/* Wait for the clocks to stabilize. */
> +	POSTING_READ(DPLL(pipe));
> +	udelay(150);
> +
>  	/* The pixel multiplier can only be updated once the
>  	 * DPLL is enabled and the clocks are stable.
>  	 *

Looks fine.

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

-- 
Jesse Barnes, Intel Open Source Technology Center

Re: [PATCH] drm/i915: enable lvds pin pairs before dpll on gen2

[Daniel Vetter]

On Wed, Sep 12, 2012 at 08:04:42AM -0700, Jesse Barnes wrote:
> On Tue, 11 Sep 2012 12:37:55 +0200
> Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> 
> > Otherwise things migt not work too well.
> > 
> > Breakage introduced in
> > 
> > commit eb1cbe4848b01f9f073064377875bc7d71eb401b
> > Author: Daniel Vetter <daniel.vetter@ffwll.ch>
> > Date:   Wed Mar 28 23:12:16 2012 +0200
> > 
> >     drm/i915: split PLL update code out of i9xx_crtc_mode_set
> > 
> > Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
> > Cc: stable@vger.kernel.org (for 3.5 only)
> > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 12 ++++++------
> >  1 file changed, 6 insertions(+), 6 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 6be59cf..4c4a88b 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -4227,12 +4227,6 @@ static void i8xx_update_pll(struct drm_crtc *crtc,
> >  	POSTING_READ(DPLL(pipe));
> >  	udelay(150);
> >  
> > -	I915_WRITE(DPLL(pipe), dpll);
> > -
> > -	/* Wait for the clocks to stabilize. */
> > -	POSTING_READ(DPLL(pipe));
> > -	udelay(150);
> > -
> >  	/* The LVDS pin pair needs to be on before the DPLLs are enabled.
> >  	 * This is an exception to the general rule that mode_set doesn't turn
> >  	 * things on.
> > @@ -4240,6 +4234,12 @@ static void i8xx_update_pll(struct drm_crtc *crtc,
> >  	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
> >  		intel_update_lvds(crtc, clock, adjusted_mode);
> >  
> > +	I915_WRITE(DPLL(pipe), dpll);
> > +
> > +	/* Wait for the clocks to stabilize. */
> > +	POSTING_READ(DPLL(pipe));
> > +	udelay(150);
> > +
> >  	/* The pixel multiplier can only be updated once the
> >  	 * DPLL is enabled and the clocks are stable.
> >  	 *
> 
> Looks fine.
> 
> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

Applied to -fixes, but not yet pushed (since Dave hasn't pulled the old
-fixes tree yet).
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch