From: Daniel Vetter <daniel@ffwll.ch>
To: Paulo Zanoni <przanoni@gmail.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: Flush using only the correct base address register
Date: Tue, 30 Oct 2012 20:37:24 +0100 [thread overview]
Message-ID: <20121030193724.GB5755@phenom.ffwll.local> (raw)
In-Reply-To: <CA+gsUGTJ5xcPaBnJPUBEWmcd9fSfzFet5cyox4RyWmzR-JM7xQ@mail.gmail.com>
On Tue, Oct 30, 2012 at 09:01:57AM -0200, Paulo Zanoni wrote:
> Hi
>
> 2012/10/29 Damien Lespiau <damien.lespiau@gmail.com>:
> > From: Damien Lespiau <damien.lespiau@intel.com>
> >
> > We were writing DSP_ADDR and DSP_SURF unconditionally. This did not
> > trigger an unclaimed write before HSW as the address of DSP_ADDR has
> > been repurposed as DSP_LINOFF.
> >
> > On HSW, though, DSP_LINOFF has been removed and then writting to it
> > triggers an unclaimed write.
> >
> > This patch writes to DSP_ADDR or DSP_SURF to flush the display plane
> > configuration depending on the gen we're running on.
> >
> > Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
>
> Looks correct.
>
> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Queued for -next, thanks for the patch.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
prev parent reply other threads:[~2012-10-30 19:36 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-10-29 15:24 [PATCH] drm/i915: Flush using only the correct base address register Damien Lespiau
2012-10-30 11:01 ` Paulo Zanoni
2012-10-30 19:37 ` Daniel Vetter [this message]
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