* [PATCH 1/2] drm/i915: Implement WaDisableHiZPlanesWhenMSAAEnabled
@ 2012-12-14 22:38 Daniel Vetter
2012-12-14 22:38 ` [PATCH 2/2] drm/i915: Implement WaSetupGtModeTdRowDispatch Daniel Vetter
2012-12-17 13:31 ` [PATCH 1/2] drm/i915: Implement WaDisableHiZPlanesWhenMSAAEnabled Rodrigo Vivi
0 siblings, 2 replies; 6+ messages in thread
From: Daniel Vetter @ 2012-12-14 22:38 UTC (permalink / raw)
To: Intel Graphics Development; +Cc: Daniel Vetter
Quoting from Bspec, 3D_CHICKEN1, bit 10
This bit needs to be set always to "1", Project: DevSNB "
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 4 ++++
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f834804..d72744e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -518,6 +518,7 @@
* the enables for writing to the corresponding low bit.
*/
#define _3D_CHICKEN 0x02084
+#define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10)
#define _3D_CHICKEN2 0x0208c
/* Disables pipelining of read flushes past the SF-WIZ interface.
* Required on all Ironlake steppings according to the B-Spec, but the
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index abfff29..2fddd17 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3474,6 +3474,10 @@ static void gen6_init_clock_gating(struct drm_device *dev)
I915_READ(ILK_DISPLAY_CHICKEN2) |
ILK_ELPIN_409_SELECT);
+ /* WaDisableHiZPlanesWhenMSAAEnabled */
+ I915_WRITE(_3D_CHICKEN,
+ _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
+
I915_WRITE(WM3_LP_ILK, 0);
I915_WRITE(WM2_LP_ILK, 0);
I915_WRITE(WM1_LP_ILK, 0);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/2] drm/i915: Implement WaSetupGtModeTdRowDispatch
2012-12-14 22:38 [PATCH 1/2] drm/i915: Implement WaDisableHiZPlanesWhenMSAAEnabled Daniel Vetter
@ 2012-12-14 22:38 ` Daniel Vetter
2012-12-17 11:43 ` Rodrigo Vivi
2012-12-17 13:31 ` [PATCH 1/2] drm/i915: Implement WaDisableHiZPlanesWhenMSAAEnabled Rodrigo Vivi
1 sibling, 1 reply; 6+ messages in thread
From: Daniel Vetter @ 2012-12-14 22:38 UTC (permalink / raw)
To: Intel Graphics Development; +Cc: Daniel Vetter
I'm not really sure, since the w/a entry is as thin on details as
ever, and Bspec doesn't say anything about it. But I've figured only
dispatching to rows 0&1 instead of all four should be the right thing
for GT1.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_reg.h | 3 ++-
drivers/gpu/drm/i915/intel_pm.c | 5 +++++
3 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 514aee8..84be497 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1196,6 +1196,8 @@ struct drm_i915_file_private {
#define IS_IVB_GT1(dev) ((dev)->pci_device == 0x0156 || \
(dev)->pci_device == 0x0152 || \
(dev)->pci_device == 0x015a)
+#define IS_SNB_GT1(dev) ((dev)->pci_device == 0x0102 || \
+ (dev)->pci_device == 0x0106)
#define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
#define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d72744e..4abf4f9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -534,7 +534,8 @@
# define MI_FLUSH_ENABLE (1 << 12)
#define GEN6_GT_MODE 0x20d0
-#define GEN6_GT_MODE_HI (1 << 9)
+#define GEN6_GT_MODE_HI (1 << 9)
+#define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5)
#define GFX_MODE 0x02520
#define GFX_MODE_GEN7 0x0229c
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2fddd17..89324a9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3478,6 +3478,11 @@ static void gen6_init_clock_gating(struct drm_device *dev)
I915_WRITE(_3D_CHICKEN,
_MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
+ /* WaSetupGtModeTdRowDispatch */
+ if (IS_SNB_GT1(dev))
+ I915_WRITE(GEN6_GT_MODE,
+ _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
+
I915_WRITE(WM3_LP_ILK, 0);
I915_WRITE(WM2_LP_ILK, 0);
I915_WRITE(WM1_LP_ILK, 0);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] drm/i915: Implement WaSetupGtModeTdRowDispatch
2012-12-14 22:38 ` [PATCH 2/2] drm/i915: Implement WaSetupGtModeTdRowDispatch Daniel Vetter
@ 2012-12-17 11:43 ` Rodrigo Vivi
2012-12-17 14:11 ` Daniel Vetter
2012-12-17 16:27 ` Daniel Vetter
0 siblings, 2 replies; 6+ messages in thread
From: Rodrigo Vivi @ 2012-12-17 11:43 UTC (permalink / raw)
To: Daniel Vetter; +Cc: Intel Graphics Development
I checked wadatabase and bspec and agree with your understanding, so
feel free to use:
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
On Fri, Dec 14, 2012 at 8:38 PM, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> I'm not really sure, since the w/a entry is as thin on details as
> ever, and Bspec doesn't say anything about it. But I've figured only
> dispatching to rows 0&1 instead of all four should be the right thing
> for GT1.
>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> drivers/gpu/drm/i915/i915_reg.h | 3 ++-
> drivers/gpu/drm/i915/intel_pm.c | 5 +++++
> 3 files changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 514aee8..84be497 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1196,6 +1196,8 @@ struct drm_i915_file_private {
> #define IS_IVB_GT1(dev) ((dev)->pci_device == 0x0156 || \
> (dev)->pci_device == 0x0152 || \
> (dev)->pci_device == 0x015a)
> +#define IS_SNB_GT1(dev) ((dev)->pci_device == 0x0102 || \
> + (dev)->pci_device == 0x0106)
> #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
> #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
> #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d72744e..4abf4f9 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -534,7 +534,8 @@
> # define MI_FLUSH_ENABLE (1 << 12)
>
> #define GEN6_GT_MODE 0x20d0
> -#define GEN6_GT_MODE_HI (1 << 9)
> +#define GEN6_GT_MODE_HI (1 << 9)
> +#define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5)
>
> #define GFX_MODE 0x02520
> #define GFX_MODE_GEN7 0x0229c
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 2fddd17..89324a9 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3478,6 +3478,11 @@ static void gen6_init_clock_gating(struct drm_device *dev)
> I915_WRITE(_3D_CHICKEN,
> _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
>
> + /* WaSetupGtModeTdRowDispatch */
> + if (IS_SNB_GT1(dev))
> + I915_WRITE(GEN6_GT_MODE,
> + _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
> +
> I915_WRITE(WM3_LP_ILK, 0);
> I915_WRITE(WM2_LP_ILK, 0);
> I915_WRITE(WM1_LP_ILK, 0);
> --
> 1.7.10.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] drm/i915: Implement WaDisableHiZPlanesWhenMSAAEnabled
2012-12-14 22:38 [PATCH 1/2] drm/i915: Implement WaDisableHiZPlanesWhenMSAAEnabled Daniel Vetter
2012-12-14 22:38 ` [PATCH 2/2] drm/i915: Implement WaSetupGtModeTdRowDispatch Daniel Vetter
@ 2012-12-17 13:31 ` Rodrigo Vivi
1 sibling, 0 replies; 6+ messages in thread
From: Rodrigo Vivi @ 2012-12-17 13:31 UTC (permalink / raw)
To: Daniel Vetter; +Cc: Intel Graphics Development
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
On Fri, Dec 14, 2012 at 8:38 PM, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> Quoting from Bspec, 3D_CHICKEN1, bit 10
>
> This bit needs to be set always to "1", Project: DevSNB "
>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 4 ++++
> 2 files changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f834804..d72744e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -518,6 +518,7 @@
> * the enables for writing to the corresponding low bit.
> */
> #define _3D_CHICKEN 0x02084
> +#define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10)
> #define _3D_CHICKEN2 0x0208c
> /* Disables pipelining of read flushes past the SF-WIZ interface.
> * Required on all Ironlake steppings according to the B-Spec, but the
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index abfff29..2fddd17 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3474,6 +3474,10 @@ static void gen6_init_clock_gating(struct drm_device *dev)
> I915_READ(ILK_DISPLAY_CHICKEN2) |
> ILK_ELPIN_409_SELECT);
>
> + /* WaDisableHiZPlanesWhenMSAAEnabled */
> + I915_WRITE(_3D_CHICKEN,
> + _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
> +
> I915_WRITE(WM3_LP_ILK, 0);
> I915_WRITE(WM2_LP_ILK, 0);
> I915_WRITE(WM1_LP_ILK, 0);
> --
> 1.7.10.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] drm/i915: Implement WaSetupGtModeTdRowDispatch
2012-12-17 11:43 ` Rodrigo Vivi
@ 2012-12-17 14:11 ` Daniel Vetter
2012-12-17 16:27 ` Daniel Vetter
1 sibling, 0 replies; 6+ messages in thread
From: Daniel Vetter @ 2012-12-17 14:11 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: Daniel Vetter, Intel Graphics Development
On Mon, Dec 17, 2012 at 09:43:37AM -0200, Rodrigo Vivi wrote:
> I checked wadatabase and bspec and agree with your understanding, so
> feel free to use:
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Both picked up for -fixes, thanks for the review.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] drm/i915: Implement WaSetupGtModeTdRowDispatch
2012-12-17 11:43 ` Rodrigo Vivi
2012-12-17 14:11 ` Daniel Vetter
@ 2012-12-17 16:27 ` Daniel Vetter
1 sibling, 0 replies; 6+ messages in thread
From: Daniel Vetter @ 2012-12-17 16:27 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: Daniel Vetter, Intel Graphics Development
On Mon, Dec 17, 2012 at 09:43:37AM -0200, Rodrigo Vivi wrote:
> I checked wadatabase and bspec and agree with your understanding, so
> feel free to use:
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Chris spotted that I've missed the server GT1. Patch fixed up locally.
-Daniel
>
>
>
> On Fri, Dec 14, 2012 at 8:38 PM, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> > I'm not really sure, since the w/a entry is as thin on details as
> > ever, and Bspec doesn't say anything about it. But I've figured only
> > dispatching to rows 0&1 instead of all four should be the right thing
> > for GT1.
> >
> > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> > ---
> > drivers/gpu/drm/i915/i915_drv.h | 2 ++
> > drivers/gpu/drm/i915/i915_reg.h | 3 ++-
> > drivers/gpu/drm/i915/intel_pm.c | 5 +++++
> > 3 files changed, 9 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 514aee8..84be497 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1196,6 +1196,8 @@ struct drm_i915_file_private {
> > #define IS_IVB_GT1(dev) ((dev)->pci_device == 0x0156 || \
> > (dev)->pci_device == 0x0152 || \
> > (dev)->pci_device == 0x015a)
> > +#define IS_SNB_GT1(dev) ((dev)->pci_device == 0x0102 || \
> > + (dev)->pci_device == 0x0106)
> > #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
> > #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
> > #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index d72744e..4abf4f9 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -534,7 +534,8 @@
> > # define MI_FLUSH_ENABLE (1 << 12)
> >
> > #define GEN6_GT_MODE 0x20d0
> > -#define GEN6_GT_MODE_HI (1 << 9)
> > +#define GEN6_GT_MODE_HI (1 << 9)
> > +#define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5)
> >
> > #define GFX_MODE 0x02520
> > #define GFX_MODE_GEN7 0x0229c
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 2fddd17..89324a9 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3478,6 +3478,11 @@ static void gen6_init_clock_gating(struct drm_device *dev)
> > I915_WRITE(_3D_CHICKEN,
> > _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
> >
> > + /* WaSetupGtModeTdRowDispatch */
> > + if (IS_SNB_GT1(dev))
> > + I915_WRITE(GEN6_GT_MODE,
> > + _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
> > +
> > I915_WRITE(WM3_LP_ILK, 0);
> > I915_WRITE(WM2_LP_ILK, 0);
> > I915_WRITE(WM1_LP_ILK, 0);
> > --
> > 1.7.10.4
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>
>
> --
> Rodrigo Vivi
> Blog: http://blog.vivi.eng.br
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2012-12-17 16:26 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
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2012-12-14 22:38 [PATCH 1/2] drm/i915: Implement WaDisableHiZPlanesWhenMSAAEnabled Daniel Vetter
2012-12-14 22:38 ` [PATCH 2/2] drm/i915: Implement WaSetupGtModeTdRowDispatch Daniel Vetter
2012-12-17 11:43 ` Rodrigo Vivi
2012-12-17 14:11 ` Daniel Vetter
2012-12-17 16:27 ` Daniel Vetter
2012-12-17 13:31 ` [PATCH 1/2] drm/i915: Implement WaDisableHiZPlanesWhenMSAAEnabled Rodrigo Vivi
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