Re: [PATCH 05/28] drm/i915: panel power sequencing for VLV eDP

[Jesse Barnes <jbarnes@virtuousgeek.org>]

On Fri, 1 Mar 2013 23:43:36 +0200
Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:

> On Fri, Mar 01, 2013 at 01:14:08PM -0800, Jesse Barnes wrote:
> > PPS register offsets have changed in Valleyview.
> > 
> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> > Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
> > Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
> > Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h      |    9 ++
> >  drivers/gpu/drm/i915/intel_display.c |    1 -
> >  drivers/gpu/drm/i915/intel_dp.c      |  171 ++++++++++++++++++++++++----------
> >  3 files changed, 132 insertions(+), 49 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index b0124e3..766518b 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -4132,6 +4132,15 @@
> >  #define PIPEB_PP_OFF_DELAYS     (VLV_DISPLAY_BASE + 0x6130c)
> >  #define PIPEB_PP_DIVISOR        (VLV_DISPLAY_BASE + 0x61310)
> >  
> > +#define VLV_PIPE_PP_STATUS(pipe) _PIPE(pipe, PIPEA_PP_STATUS, PIPEB_PP_STATUS)
> > +#define VLV_PIPE_PP_CONTROL(pipe) _PIPE(pipe, PIPEA_PP_CONTROL, PIPEB_PP_CONTROL)
> > +#define VLV_PIPE_PP_ON_DELAYS(pipe) \
> > +		_PIPE(pipe, PIPEA_PP_ON_DELAYS, PIPEB_PP_ON_DELAYS)
> > +#define VLV_PIPE_PP_OFF_DELAYS(pipe) \
> > +		_PIPE(pipe, PIPEA_PP_OFF_DELAYS, PIPEB_PP_OFF_DELAYS)
> > +#define VLV_PIPE_PP_DIVISOR(pipe) \
> > +		_PIPE(pipe, PIPEA_PP_DIVISOR, PIPEB_PP_DIVISOR)
> > +
> >  #define PCH_PP_STATUS		0xc7200
> >  #define PCH_PP_CONTROL		0xc7204
> >  #define  PANEL_UNLOCK_REGS	(0xabcd << 16)
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index cb4ecad..3b189fa 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -8551,7 +8551,6 @@ static void intel_setup_outputs(struct drm_device *dev)
> >  			if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
> >  				intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
> >  		}
> > -
> >  		if (I915_READ(VLV_DISPLAY_BASE + SDVOC) & PORT_DETECTED)
> >  			intel_hdmi_init(dev, VLV_DISPLAY_BASE + SDVOC, PORT_C);
> >  	} else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index 2903380..68d238d 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -294,16 +294,20 @@ static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
> >  {
> >  	struct drm_device *dev = intel_dp_to_dev(intel_dp);
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> > +	u32 pp_stat_reg;
> >  
> > -	return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
> > +	pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
> 
> You added the macros that take pipe as a parameter. But why is the
> actual code hardcoded for pipe A?

Just because current systems are hard wired to pipe A at this point.
When we get more diverse configs, we'll have to figure out a way to map
the PPS control regs to the right panel (it may not be pipe, but actual
hard wiring).

-- 
Jesse Barnes, Intel Open Source Technology Center
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