Intel-GFX Archive on lore.kernel.org
 help / color / mirror / Atom feed
From: Jesse Barnes <jbarnes@virtuousgeek.org>
To: Rohit Jain <rohit@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 16/26] drm/i915: turbo & RC6 support for VLV
Date: Thu, 7 Mar 2013 14:27:53 -0800	[thread overview]
Message-ID: <20130307142753.1ca01da4@jbarnes-desktop> (raw)
In-Reply-To: <alpine.DEB.2.02.1303061537060.19691@rohit-desk>

On Wed, 6 Mar 2013 16:21:03 +0530 (IST)
Rohit Jain <rohit@intel.com> wrote:

> 
> 
> On Sat, 2 Mar 2013, Jesse Barnes wrote:
> 
> > From: Ben Widawsky <ben@bwidawsk.net>
> >
> > Uses slightly different interfaces than other platforms.
> >
> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> > ---
> > drivers/gpu/drm/i915/intel_pm.c |  148 +++++++++++++++++++++++++++++++++++++--
> > 1 file changed, 144 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index e3947cb..d16f4f40 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -2477,6 +2477,47 @@ void gen6_set_rps(struct drm_device *dev, u8 val)
> > 	trace_intel_gpu_freq_change(val * 50);
> > }
> >
> > +void valleyview_set_rps(struct drm_device *dev, u8 val)
> > +{
> > +	struct drm_i915_private *dev_priv = dev->dev_private;
> > +	unsigned long timeout = jiffies + msecs_to_jiffies(100);
> > +	u32 limits = gen6_rps_limits(dev_priv, &val);
> > +	u32 pval;
> > +
> > +	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
> > +	WARN_ON(val > dev_priv->rps.max_delay);
> > +	WARN_ON(val < dev_priv->rps.min_delay);
> > +
> > +	if (val == dev_priv->rps.cur_delay)
> > +		return;
> > +
> > +	valleyview_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
> > +
> > +	do {
> > +		valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &pval);
> > +		if (time_after(jiffies, timeout)) {
> > +			DRM_DEBUG_DRIVER("timed out waiting for Punit\n");
> > +			break;
> > +		}
> > +		udelay(10);
> > +	} while (pval & 1);
> > +
> > +	valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &pval);
> > +	if ((pval >> 8) != val)
> > +		DRM_DEBUG_DRIVER("punit overrode freq: %d requested, but got %d\n",
> > +			  val, pval >> 8);
> > +
> > +	/* Make sure we continue to get interrupts
> > +	 * until we hit the minimum or maximum frequencies.
> > +	 */
> > +	I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
> > +
> > +	dev_priv->rps.cur_delay = val;
> 
> Shouldn't we store pval >> 8 instead of val in cur_delay in order to
> reclaim the rps state? If we store val here, the requested frequency will
> eventually exceed max_delay if punit overrides with a lower frequency.
> 

Yeah we should track the current freq here instead.  But we clamp to
max_delay in the caller right?  And yeah I missed the update to
i915_irq.c, I fixed that too.

-- 
Jesse Barnes, Intel Open Source Technology Center

  reply	other threads:[~2013-03-07 22:27 UTC|newest]

Thread overview: 62+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-03-01 22:08 [PATCH 01/26] drm/i915: sprite support for ValleyView Jesse Barnes
2013-03-01 22:08 ` [PATCH 02/26] drm/i915: add sprite assertion function for VLV Jesse Barnes
2013-03-01 22:08 ` [PATCH 03/26] drm/i915: add constant alpha support to sprite ioctl Jesse Barnes
2013-03-01 22:08 ` [PATCH 04/26] drm/i915: update VLV PLL and DPIO code Jesse Barnes
2013-03-01 22:19   ` Jesse Barnes
2013-03-01 22:19   ` Jesse Barnes
2013-03-03 16:21   ` Daniel Vetter
2013-03-05 15:05   ` Jani Nikula
2013-03-08 13:33   ` Jani Nikula
2013-03-08 16:52     ` Jesse Barnes
2013-03-01 22:08 ` [PATCH 05/26] drm/i915: panel power sequencing for VLV eDP Jesse Barnes
2013-03-08 13:51   ` Jani Nikula
2013-03-08 16:53     ` Jesse Barnes
2013-03-01 22:08 ` [PATCH 06/26] drm/i915: add more VLV IDs Jesse Barnes
2013-03-01 22:08 ` [PATCH 07/26] drm/i915: implement WaDisablePSDDualDispatchEnable on VLV Jesse Barnes
2013-03-06 18:20   ` Ville Syrjälä
2013-03-06 18:28     ` Jesse Barnes
2013-03-01 22:08 ` [PATCH 08/26] drm/i915: VLV has force wake Jesse Barnes
2013-03-01 22:08 ` [PATCH 09/26] drm/i915: add power context allocation and setup on VLV Jesse Barnes
2013-03-05 15:10   ` Jani Nikula
2013-03-07 22:56     ` Jesse Barnes
2013-03-01 22:08 ` [PATCH 10/26] drm/i915: add more clock gating for VLV, allow force wake at init Jesse Barnes
2013-03-08 13:39   ` Jani Nikula
2013-03-08 16:52     ` Jesse Barnes
2013-03-08 17:06       ` Ville Syrjälä
2013-03-08 17:08         ` Jesse Barnes
2013-03-01 22:08 ` [PATCH 11/26] drm/i915: fix VLV limits and m/n/p calculations Jesse Barnes
2013-03-05 12:56   ` Daniel Vetter
2013-03-07 21:41     ` Jesse Barnes
2013-03-01 22:08 ` [PATCH 12/26] drm/i915: disable watermarks on VLV, pondicherry takes care of this Jesse Barnes
2013-03-01 22:08 ` [PATCH 13/26] drm/i915: use gen6 stolen check on VLV Jesse Barnes
2013-03-06 18:45   ` Ville Syrjälä
2013-03-06 19:07     ` Daniel Vetter
2013-03-01 22:08 ` [PATCH 14/26] drm/i915: add Punit read/write routines for VLV Jesse Barnes
2013-03-01 22:08 ` [PATCH 15/26] drm/i915: add media well to VLV force wake routines Jesse Barnes
2013-03-06 18:28   ` Ville Syrjälä
2013-03-06 18:33     ` Jesse Barnes
2013-03-06 18:52       ` Ville Syrjälä
2013-03-06 19:10       ` Daniel Vetter
2013-03-06 20:53         ` Jesse Barnes
2013-03-01 22:08 ` [PATCH 16/26] drm/i915: turbo & RC6 support for VLV Jesse Barnes
2013-03-06 10:51   ` Rohit Jain
2013-03-07 22:27     ` Jesse Barnes [this message]
2013-03-11  6:21       ` Jain, Rohit
2013-03-01 22:08 ` [PATCH 17/26] drm/i915: remove VLV MSI IRQ hack Jesse Barnes
2013-04-26 21:40   ` Daniel Vetter
2013-03-01 22:08 ` [PATCH 18/26] drm/i915: don't enumerate VGA on VLV Jesse Barnes
2013-03-01 22:08 ` [PATCH 19/26] drm/i915: DSPFW and BLC regs are in the display offset range Jesse Barnes
2013-03-08 13:57   ` Jani Nikula
2013-03-08 16:54     ` Jesse Barnes
2013-03-01 22:08 ` [PATCH 20/26] drm/i915: don't use plane pipe select on VLV Jesse Barnes
2013-03-01 22:08 ` [PATCH 21/26] drm/i915: use VLV DIP routines " Jesse Barnes
2013-03-01 22:08 ` [PATCH 22/26] drm/i915: export intel_dpio_write for use in intel_dp.c Jesse Barnes
2013-03-01 22:08 ` [PATCH 23/26] drm/i915/dp: program VSwing and Preemphasis control settings on VLV Jesse Barnes
2013-03-01 22:08 ` [PATCH 24/26] drm/i915: VLV doesn't have HDMI on port C Jesse Barnes
2013-03-19 13:00   ` Ville Syrjälä
2013-03-19 15:27     ` Jesse Barnes
2013-03-01 22:08 ` [PATCH 25/26] drm/i915/dp: don't use ILK paths on VLV Jesse Barnes
2013-03-08 14:12   ` Jani Nikula
2013-03-08 14:57     ` Ville Syrjälä
2013-03-01 22:08 ` [PATCH 26/26] drm/i915/dp: add pre-PCH eDP checking to DP detect for VLV Jesse Barnes
2013-03-08 14:16 ` [PATCH 01/26] drm/i915: sprite support for ValleyView Jani Nikula

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20130307142753.1ca01da4@jbarnes-desktop \
    --to=jbarnes@virtuousgeek.org \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=rohit@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox