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From: Jesse Barnes <jbarnes@virtuousgeek.org>
To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: Fix pipe enabled mask for pipe C in WM calculations
Date: Wed, 20 Mar 2013 15:50:06 -0700	[thread overview]
Message-ID: <20130320155006.5427638e@jbarnes-desktop> (raw)
In-Reply-To: <20130320223933.GA7131@cantiga.alporthouse.com>

On Wed, 20 Mar 2013 22:39:33 +0000
Chris Wilson <chris@chris-wilson.co.uk> wrote:

> On Wed, Mar 20, 2013 at 11:05:37PM +0100, Daniel Vetter wrote:
> > On Wed, Mar 20, 2013 at 09:51:05PM +0200, ville.syrjala@linux.intel.com wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > Cc: stable@vger.kernel.org
> > 
> > One of the stable rules is that patches should fix real issues. So can you
> > please hunt through bugzillas quickly and feed this to relevant bug
> > reports?
> 
> It would take an astute user to notice that his machine was not using a
> lower power self-refresh FIFO mode. And the number of machines that only
> set up the third pipe is going to be small, so the impact minor. It
> will not fix any of the three pipe issues we have open, for example.
> 
> The patch is correct, though had I used enabled |= 1 << PIPE_[ABC] it
> would have probably prevented this bug.
> 
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

My fault; I had to merge the initial 3 pipe code after Chris changed
this and added the enabled bitfield.  I remember complaining about it
at the time, I must have been feeling passive-aggressive and snuck the
bug in. :)

-- 
Jesse Barnes, Intel Open Source Technology Center
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      parent reply	other threads:[~2013-03-20 22:50 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-03-20 19:51 [PATCH] drm/i915: Fix pipe enabled mask for pipe C in WM calculations ville.syrjala
2013-03-20 22:05 ` [Intel-gfx] " Daniel Vetter
2013-03-20 22:39   ` Chris Wilson
2013-03-20 22:49     ` Daniel Vetter
2013-03-20 22:50     ` Jesse Barnes [this message]

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