Re: [PATCH] drm/i915: s/mdelay/msleep/

[Jesse Barnes <jbarnes@virtuousgeek.org>]

On Sun,  7 Apr 2013 11:13:03 +0200
Daniel Vetter <daniel.vetter@ffwll.ch> wrote:

> The first in wait_pipe_off is really just a delay loop to wait for the
> scanline counter to settle (which takes about a frame worth of time).
> So also shrink it a bit.
> 
> The other is in the ilk dprs code. If we need _exactly_ an 1ms wait in
> there, that's already not guaranteed with the current code (since
> especially at start-up we're likely to get scheduled away in between).
> So replace those, too.
> 
> Noticed while trying to understand why we've again broken the panel
> fitter.
> 
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
>  drivers/gpu/drm/i915/intel_display.c |    2 +-
>  drivers/gpu/drm/i915/intel_pm.c      |    6 +++---
>  2 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index b884932..908f697 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -990,7 +990,7 @@ void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
>  		/* Wait for the display line to settle */
>  		do {
>  			last_line = I915_READ(reg) & line_mask;
> -			mdelay(5);
> +			msleep(1);
>  		} while (((I915_READ(reg) & line_mask) != last_line) &&
>  			 time_after(timeout, jiffies));
>  		if (time_after(jiffies, timeout))
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 17f157a..986770e 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2380,7 +2380,7 @@ static void ironlake_enable_drps(struct drm_device *dev)
>  
>  	if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
>  		DRM_ERROR("stuck trying to change perf mode\n");
> -	mdelay(1);
> +	msleep(1);
>  
>  	ironlake_set_drps(dev, fstart);
>  
> @@ -2411,10 +2411,10 @@ static void ironlake_disable_drps(struct drm_device *dev)
>  
>  	/* Go back to the starting frequency */
>  	ironlake_set_drps(dev, dev_priv->ips.fstart);
> -	mdelay(1);
> +	msleep(1);
>  	rgvswctl |= MEMCTL_CMD_STS;
>  	I915_WRITE(MEMSWCTL, rgvswctl);
> -	mdelay(1);
> +	msleep(1);
>  
>  	spin_unlock_irq(&mchdev_lock);
>  }

Fine with me.  Chris is right that I probably added these, back when I
thought a few ms at startup or mode set time wasn't so long.  Now of
course it's an eternity.

-- 
Jesse Barnes, Intel Open Source Technology Center