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From: Daniel Vetter <daniel@ffwll.ch>
To: Chris Wilson <chris@chris-wilson.co.uk>,
	Daniel Vetter <daniel.vetter@ffwll.ch>,
	Intel Graphics Development <intel-gfx@lists.freedesktop.org>,
	Arthur Ranyan <arthur.j.runyan@intel.com>,
	stable@vger.kernel.org
Subject: Re: [Intel-gfx] [PATCH] drm/i915: Fix up sdvo hpd pins for i965g/gm
Date: Tue, 25 Jun 2013 11:39:15 +0200	[thread overview]
Message-ID: <20130625093915.GO5823@phenom.ffwll.local> (raw)
In-Reply-To: <20130625074309.GB19636@cantiga.alporthouse.com>

On Tue, Jun 25, 2013 at 08:43:09AM +0100, Chris Wilson wrote:
> On Mon, Jun 24, 2013 at 09:04:40PM +0200, Daniel Vetter wrote:
> > Bspec seems to be full of lies, at least it disagress with reality:
> > Two systems corrobated that SDVO hpd bits are the same as on gen3.
> > 
> > Cc: Arthur Ranyan <arthur.j.runyan@intel.com>
> > Cc: Chris Wilson <chris@chris-wilson.co.uk>
> > Tested-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Reported-and-tested-by: Alex Fiestas <afiestas@kde.org>
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=58405
> > Cc: stable@vger.kernel.org
> > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> Acked-by: Chris Wilson <chris@chris-wilson.co.uk>

Queued for -next, let's see whether there's a funny gen4.0 version out
there where Bspec is right ...
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

      reply	other threads:[~2013-06-25  9:39 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-06-24 19:04 [PATCH] drm/i915: Fix up sdvo hpd pins for i965g/gm Daniel Vetter
2013-06-24 19:33 ` Daniel Vetter
2013-06-25  7:43 ` Chris Wilson
2013-06-25  9:39   ` Daniel Vetter [this message]

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