From: Daniel Vetter <daniel@ffwll.ch>
To: Chon Ming Lee <chon.ming.lee@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: Fix VLV eDP timing v2
Date: Wed, 25 Sep 2013 10:20:26 +0200 [thread overview]
Message-ID: <20130925082026.GI12663@phenom.ffwll.local> (raw)
In-Reply-To: <1380095271-10016-1-git-send-email-chon.ming.lee@intel.com>
On Wed, Sep 25, 2013 at 03:47:51PM +0800, Chon Ming Lee wrote:
> Fix the typo in previous commit for DP 1.62 divisor.
> drm/i915: Move Valleyview DP DPLL divisor calc to intel_dp_set_clock v2
>
> v2: sigh, the m1 div is 3.
>
> Reported-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com>
Ok, I'll try this one ...
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
next prev parent reply other threads:[~2013-09-25 8:20 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-09-14 0:27 [PATCH] Revert "drm/i915: Move Valleyview DP DPLL divisor calc to intel_dp_set_clock v2" Jesse Barnes
2013-09-14 0:29 ` Jesse Barnes
2013-09-14 11:28 ` Daniel Vetter
2013-09-25 7:36 ` [PATCH] drm/i915: Fix VLV eDP timing Chon Ming Lee
2013-09-25 7:47 ` [PATCH] drm/i915: Fix VLV eDP timing v2 Chon Ming Lee
2013-09-25 8:20 ` Daniel Vetter [this message]
2013-09-25 8:00 ` [PATCH] drm/i915: Fix VLV eDP timing Daniel Vetter
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