From: Jesse Barnes <jbarnes@virtuousgeek.org>
To: Andi Kleen <andi@firstfloor.org>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: intel_pre_enable_dp
Date: Sun, 29 Sep 2013 17:16:58 -0700 [thread overview]
Message-ID: <20130929171658.6eab2b61@jbarnes-desktop> (raw)
In-Reply-To: <20130929235347.GA2214@two.firstfloor.org>
On Mon, 30 Sep 2013 01:53:47 +0200
Andi Kleen <andi@firstfloor.org> wrote:
> On Mon, Sep 30, 2013 at 01:48:13AM +0200, Andi Kleen wrote:
> >
> > Jesse,
> >
> > I was playing with a static analyzer and it flagged the following
> > code of yours.
> >
> > Is the val = 0 directly after the register read correct and intended?
>
> Also the same pattern is in other places, like vlv_pre_enable_dp.
Hm definitely looks suspect... I'll check it out. On the plus side
that code is actually working in practice, so maybe the zeroing isn't
too harmful. :)
--
Jesse Barnes, Intel Open Source Technology Center
prev parent reply other threads:[~2013-09-30 0:16 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-09-29 23:48 intel_pre_enable_dp Andi Kleen
2013-09-29 23:53 ` intel_pre_enable_dp Andi Kleen
2013-09-30 0:16 ` Jesse Barnes [this message]
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