From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Paulo Zanoni <przanoni@gmail.com>
Cc: Intel Graphics Development <intel-gfx@lists.freedesktop.org>
Subject: Re: [PATCH 07/16] drm/i915: Refactor wm_lp to level calculation
Date: Fri, 11 Oct 2013 11:10:30 +0300 [thread overview]
Message-ID: <20131011081030.GQ13047@intel.com> (raw)
In-Reply-To: <CA+gsUGRWoSsP8kXzH+ympfbJSbo+nEVz7Nq=2LXBf6Oo48qrOQ@mail.gmail.com>
On Thu, Oct 10, 2013 at 07:42:22PM -0300, Paulo Zanoni wrote:
> 2013/10/9 <ville.syrjala@linux.intel.com>:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > On HSW the LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4. We make the
> > conversion from LPn to to the level at one point current. Later we're
> > going to do it in a few places, so move it to a separate function.
>
> I guess this function will work on ILK/SNB/IVB even though they don't
> follow this rule, right? If yes: Reviewed-by: Paulo Zanoni
> <paulo.r.zanoni@intel.com>
Yes, level 4 is never enabled on those, so we never do the +1.
>
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_pm.c | 8 +++++++-
> > 1 file changed, 7 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index c17518d..d307039 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -2705,6 +2705,12 @@ static void ilk_wm_merge(struct drm_device *dev,
> > }
> > }
> >
> > +static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
> > +{
> > + /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
> > + return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
> > +}
> > +
> > static void hsw_compute_wm_results(struct drm_device *dev,
> > const struct intel_pipe_wm *merged,
> > struct hsw_wm_values *results)
> > @@ -2718,7 +2724,7 @@ static void hsw_compute_wm_results(struct drm_device *dev,
> > for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
> > const struct intel_wm_level *r;
> >
> > - level = wm_lp + (wm_lp >= 2 && merged->wm[4].enable);
> > + level = ilk_wm_lp_to_level(wm_lp, merged);
> >
> > r = &merged->wm[level];
> > if (!r->enable)
> > --
> > 1.8.1.5
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>
>
> --
> Paulo Zanoni
--
Ville Syrjälä
Intel OTC
next prev parent reply other threads:[~2013-10-11 8:10 UTC|newest]
Thread overview: 59+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-10-09 16:17 [PATCH 00/16] drm/i915: More HSW watermark prep work v2 ville.syrjala
2013-10-09 16:17 ` [PATCH v2 01/16] drm/i915: Add intel_pipe_wm and prepare for watermark pre-compute ville.syrjala
2013-10-10 21:43 ` Paulo Zanoni
2013-10-11 8:07 ` Ville Syrjälä
2013-10-11 13:51 ` Paulo Zanoni
2013-10-09 16:17 ` [PATCH 02/16] drm/i915: Don't re-compute pipe watermarks except for the affected pipe ville.syrjala
2013-10-10 21:57 ` Paulo Zanoni
2013-10-09 16:17 ` [PATCH 03/16] drm/i915: Move LP1+ watermark merging out from hsw_compute_wm_results() ville.syrjala
2013-10-10 22:04 ` Paulo Zanoni
2013-10-09 16:17 ` [PATCH 04/16] drm/i915: Use intel_pipe_wm in hsw_find_best_results ville.syrjala
2013-10-10 22:20 ` Paulo Zanoni
2013-10-09 16:17 ` [PATCH 05/16] drm/i915: Move some computations out from hsw_compute_wm_parameters() ville.syrjala
2013-10-10 22:34 ` Paulo Zanoni
2013-10-11 8:26 ` Ville Syrjälä
2013-10-11 12:26 ` [PATCH 17/16] drm/i915: Check 5/6 DDB split only when sprites are enabled ville.syrjala
2013-10-11 17:21 ` Paulo Zanoni
2013-10-11 13:53 ` [PATCH 05/16] drm/i915: Move some computations out from hsw_compute_wm_parameters() Paulo Zanoni
2013-10-09 16:18 ` [PATCH 06/16] drm/i915: Don't compute 5/6 DDB split w/ zero active pipes ville.syrjala
2013-10-10 22:38 ` Paulo Zanoni
2013-10-09 16:18 ` [PATCH 07/16] drm/i915: Refactor wm_lp to level calculation ville.syrjala
2013-10-10 22:42 ` Paulo Zanoni
2013-10-11 8:10 ` Ville Syrjälä [this message]
2013-10-09 16:18 ` [PATCH 08/16] drm/i915: Kill fbc_wm_enabled from intel_wm_config ville.syrjala
2013-10-10 22:45 ` Paulo Zanoni
2013-10-09 16:18 ` [PATCH 09/16] drm/i915: Store current watermark state in dev_priv->wm ville.syrjala
2013-10-11 14:21 ` Paulo Zanoni
2013-10-15 8:24 ` Daniel Vetter
2013-10-15 16:49 ` Paulo Zanoni
2013-10-09 16:18 ` [PATCH 10/16] drm/i915: Improve watermark dirtyness checks ville.syrjala
2013-10-11 15:02 ` Paulo Zanoni
2013-10-11 15:48 ` Ville Syrjälä
2013-10-11 16:12 ` Paulo Zanoni
2013-10-11 16:39 ` [PATCH v2 " ville.syrjala
2013-10-11 17:57 ` Paulo Zanoni
2013-10-09 16:18 ` [PATCH 11/16] drm/i915: Init HSW watermark tracking in intel_modeset_setup_hw_state() ville.syrjala
2013-10-11 16:45 ` Paulo Zanoni
2013-10-11 17:15 ` Ville Syrjälä
2013-10-11 18:15 ` Paulo Zanoni
2013-10-11 19:12 ` Ville Syrjälä
2013-10-11 19:46 ` Paulo Zanoni
2013-10-14 11:21 ` Ville Syrjälä
2013-10-14 11:55 ` [PATCH v2 " ville.syrjala
2013-10-14 13:56 ` Paulo Zanoni
2013-10-09 16:18 ` [PATCH 12/16] drm/i915: Remove a somewhat silly debug print from watermark code ville.syrjala
2013-10-11 16:48 ` Paulo Zanoni
2013-10-09 16:18 ` [PATCH v2 13/16] drm/i915: Adjust watermark register masks ville.syrjala
2013-10-11 17:02 ` Paulo Zanoni
2013-10-09 16:18 ` [PATCH 14/16] drm/i915: Add watermark tracepoints ville.syrjala
2013-10-11 19:40 ` Paulo Zanoni
2013-10-15 8:43 ` Daniel Vetter
2013-10-15 10:11 ` Ville Syrjälä
2013-10-15 10:59 ` Daniel Vetter
2013-10-09 16:18 ` [PATCH 15/16] drm/i915: Rename ilk_wm_max to ilk_compute_wm_maximums ville.syrjala
2013-10-11 17:07 ` Paulo Zanoni
2013-10-09 16:18 ` [PATCH 16/16] drm/i915: Rename ilk_check_wm to ilk_validate_wm_level ville.syrjala
2013-10-11 17:08 ` Paulo Zanoni
2013-10-15 9:16 ` Daniel Vetter
2013-10-15 17:01 ` Paulo Zanoni
2013-10-15 17:46 ` Ville Syrjälä
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