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From: Daniel Vetter <daniel@ffwll.ch>
To: Intel Graphics Development <intel-gfx@lists.freedesktop.org>
Cc: Jani Nikula <jani.nikula@intel.com>,
	Daniel Vetter <daniel.vetter@ffwll.ch>
Subject: Re: [PATCH] drm/i915: dp aux irq support for g4x/vlv
Date: Mon, 18 Nov 2013 09:01:55 +0100	[thread overview]
Message-ID: <20131118080117.GA8203@phenom.ffwll.local> (raw)
In-Reply-To: <1383209616-3305-1-git-send-email-daniel.vetter@ffwll.ch>

On Thu, Oct 31, 2013 at 09:53:36AM +0100, Daniel Vetter wrote:
> Now we have this everywhere. Next up would be to wire up the DP
> hotplug pin to speed up panel power sequencing for eDP panels ...
> 
> I've decided to leave the has_aux_irq logic in the code, it should
> come handy for hw bringup.
> 
> For testing/fail-safety the dp aux code already has a timeout when
> waiting for interrupts to signal completion and screams rather loud if
> they don't arrive in time. Given that we need a real piece of hw to
> talk to anyway this is probably as good as it gets.
> 
> v2: Don't check the dp aux channel bits on i965 machines, they have a
> different meaning there. Yay for reusing bits at will! Spotted by
> Jani.
> 
> Cc: Jani Nikula <jani.nikula@intel.com>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

Oops, I've seemed to have missed this one here. Merged to dinq.
-Daniel

> ---
>  drivers/gpu/drm/i915/i915_irq.c | 7 +++++++
>  drivers/gpu/drm/i915/i915_reg.h | 4 ++++
>  drivers/gpu/drm/i915/intel_dp.c | 2 +-
>  3 files changed, 12 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 2a44816..a2bfcdb 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -1375,6 +1375,9 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
>  
>  			intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
>  
> +			if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
> +				dp_aux_irq_handler(dev);
> +
>  			I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
>  			I915_READ(PORT_HOTPLUG_STAT);
>  		}
> @@ -3256,6 +3259,10 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
>  			intel_hpd_irq_handler(dev, hotplug_trigger,
>  					      IS_G4X(dev) ? hpd_status_gen4 : hpd_status_i915);
>  
> +			if (IS_G4X(dev) &&
> +			    (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X))
> +				dp_aux_irq_handler(dev);
> +
>  			I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
>  			I915_READ(PORT_HOTPLUG_STAT);
>  		}
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4d2db59..447fd83 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2116,6 +2116,10 @@
>  #define   CRT_HOTPLUG_MONITOR_COLOR		(3 << 8)
>  #define   CRT_HOTPLUG_MONITOR_MONO		(2 << 8)
>  #define   CRT_HOTPLUG_MONITOR_NONE		(0 << 8)
> +#define   DP_AUX_CHANNEL_D_INT_STATUS_G4X	(1 << 6)
> +#define   DP_AUX_CHANNEL_C_INT_STATUS_G4X	(1 << 5)
> +#define   DP_AUX_CHANNEL_B_INT_STATUS_G4X	(1 << 4)
> +#define   DP_AUX_CHANNEL_MASK_INT_STATUS_G4X	(1 << 4)
>  /* SDVO is different across gen3/4 */
>  #define   SDVOC_HOTPLUG_INT_STATUS_G4X		(1 << 3)
>  #define   SDVOB_HOTPLUG_INT_STATUS_G4X		(1 << 2)
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index b3cc333..7fa4518 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -404,7 +404,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
>  	int i, ret, recv_bytes;
>  	uint32_t status;
>  	int try, precharge, clock = 0;
> -	bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
> +	bool has_aux_irq = true;
>  
>  	/* dp aux is extremely sensitive to irq latency, hence request the
>  	 * lowest possible wakeup latency and so prevent the cpu from going into
> -- 
> 1.8.4.rc3
> 

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

  reply	other threads:[~2013-11-18  8:01 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-10-30 20:19 [PATCH] drm/i915: dp aux irq support for g4x/vlv Daniel Vetter
2013-10-31  8:44 ` Jani Nikula
2013-10-31  8:53   ` Daniel Vetter
2013-11-18  8:01     ` Daniel Vetter [this message]
     [not found]     ` <10352_1384761690_5289C95A_10352_731_1_20131118080117.GA8203@phenom.ffwll.local>
2013-11-18  9:42       ` [PATCH] Watermark level workaround for i830 Thomas Richter
2013-11-19  9:55         ` Fwd: " Thomas Richter
2013-11-19 10:24           ` Daniel Vetter

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