* [PATCH 1/2] drm/i915/vlv: use a lower RC6 timeout on VLV
@ 2013-11-15 17:32 Jesse Barnes
2013-11-15 17:32 ` [PATCH 2/2] drm/i915/vlv: use parallel context restore when coming out of RC6 Jesse Barnes
[not found] ` <CAOh5HuXbrDaOwzeOvO0QD4x7xEJuyWRmVzhE51DcrXGrow2dUg@mail.gmail.com>
0 siblings, 2 replies; 5+ messages in thread
From: Jesse Barnes @ 2013-11-15 17:32 UTC (permalink / raw)
To: intel-gfx
We use timeout mode, and we need to lower the timeout to get good RC6
residency when loads are running. This gets me from 0% residency during
glxgears to 77%, which is a pretty good improvement. This value also
matches the current BWG recommentations.
Tested-by: "Meng, Mengmeng" <mengmeng.meng@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
drivers/gpu/drm/i915/intel_pm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 172efa0..5d3912a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4102,7 +4102,7 @@ static void valleyview_enable_rps(struct drm_device *dev)
for_each_ring(ring, dev_priv, i)
I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
- I915_WRITE(GEN6_RC6_THRESHOLD, 0xc350);
+ I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
/* allows RC6 residency counter to work */
I915_WRITE(VLV_COUNTER_CONTROL,
--
1.8.4.2
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH 2/2] drm/i915/vlv: use parallel context restore when coming out of RC6
2013-11-15 17:32 [PATCH 1/2] drm/i915/vlv: use a lower RC6 timeout on VLV Jesse Barnes
@ 2013-11-15 17:32 ` Jesse Barnes
[not found] ` <CAOh5HuUMHUm0rqA3VbN00sOaae5qGgLzdAwHbMtEP3gKsQfdXg@mail.gmail.com>
[not found] ` <CAOh5HuXbrDaOwzeOvO0QD4x7xEJuyWRmVzhE51DcrXGrow2dUg@mail.gmail.com>
1 sibling, 1 reply; 5+ messages in thread
From: Jesse Barnes @ 2013-11-15 17:32 UTC (permalink / raw)
To: intel-gfx
Setting this bit restores all ring contexts in parallel rather than
serially. Matches current BWG recommendations.
Tested-by: "Meng, Mengmeng" <mengmeng.meng@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 849e595..40b1136 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4891,6 +4891,7 @@
#define GEN6_RC_CTL_RC6_ENABLE (1<<18)
#define GEN6_RC_CTL_RC1e_ENABLE (1<<20)
#define GEN6_RC_CTL_RC7_ENABLE (1<<22)
+#define VLV_RC_CTL_CTX_RST_PARALLEL (1<<24)
#define GEN7_RC_CTL_TO_MODE (1<<28)
#define GEN6_RC_CTL_EI_MODE(x) ((x)<<27)
#define GEN6_RC_CTL_HW_ENABLE (1<<31)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5d3912a..6a21d11 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4110,7 +4110,7 @@ static void valleyview_enable_rps(struct drm_device *dev)
VLV_MEDIA_RC6_COUNT_EN |
VLV_RENDER_RC6_COUNT_EN));
if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
- rc6_mode = GEN7_RC_CTL_TO_MODE;
+ rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
intel_print_rc6_info(dev, rc6_mode);
--
1.8.4.2
^ permalink raw reply related [flat|nested] 5+ messages in thread[parent not found: <CAOh5HuXbrDaOwzeOvO0QD4x7xEJuyWRmVzhE51DcrXGrow2dUg@mail.gmail.com>]
* Re: [PATCH 1/2] drm/i915/vlv: use a lower RC6 timeout on VLV
[not found] ` <CAOh5HuXbrDaOwzeOvO0QD4x7xEJuyWRmVzhE51DcrXGrow2dUg@mail.gmail.com>
@ 2013-11-28 8:17 ` S, Deepak
0 siblings, 0 replies; 5+ messages in thread
From: S, Deepak @ 2013-11-28 8:17 UTC (permalink / raw)
To: Jesse Barnes; +Cc: intel-gfx@lists.freedesktop.org
[-- Attachment #1.1: Type: text/plain, Size: 1723 bytes --]
Patches looks fine.
Reviewed-by: Deepak S <deepak.s@inel.com<mailto:jbarnes@virtuousgeek.org>>
From: Jesse Barnes <jbarnes@virtuousgeek.org<mailto:jbarnes@virtuousgeek.org>>
Date: Fri, Nov 15, 2013 at 11:02 PM
Subject: [Intel-gfx] [PATCH 1/2] drm/i915/vlv: use a lower RC6 timeout on VLV
To: intel-gfx@lists.freedesktop.org<mailto:intel-gfx@lists.freedesktop.org>
We use timeout mode, and we need to lower the timeout to get good RC6
residency when loads are running. This gets me from 0% residency during
glxgears to 77%, which is a pretty good improvement. This value also
matches the current BWG recommentations.
Tested-by: "Meng, Mengmeng" <mengmeng.meng@intel.com<mailto:mengmeng.meng@intel.com>>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org<mailto:jbarnes@virtuousgeek.org>>
---
drivers/gpu/drm/i915/intel_pm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 172efa0..5d3912a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4102,7 +4102,7 @@ static void valleyview_enable_rps(struct drm_device *dev)
for_each_ring(ring, dev_priv, i)
I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
- I915_WRITE(GEN6_RC6_THRESHOLD, 0xc350);
+ I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
/* allows RC6 residency counter to work */
I915_WRITE(VLV_COUNTER_CONTROL,
--
1.8.4.2
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Intel-gfx mailing list
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Deepak S
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^ permalink raw reply related [flat|nested] 5+ messages in thread
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2013-11-15 17:32 [PATCH 1/2] drm/i915/vlv: use a lower RC6 timeout on VLV Jesse Barnes
2013-11-15 17:32 ` [PATCH 2/2] drm/i915/vlv: use parallel context restore when coming out of RC6 Jesse Barnes
[not found] ` <CAOh5HuUMHUm0rqA3VbN00sOaae5qGgLzdAwHbMtEP3gKsQfdXg@mail.gmail.com>
2013-11-28 8:17 ` S, Deepak
2013-11-28 10:03 ` Daniel Vetter
[not found] ` <CAOh5HuXbrDaOwzeOvO0QD4x7xEJuyWRmVzhE51DcrXGrow2dUg@mail.gmail.com>
2013-11-28 8:17 ` [PATCH 1/2] drm/i915/vlv: use a lower RC6 timeout on VLV S, Deepak
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