[PATCH 0/6] Enabling DRRS support in the kernel

[PATCH 0/6] Enabling DRRS support in the kernel

[Vandana Kannan]

Dynamic Refresh Rate Switching (DRRS) is a power conservation feature which     
enables switching between low and high refresh rates based on the usage         
scenario. This feature is applicable for internal eDP panel. Indication that    
the panel can support DRRS is given by the panel EDID, which would list         
multiple refresh rates for one resolution.                                      
DRRS is of 2 types -                                                            
Static DRRS involves execution of the entire mode set sequence to switch        
between refresh rate.                                                           
seamless DRRS involves refresh rate switching during runtime without any        
blanking effect/mode set.                                                       
The vendor fills in a VBT field indicating static/seamless DRRS based on the    
panel spec. This information is needed to enable seamless DRRS in kernel.       
The patch series supports idleness detection in display i915 driver and switch  
to low refresh rate. It also provides set_property API for user space to         
request for different refresh rates for active use cases like video playback    
at 48/50 Hz.       


Pradeep Bhat (5):
  drm/i915: Adding VBT fields to support eDP DRRS feature
  drm/i915: Parse EDID probed modes for DRRS support
  drm/i915: Add support for DRRS set property to switch RR
  drm/i915: Support to read DMRRS field from VBT structure
  drm/i915: Adding support for DMRRS for media playback

Vandana Kannan (1):
  drm/i915: Idleness detection for DRRS

 drivers/gpu/drm/i915/i915_drv.h      |   30 ++++
 drivers/gpu/drm/i915/i915_reg.h      |    1 +
 drivers/gpu/drm/i915/intel_bios.c    |   25 +++
 drivers/gpu/drm/i915/intel_bios.h    |   31 ++++
 drivers/gpu/drm/i915/intel_display.c |   13 ++
 drivers/gpu/drm/i915/intel_dp.c      |  296 ++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_drv.h     |   48 ++++++
 drivers/gpu/drm/i915/intel_pm.c      |  113 +++++++++++++
 drivers/gpu/drm/i915/intel_sprite.c  |    3 +
 9 files changed, 560 insertions(+)

-- 
1.7.9.5

[PATCH 1/6] drm/i915: Adding VBT fields to support eDP DRRS feature

[Vandana Kannan]

From: Pradeep Bhat <pradeep.bhat@intel.com>

This patch reads the DRRS support and Mode type from VBT fields.
The read information will be stored in VBT struct during BIOS
parsing. The above functionality is needed for decision making
whether DRRS feature is supported in i915 driver for eDP panels.
This information helps us decide if seamless DRRS can be done
at runtime to support certain power saving features. This patch
was tested by setting necessary bit in VBT struct and merging
the new VBT with system BIOS so that we can read the value. This
feature is for PV2 and not for PV1.

Signed-off-by: Pradeep Bhat <pradeep.bhat@intel.com>
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h   |    9 +++++++++
 drivers/gpu/drm/i915/intel_bios.c |   23 +++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_bios.h |   29 +++++++++++++++++++++++++++++
 3 files changed, 61 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b12d942..98aac55 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1128,6 +1128,15 @@ struct intel_vbt_data {
 	int lvds_ssc_freq;
 	unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
 
+	/**
+	 * DRRS mode type (Seamless OR Static DRRS)
+	 * drrs_mode Val 0x2 is Seamless DRRS and 0 is Static DRRS.
+	 * These values correspond to the VBT values for drrs mode.
+	 */
+	int drrs_mode;
+	/* DRRS enabled or disabled in VBT */
+	bool intel_drrs_enabled;
+
 	/* eDP */
 	int edp_rate;
 	int edp_lanes;
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index e29bcae..4aaa0f9 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -195,6 +195,21 @@ get_lvds_fp_timing(const struct bdb_header *bdb,
 	return (const struct lvds_fp_timing *)((const u8 *)bdb + ofs);
 }
 
+/**
+ * This function returns the 2 bit information pertaining to a panel type
+ * present in a 32 bit field in VBT blocks. There are 16 panel types in VBT
+ * each occupying 2 bits of information in some 32 bit fields of VBT blocks.
+ */
+static int
+get_mode_by_paneltype(unsigned int word)
+{
+	/**
+	 * The caller of this API should interpret the 2 bits
+	 * based on VBT description for that field.
+	 */
+	return (word >> ((panel_type - 1) * 2)) & MODE_MASK;
+}
+
 /* Try to find integrated panel data */
 static void
 parse_lfp_panel_data(struct drm_i915_private *dev_priv,
@@ -218,6 +233,11 @@ parse_lfp_panel_data(struct drm_i915_private *dev_priv,
 
 	panel_type = lvds_options->panel_type;
 
+	dev_priv->vbt.drrs_mode =
+		get_mode_by_paneltype(lvds_options->dps_panel_type_bits);
+	DRM_DEBUG_KMS("DRRS supported mode is : %s\n",
+			(dev_priv->vbt.drrs_mode == 0) ? "STATIC" : "SEAMLESS");
+
 	lvds_lfp_data = find_section(bdb, BDB_LVDS_LFP_DATA);
 	if (!lvds_lfp_data)
 		return;
@@ -488,6 +508,9 @@ parse_driver_features(struct drm_i915_private *dev_priv,
 
 	if (driver->dual_frequency)
 		dev_priv->render_reclock_avail = true;
+
+	dev_priv->vbt.intel_drrs_enabled = driver->intel_drrs_state;
+	DRM_DEBUG_KMS("DRRS State Enabled : %d\n", driver->intel_drrs_state);
 }
 
 static void
diff --git a/drivers/gpu/drm/i915/intel_bios.h b/drivers/gpu/drm/i915/intel_bios.h
index 287cc5a..8ac6e1e 100644
--- a/drivers/gpu/drm/i915/intel_bios.h
+++ b/drivers/gpu/drm/i915/intel_bios.h
@@ -202,6 +202,9 @@ struct bdb_general_features {
 #define DEVICE_PORT_DVOB	0x01
 #define DEVICE_PORT_DVOC	0x02
 
+/* Mask for DRRS / Panel Channel / SSC / BLT control bits extraction */
+#define MODE_MASK		0x3
+
 /* We used to keep this struct but without any version control. We should avoid
  * using it in the future, but it should be safe to keep using it in the old
  * code. */
@@ -293,6 +296,18 @@ struct bdb_lvds_options {
 	u8 lvds_edid:1;
 	u8 rsvd2:1;
 	u8 rsvd4;
+	/* LVDS Panel channel bits stored here */
+	u32 lvds_panel_channel_bits;
+	/* LVDS SSC (Spread Spectrum Clock) bits stored here. */
+	u16 ssc_bits;
+	u16 ssc_freq;
+	u16 ssc_ddt;
+	/* Panel color depth defined here */
+	u16 panel_color_depth;
+	/* LVDS panel type bits stored here */
+	u32 dps_panel_type_bits;
+	/* LVDS backlight control type bits stored here */
+	u32 blt_control_type_bits;
 } __attribute__((packed));
 
 /* LFP pointer table contains entries to the struct below */
@@ -462,6 +477,20 @@ struct bdb_driver_features {
 
 	u8 hdmi_termination;
 	u8 custom_vbt_version;
+	/* Driver features data block */
+	u16 intel_rmpm_state:1;
+	u16 intel_s2ddt_state:1;
+	u16 intel_dpst_state:1;
+	u16 intel_bltclt_state:1;
+	u16 intel_adb_state:1;
+	u16 intel_drrs_state:1;
+	u16 intel_grs_state:1;
+	u16 intel_gpmt_state:1;
+	u16 intel_tbt_state:1;
+	u16 psr_state:1;
+	u16 ips_state:1;
+	u16 reserved3:4;
+	u16 pc_feature_validity:1;
 } __attribute__((packed));
 
 #define EDP_18BPP	0
-- 
1.7.9.5

[PATCH 2/6] drm/i915: Parse EDID probed modes for DRRS support

[Vandana Kannan]

From: Pradeep Bhat <pradeep.bhat@intel.com>

This patch parses the eDP EDID probed_mode list and finds out the
lowest refresh rate supported for the resolution same as the
fixed_mode. It also checks the VBT fields to see if panel supports
seamless DRRS or not. Based on above data it marks whether eDP
panel supports seamless DRRS or not. This information is needed for
supporting seamless DRRS switch for certain power saving usecases.
This patch is tested by enabling the DRM logs and user should see
whether Seamless DRRS is supported or not. This feature is for PV2
and not PV1.

Signed-off-by: Pradeep Bhat <pradeep.bhat@intel.com>
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c  |   91 ++++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_drv.h |   35 +++++++++++++++
 2 files changed, 126 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 7619eae..46f202b 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3481,6 +3481,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
 	struct drm_display_mode *scan;
 	struct edid *edid;
 
+	intel_dp->drrs_state.is_drrs_supported = DRRS_NOT_SUPPORTED;
 	if (!is_edp(intel_dp))
 		return true;
 
@@ -3529,6 +3530,15 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
 		}
 	}
 
+	/**
+	 * Do the eDP DRRS support check here as we have valid EDID.
+	 * Parse the list of probed modes and find out if we can get
+	 * a mode with low refresh rate for resolution same as fixed_mode.
+	 */
+	if (fixed_mode && INTEL_INFO(dev)->gen >= 5)
+		intel_dp_find_drrs_lowclk(intel_dig_port,
+					intel_connector, fixed_mode);
+
 	/* fallback to VBT if available for eDP */
 	if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
 		fixed_mode = drm_mode_duplicate(dev,
@@ -3738,3 +3748,84 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
 		kfree(intel_connector);
 	}
 }
+
+static void
+intel_dp_drrs_modelist_create(struct intel_digital_port *intel_dig_port,
+				struct drm_display_mode *fixed_mode,
+				struct drm_display_mode *lowest_mode)
+{
+	struct intel_dp *intel_dp = &intel_dig_port->dp;
+
+	intel_dp->drrs_state.refresh_rate_array[DRRS_HIGH_RR] =
+							fixed_mode->vrefresh;
+	intel_dp->drrs_state.pixel_clock[DRRS_HIGH_RR] = fixed_mode->clock;
+
+	intel_dp->drrs_state.refresh_rate_array[DRRS_LOW_RR] =
+							lowest_mode->vrefresh;
+	intel_dp->drrs_state.pixel_clock[DRRS_LOW_RR] = lowest_mode->clock;
+}
+
+void
+intel_dp_find_drrs_lowclk(struct intel_digital_port *intel_dig_port,
+			     struct intel_connector *intel_connector,
+			     struct drm_display_mode *fixed_mode)
+{
+	struct drm_connector *connector = &intel_connector->base;
+	struct intel_dp *intel_dp = &intel_dig_port->dp;
+	struct intel_encoder *intel_encoder = &intel_dig_port->base;
+	struct drm_device *dev = intel_encoder->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_display_mode *scan, *temp_mode;
+	int downclock;
+
+	intel_dp->drrs_state.is_drrs_supported = DRRS_NOT_SUPPORTED;
+	/**
+	 * Check if PSR is supported by panel and enabled
+	 * if so then DRRS is reported as not supported for Haswell.
+	 */
+
+	if (INTEL_INFO(dev)->gen < 8 &&	intel_edp_is_psr_enabled(dev)) {
+		DRM_INFO("eDP panel is PSR enabled. Cannot support DRRS.\n");
+		return;
+	}
+
+	/* First check if DRRS is enabled from VBT struct */
+	if (!dev_priv->vbt.intel_drrs_enabled) {
+		DRM_INFO("VBT doesn't support DRRS.\n");
+		return;
+	}
+
+	/* Iterate the EDID probed_modes to get the Lowest refresh rate */
+	downclock = fixed_mode->clock;
+	temp_mode = fixed_mode;
+
+	list_for_each_entry(scan, &connector->probed_modes, head) {
+		if (scan->hdisplay == fixed_mode->hdisplay &&
+		    scan->hsync_start == fixed_mode->hsync_start &&
+		    scan->hsync_end == fixed_mode->hsync_end &&
+		    scan->htotal == fixed_mode->htotal &&
+		    scan->vdisplay == fixed_mode->vdisplay &&
+		    scan->vsync_start == fixed_mode->vsync_start &&
+		    scan->vsync_end == fixed_mode->vsync_end &&
+		    scan->vtotal == fixed_mode->vtotal) {
+			if (scan->clock < downclock) {
+				downclock = scan->clock;
+				temp_mode = scan;
+			}
+		}
+	}
+
+	/* Create a list of different DRRS Refresh rates for use later */
+	if (downclock < fixed_mode->clock &&
+	    dev_priv->vbt.drrs_mode == SEAMLESS_DRRS_SUPPORT) {
+		intel_dp_drrs_modelist_create(intel_dig_port, fixed_mode,
+						temp_mode);
+		intel_dp->drrs_state.is_drrs_supported =
+					dev_priv->vbt.drrs_mode;
+		intel_dp->drrs_state.drrs_refresh_rate_type = DRRS_HIGH_RR;
+		DRM_INFO("SEAMLESS DRRS supported for eDP panel.\n");
+	}
+
+	return;
+}
+
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 9d2624f..bd7964d 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -450,6 +450,36 @@ struct intel_hdmi {
 
 #define DP_MAX_DOWNSTREAM_PORTS		0x10
 
+/**
+ * This enum is used to indicate the DRRS support type.
+ * The values of the enum map 1-to-1 with the values from VBT.
+ */
+enum edp_panel_type {
+	DRRS_NOT_SUPPORTED = -1,
+	STATIC_DRRS_SUPPORT = 0,
+	SEAMLESS_DRRS_SUPPORT = 2
+};
+/**
+ * HIGH_RR is the highest eDP panel refresh rate read from EDID
+ * LOW_RR is the lowest eDP panel refresh rate found from EDID
+ * parsing for same resolution.
+ */
+enum edp_drrs_refresh_rate_type {
+	DRRS_HIGH_RR,
+	DRRS_LOW_RR,
+	DRRS_MAX_RR, /* RR count */
+};
+/**
+ * The drrs_info struct will represent the DRRS feature for eDP
+ * panel.
+ */
+struct drrs_info {
+	int is_drrs_supported;
+	int drrs_refresh_rate_type;
+	int refresh_rate_array[DRRS_MAX_RR];
+	int pixel_clock[DRRS_MAX_RR];
+};
+
 struct intel_dp {
 	uint32_t output_reg;
 	uint32_t aux_ch_ctl_reg;
@@ -475,6 +505,7 @@ struct intel_dp {
 	bool want_panel_vdd;
 	bool psr_setup_done;
 	struct intel_connector *attached_connector;
+	struct drrs_info drrs_state;
 };
 
 struct intel_digital_port {
@@ -789,6 +820,10 @@ int intel_overlay_put_image(struct drm_device *dev, void *data,
 int intel_overlay_attrs(struct drm_device *dev, void *data,
 			struct drm_file *file_priv);
 
+/* drrs */
+extern void intel_dp_find_drrs_lowclk(struct intel_digital_port *intel_dig_port,
+				      struct intel_connector *intel_connector,
+				      struct drm_display_mode *fixed_mode);
 
 /* intel_panel.c */
 int intel_panel_init(struct intel_panel *panel,
-- 
1.7.9.5

[PATCH 3/6] drm/i915: Add support for DRRS set property to switch RR

[Vandana Kannan]

From: Pradeep Bhat <pradeep.bhat@intel.com>

This patch provides a set_property interface for user space to
seamlessly switch between different DRRS refresh rates. The
patch creates the property only if seamless DRRS is supported.
It implements the support for computing Data & Link M/N for any
given Refresh Rate and programs the same in 2nd M/N/TU for
switching to different refresh rate dynamically using DRM set
property IOCTL. The PIPECONF_EDP_RR_MODE_SWITCH bit helps toggle
between alternate refresh rates programmed in 2nd M/N/TU registers.
The user space should use this property to switch to any required
refresh rate based on its policy. This feature enables user space
in acheiving better power savings for certain use cases. This
feature is for PV2 and not PV1.

Signed-off-by: Pradeep Bhat <pradeep.bhat@intel.com>
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |    1 +
 drivers/gpu/drm/i915/intel_dp.c  |  160 ++++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_drv.h |    6 ++
 3 files changed, 167 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3f303ba..d1f8cc7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3168,6 +3168,7 @@
 #define   PIPECONF_INTERLACED_DBL_ILK		(4 << 21) /* ilk/snb only */
 #define   PIPECONF_PFIT_PF_INTERLACED_DBL_ILK	(5 << 21) /* ilk/snb only */
 #define   PIPECONF_INTERLACE_MODE_MASK		(7 << 21)
+#define   PIPECONF_EDP_RR_MODE_SWITCH		(1 << 20)
 #define   PIPECONF_CXSR_DOWNCLOCK	(1<<16)
 #define   PIPECONF_COLOR_RANGE_SELECT	(1 << 13)
 #define   PIPECONF_BPC_MASK	(0x7 << 5)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 46f202b..ff156d2 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3118,6 +3118,12 @@ intel_dp_set_property(struct drm_connector *connector,
 	if (ret)
 		return ret;
 
+	if (is_edp(intel_dp) && property ==
+				intel_dp->drrs_state.seamless_drrs_property) {
+		intel_dp_set_drrs_state(connector->dev, val);
+		return 0;
+	}
+
 	if (property == dev_priv->force_audio_property) {
 		int i = val;
 		bool has_audio;
@@ -3300,6 +3306,9 @@ intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connect
 	intel_dp->color_range_auto = true;
 
 	if (is_edp(intel_dp)) {
+		if (intel_dp->drrs_state.is_drrs_supported !=
+							DRRS_NOT_SUPPORTED)
+			intel_dp_attach_drrs_properties(intel_dp, connector);
 		drm_mode_create_scaling_mode_property(connector->dev);
 		drm_object_attach_property(
 			&connector->base,
@@ -3820,6 +3829,7 @@ intel_dp_find_drrs_lowclk(struct intel_digital_port *intel_dig_port,
 	    dev_priv->vbt.drrs_mode == SEAMLESS_DRRS_SUPPORT) {
 		intel_dp_drrs_modelist_create(intel_dig_port, fixed_mode,
 						temp_mode);
+		mutex_init(&intel_dp->drrs_state.mutex);
 		intel_dp->drrs_state.is_drrs_supported =
 					dev_priv->vbt.drrs_mode;
 		intel_dp->drrs_state.drrs_refresh_rate_type = DRRS_HIGH_RR;
@@ -3829,3 +3839,153 @@ intel_dp_find_drrs_lowclk(struct intel_digital_port *intel_dig_port,
 	return;
 }
 
+void
+intel_dp_attach_drrs_properties(struct intel_dp *intel_dp,
+				struct drm_connector *connector)
+{
+	struct drm_device *dev = connector->dev;
+	struct drm_property *prop;
+	const struct drm_prop_enum_list seamless_drrs_names[] = {
+		{ intel_dp->drrs_state.refresh_rate_array[DRRS_HIGH_RR],
+								"high_rr"},
+		{ intel_dp->drrs_state.refresh_rate_array[DRRS_LOW_RR],
+								"low_rr"},
+		/**
+		 * add more entries if more DRRS RRs supported.
+		 * The no.of entries should be equal to
+		 * DRRS_MAX_RR.
+		 */
+	};
+
+	prop = intel_dp->drrs_state.seamless_drrs_property;
+	if (prop == NULL) {
+		prop = drm_property_create_enum(dev, 0,
+					"seamless_drrs",
+					seamless_drrs_names,
+					ARRAY_SIZE(seamless_drrs_names));
+		if (prop == NULL)
+			return;
+		intel_dp->drrs_state.seamless_drrs_property = prop;
+	}
+	drm_object_attach_property(&connector->base, prop,
+				intel_dp->drrs_state.refresh_rate_array[0]);
+}
+
+static void
+intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
+{
+	struct drm_device *dev = crtc->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	enum transcoder transcoder = crtc->config.cpu_transcoder;
+
+	if (INTEL_INFO(dev)->gen >= 5 && INTEL_INFO(dev)->gen < 8) {
+		I915_WRITE(PIPE_DATA_M2(transcoder),
+			   TU_SIZE(m_n->tu) | m_n->gmch_m);
+		I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
+		I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
+		I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
+	}
+	return;
+}
+
+void
+intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_mode_config *mode_config = &dev->mode_config;
+	struct intel_encoder *encoder;
+	struct intel_dp *intel_dp = NULL;
+	struct intel_crtc_config *config = NULL;
+	struct intel_crtc *intel_crtc = NULL;
+	struct intel_connector *intel_connector = NULL;
+	bool found_edp = false;
+	u32 reg, val;
+	int index = 0;
+
+	if (refresh_rate <= 0) {
+		DRM_INFO("Refresh rate should be positive non-zero.\n");
+		goto out;
+	}
+
+	list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
+		if (encoder->type == INTEL_OUTPUT_EDP) {
+			intel_dp = enc_to_intel_dp(&encoder->base);
+			intel_crtc = encoder->new_crtc;
+			if (!intel_crtc) {
+				DRM_INFO("DRRS: intel_crtc not initialized\n");
+				goto out;
+			}
+			config = &intel_crtc->config;
+			intel_connector = intel_dp->attached_connector;
+			found_edp = true;
+			break;
+		}
+	}
+
+	if (!found_edp) {
+		DRM_INFO("DRRS supported for eDP only.\n");
+		goto out;
+	}
+
+	if (intel_dp->drrs_state.is_drrs_supported < SEAMLESS_DRRS_SUPPORT) {
+		DRM_INFO("Seamless DRRS not supported.\n");
+		goto out;
+	}
+
+	for (; index < DRRS_MAX_RR; index++) {
+		if (intel_dp->drrs_state.refresh_rate_array[index] ==
+								refresh_rate)
+			break;
+	}
+
+	if (index >= DRRS_MAX_RR) {
+		DRM_INFO("Invalid refresh rate requested for DRRS.\n");
+		goto out;
+	}
+
+	if (index == intel_dp->drrs_state.drrs_refresh_rate_type) {
+		DRM_INFO("DRRS requested for previously set RR...ignoring\n");
+		goto out;
+	}
+
+	if (!intel_crtc->active) {
+		DRM_INFO("eDP encoder has been disabled. CRTC not Active\n");
+		goto out;
+	}
+
+	mutex_lock(&intel_dp->drrs_state.mutex);
+
+	intel_link_compute_m_n(config->pipe_bpp, intel_dp->lane_count,
+				intel_dp->drrs_state.pixel_clock[index],
+				config->port_clock,
+				&intel_dp->drrs_state.dp_m2_n2);
+
+	if (INTEL_INFO(dev)->gen >= 8)
+		intel_dp_set_m2_n2(intel_crtc, &intel_dp->drrs_state.dp_m2_n2);
+	else {
+		/* Haswell and below */
+		reg = PIPECONF(intel_crtc->config.cpu_transcoder);
+		val = I915_READ(reg);
+		if (index > DRRS_HIGH_RR) {
+			if ((val & PIPECONF_EDP_RR_MODE_SWITCH) != 0) {
+				val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
+				I915_WRITE(reg, val);
+			}
+			intel_dp_set_m2_n2(intel_crtc,
+				&intel_dp->drrs_state.dp_m2_n2);
+			val |= PIPECONF_EDP_RR_MODE_SWITCH;
+		} else
+			val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
+		I915_WRITE(reg, val);
+	}
+
+	intel_dp->drrs_state.drrs_refresh_rate_type = index;
+	DRM_INFO("eDP Refresh Rate set to : %dHz\n",
+			intel_dp->drrs_state.refresh_rate_array[index]);
+
+	mutex_unlock(&intel_dp->drrs_state.mutex);
+
+out:
+	return;
+}
+
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index bd7964d..7c22fcf 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -478,6 +478,9 @@ struct drrs_info {
 	int drrs_refresh_rate_type;
 	int refresh_rate_array[DRRS_MAX_RR];
 	int pixel_clock[DRRS_MAX_RR];
+	struct intel_link_m_n dp_m2_n2;
+	struct drm_property *seamless_drrs_property;
+	struct mutex mutex;
 };
 
 struct intel_dp {
@@ -824,6 +827,9 @@ int intel_overlay_attrs(struct drm_device *dev, void *data,
 extern void intel_dp_find_drrs_lowclk(struct intel_digital_port *intel_dig_port,
 				      struct intel_connector *intel_connector,
 				      struct drm_display_mode *fixed_mode);
+extern void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate);
+extern void intel_dp_attach_drrs_properties(struct intel_dp *intel_dp,
+					    struct drm_connector *connector);
 
 /* intel_panel.c */
 int intel_panel_init(struct intel_panel *panel,
-- 
1.7.9.5

[PATCH 4/6] drm/i915: Idleness detection for DRRS

[Vandana Kannan]

Adding support to detect display idleness by tracking page flip from
user space. Switch to low refresh rate is triggered after 2 seconds of
idleness. The delay is configurable. If there is a page flip or call to
update the plane, then high refresh rate is applied.
The feature is not used in dual-display mode.

Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
Signed-off-by: Pradeep Bhat <pradeep.bhat@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h      |   19 ++++++
 drivers/gpu/drm/i915/intel_display.c |   13 ++++
 drivers/gpu/drm/i915/intel_dp.c      |    9 +++
 drivers/gpu/drm/i915/intel_pm.c      |  113 ++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_sprite.c  |    3 +
 5 files changed, 157 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 98aac55..7d228db 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -670,6 +670,21 @@ struct i915_fbc {
 	} no_fbc_reason;
 };
 
+/* configure the number of secs the system must be idle
+ * before DRRS is enabled
+*/
+#define DRRS_IDLENESS_TIME 2000 /* in millisecs */
+
+struct i915_drrs {
+	struct intel_connector *connector;
+	struct intel_dp *dp;
+	struct intel_drrs_work {
+		struct delayed_work work;
+		struct drm_crtc *crtc;
+		int interval;
+	} *drrs_work;
+};
+
 struct i915_psr {
 	bool sink_support;
 	bool source_ok;
@@ -1347,6 +1362,7 @@ typedef struct drm_i915_private {
 	int num_plane;
 
 	struct i915_fbc fbc;
+	struct i915_drrs drrs;
 	struct intel_opregion opregion;
 	struct intel_vbt_data vbt;
 
@@ -2365,6 +2381,9 @@ extern void intel_modeset_setup_hw_state(struct drm_device *dev,
 extern void i915_redisable_vga(struct drm_device *dev);
 extern bool intel_fbc_enabled(struct drm_device *dev);
 extern void intel_disable_fbc(struct drm_device *dev);
+extern void intel_init_drrs_idleness_detection(struct drm_device *dev,
+		struct intel_connector *connector, struct intel_dp *dp);
+extern void intel_update_drrs(struct drm_device *dev, bool update);
 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
 extern void intel_init_pch_refclk(struct drm_device *dev);
 extern void gen6_set_rps(struct drm_device *dev, u8 val);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f34252d..c5c1c52 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2372,6 +2372,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
 	}
 
 	intel_update_fbc(dev);
+	intel_update_drrs(dev, true);
 	intel_edp_psr_update(dev);
 	mutex_unlock(&dev->struct_mutex);
 
@@ -3520,6 +3521,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
 
 	mutex_lock(&dev->struct_mutex);
 	intel_update_fbc(dev);
+	intel_update_drrs(dev, true);
 	mutex_unlock(&dev->struct_mutex);
 
 	for_each_encoder_on_crtc(dev, crtc, encoder)
@@ -3561,6 +3563,7 @@ static void haswell_crtc_enable_planes(struct drm_crtc *crtc)
 
 	mutex_lock(&dev->struct_mutex);
 	intel_update_fbc(dev);
+	intel_update_drrs(dev, true);
 	mutex_unlock(&dev->struct_mutex);
 }
 
@@ -3767,6 +3770,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
 
 	mutex_lock(&dev->struct_mutex);
 	intel_update_fbc(dev);
+	intel_update_drrs(dev, true);
 	mutex_unlock(&dev->struct_mutex);
 }
 
@@ -3814,6 +3818,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
 
 	mutex_lock(&dev->struct_mutex);
 	intel_update_fbc(dev);
+	intel_update_drrs(dev, true);
 	mutex_unlock(&dev->struct_mutex);
 }
 
@@ -7938,6 +7943,11 @@ static void intel_unpin_work_fn(struct work_struct *__work)
 	drm_gem_object_unreference(&work->old_fb_obj->base);
 
 	intel_update_fbc(dev);
+
+	/* disable current DRRS work scheduled and restart
+	 * to push work by another x seconds
+	 */
+	intel_update_drrs(dev, true);
 	mutex_unlock(&dev->struct_mutex);
 
 	BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
@@ -8377,6 +8387,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
 		goto cleanup_pending;
 
 	intel_disable_fbc(dev);
+	intel_update_drrs(dev, false);
 	intel_mark_fb_busy(obj, NULL);
 	mutex_unlock(&dev->struct_mutex);
 
@@ -10986,6 +10997,8 @@ void intel_modeset_cleanup(struct drm_device *dev)
 
 	intel_disable_fbc(dev);
 
+	intel_update_drrs(dev, false);
+
 	intel_disable_gt_powersave(dev);
 
 	ironlake_teardown_rc6(dev);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index ff156d2..ef7c50d 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3219,11 +3219,18 @@ void intel_dp_encoder_destroy(struct drm_encoder *encoder)
 	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 	struct intel_dp *intel_dp = &intel_dig_port->dp;
 	struct drm_device *dev = intel_dp_to_dev(intel_dp);
+	struct drm_i915_private *dev_priv = dev->dev_private;
 
 	i2c_del_adapter(&intel_dp->adapter);
 	drm_encoder_cleanup(encoder);
 	if (is_edp(intel_dp)) {
 		cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
+		/* DRRS cleanup */
+		if (intel_dp->drrs_state.is_drrs_supported
+					== SEAMLESS_DRRS_SUPPORT) {
+			kfree(dev_priv->drrs.drrs_work);
+			dev_priv->drrs.drrs_work = NULL;
+		}
 		mutex_lock(&dev->mode_config.mutex);
 		ironlake_panel_vdd_off_sync(intel_dp);
 		mutex_unlock(&dev->mode_config.mutex);
@@ -3829,6 +3836,8 @@ intel_dp_find_drrs_lowclk(struct intel_digital_port *intel_dig_port,
 	    dev_priv->vbt.drrs_mode == SEAMLESS_DRRS_SUPPORT) {
 		intel_dp_drrs_modelist_create(intel_dig_port, fixed_mode,
 						temp_mode);
+		intel_init_drrs_idleness_detection(dev,
+						intel_connector, intel_dp);
 		mutex_init(&intel_dp->drrs_state.mutex);
 		intel_dp->drrs_state.is_drrs_supported =
 					dev_priv->vbt.drrs_mode;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 09ac9e7..5297018 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -608,6 +608,119 @@ out_disable:
 	i915_gem_stolen_cleanup_compression(dev);
 }
 
+static void intel_drrs_work_fn(struct work_struct *__work)
+{
+	struct intel_drrs_work *work =
+		container_of(to_delayed_work(__work),
+			     struct intel_drrs_work, work);
+	struct drm_device *dev = work->crtc->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	intel_dp_set_drrs_state(work->crtc->dev,
+		dev_priv->drrs.dp->drrs_state.refresh_rate_array[DRRS_LOW_RR]);
+}
+
+static void intel_cancel_drrs_work(struct drm_i915_private *dev_priv)
+{
+	if (dev_priv->drrs.drrs_work == NULL)
+		return;
+
+	DRM_DEBUG_KMS("cancelling pending DRRS enable\n");
+
+	cancel_delayed_work_sync(&dev_priv->drrs.drrs_work->work);
+}
+
+static void intel_enable_drrs(struct drm_crtc *crtc)
+{
+	struct drm_device *dev = crtc->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	if (dev_priv->drrs.dp->drrs_state.drrs_refresh_rate_type
+							!= DRRS_LOW_RR) {
+		dev_priv->drrs.drrs_work->crtc = crtc;
+
+		/* Delay the actual enabling to let pageflipping cease and the
+		 * display to settle before starting DRRS
+		 */
+		schedule_delayed_work(&dev_priv->drrs.drrs_work->work,
+			msecs_to_jiffies(dev_priv->drrs.drrs_work->interval));
+	}
+}
+
+/**
+ * intel_update_drrs - enable/disable DRRS as needed
+ * @dev: the drm_device
+ * @update: if set to true, cancel current work and schedule new work.
+ *	    if set to false, cancel current work and disable DRRS.
+*/
+void intel_update_drrs(struct drm_device *dev, bool update)
+{
+	struct drm_crtc *crtc = NULL, *tmp_crtc;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	/* if drrs.connector is NULL, then drrs_init did not get called.
+	 * which means DRRS is not supported.
+	 */
+	if (dev_priv->drrs.connector == NULL) {
+		DRM_INFO("DRRS is not supported.\n");
+		return;
+	}
+
+	intel_cancel_drrs_work(dev_priv);
+
+	list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
+		if (tmp_crtc != NULL && intel_crtc_active(tmp_crtc) &&
+		    to_intel_crtc(tmp_crtc)->primary_enabled) {
+			if (crtc) {
+				DRM_DEBUG_KMS(
+				"more than one pipe active, disabling DRRS\n");
+				update = false;
+				break;
+			}
+			crtc = tmp_crtc;
+		}
+	}
+
+	if (crtc == NULL) {
+		DRM_INFO("DRRS: crtc not initialized\n");
+		return;
+	}
+
+	/* as part of disable DRRS, reset refresh rate to HIGH_RR */
+	if (dev_priv->drrs.dp->drrs_state.drrs_refresh_rate_type
+							== DRRS_LOW_RR)
+		intel_dp_set_drrs_state(dev,
+			dev_priv->drrs.dp->drrs_state.
+			refresh_rate_array[DRRS_HIGH_RR]);
+
+	if (update == true) {
+		/* re-enable idleness detection */
+		intel_enable_drrs(crtc);
+	}
+}
+
+void intel_init_drrs_idleness_detection(struct drm_device *dev,
+					struct intel_connector *connector,
+					struct intel_dp *dp)
+{
+	struct intel_drrs_work *work;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	work = kzalloc(sizeof(struct intel_drrs_work), GFP_KERNEL);
+	if (!work) {
+		DRM_ERROR("Failed to allocate DRRS work structure\n");
+		return;
+	}
+
+	dev_priv->drrs.connector = connector;
+	dev_priv->drrs.dp = dp;
+
+	work->interval = DRRS_IDLENESS_TIME;
+	INIT_DELAYED_WORK(&work->work, intel_drrs_work_fn);
+
+	dev_priv->drrs.drrs_work = work;
+}
+
 static void i915_pineview_get_mem_freq(struct drm_device *dev)
 {
 	drm_i915_private_t *dev_priv = dev->dev_private;
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 8afaad6..e7ff21b 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -542,6 +542,7 @@ intel_enable_primary(struct drm_crtc *crtc)
 
 	mutex_lock(&dev->struct_mutex);
 	intel_update_fbc(dev);
+	intel_update_drrs(dev, true);
 	mutex_unlock(&dev->struct_mutex);
 }
 
@@ -561,6 +562,8 @@ intel_disable_primary(struct drm_crtc *crtc)
 	mutex_lock(&dev->struct_mutex);
 	if (dev_priv->fbc.plane == intel_crtc->plane)
 		intel_disable_fbc(dev);
+
+	intel_update_drrs(dev, false);
 	mutex_unlock(&dev->struct_mutex);
 
 	/*
-- 
1.7.9.5

[PATCH 5/6] drm/i915: Support to read DMRRS field from VBT structure

[Vandana Kannan]

From: Pradeep Bhat <pradeep.bhat@intel.com>

This patch provides necessary support to read the Dynamic Media
Refresh Rate (DMRRS) field from VBT. This information will be used
by DRRS feature to create additional refresh rates needed for
media use cases like video playback. This patch is tested by enabling
DRM Logs. This feature is for PV2 and not PV1.

Signed-off-by: Pradeep Bhat <pradeep.bhat@intel.com>
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h   |    2 ++
 drivers/gpu/drm/i915/intel_bios.c |    4 +++-
 drivers/gpu/drm/i915/intel_bios.h |    4 +++-
 3 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7d228db..541791c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1151,6 +1151,8 @@ struct intel_vbt_data {
 	int drrs_mode;
 	/* DRRS enabled or disabled in VBT */
 	bool intel_drrs_enabled;
+	/* Dynamic media refresh rate enable/disable */
+	bool intel_dmrrs_enabled;
 
 	/* eDP */
 	int edp_rate;
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 4aaa0f9..c65dc7a 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -510,7 +510,9 @@ parse_driver_features(struct drm_i915_private *dev_priv,
 		dev_priv->render_reclock_avail = true;
 
 	dev_priv->vbt.intel_drrs_enabled = driver->intel_drrs_state;
-	DRM_DEBUG_KMS("DRRS State Enabled : %d\n", driver->intel_drrs_state);
+	dev_priv->vbt.intel_dmrrs_enabled = driver->dmrrs_state;
+	DRM_DEBUG_KMS("DRRS State Enabled : %d DMRRS: %d\n",
+				driver->intel_drrs_state, driver->dmrrs_state);
 }
 
 static void
diff --git a/drivers/gpu/drm/i915/intel_bios.h b/drivers/gpu/drm/i915/intel_bios.h
index 8ac6e1e..56b24b7 100644
--- a/drivers/gpu/drm/i915/intel_bios.h
+++ b/drivers/gpu/drm/i915/intel_bios.h
@@ -489,7 +489,9 @@ struct bdb_driver_features {
 	u16 intel_tbt_state:1;
 	u16 psr_state:1;
 	u16 ips_state:1;
-	u16 reserved3:4;
+	u16 dfps_state:1;
+	u16 dmrrs_state:1;
+	u16 reserved3:2;
 	u16 pc_feature_validity:1;
 } __attribute__((packed));
 
-- 
1.7.9.5

[PATCH 6/6] drm/i915: Adding support for DMRRS for media playback

[Vandana Kannan]

From: Pradeep Bhat <pradeep.bhat@intel.com>

This patch provides support for two additional DRRS refresh rates
which will be used for video playback use cases. When the playback
is at 24fps, player can indicate the DRRS to set 48Hz. Similarly
for playback of 25fps DRRS 50Hz is used. This helps in better
power saving in active use cases like video playback. This feature
is for PV2 and not for PV1.

Signed-off-by: Pradeep Bhat <pradeep.bhat@intel.com>
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c  |   36 ++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_drv.h |    7 +++++++
 2 files changed, 43 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index ef7c50d..673907c 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3765,12 +3765,21 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
 	}
 }
 
+static int
+get_drrs_pclk(struct drm_display_mode *fixed_mode, int refresh_rate)
+{
+	return (refresh_rate * fixed_mode->htotal * fixed_mode->vtotal) / 1000;
+}
+
 static void
 intel_dp_drrs_modelist_create(struct intel_digital_port *intel_dig_port,
 				struct drm_display_mode *fixed_mode,
 				struct drm_display_mode *lowest_mode)
 {
 	struct intel_dp *intel_dp = &intel_dig_port->dp;
+	struct intel_encoder *intel_encoder = &intel_dig_port->base;
+	struct drm_device *dev = intel_encoder->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
 
 	intel_dp->drrs_state.refresh_rate_array[DRRS_HIGH_RR] =
 							fixed_mode->vrefresh;
@@ -3779,6 +3788,29 @@ intel_dp_drrs_modelist_create(struct intel_digital_port *intel_dig_port,
 	intel_dp->drrs_state.refresh_rate_array[DRRS_LOW_RR] =
 							lowest_mode->vrefresh;
 	intel_dp->drrs_state.pixel_clock[DRRS_LOW_RR] = lowest_mode->clock;
+
+	/* Check if DMRRS is supported and create additional entries */
+	if (dev_priv->vbt.intel_dmrrs_enabled) {
+		if (lowest_mode->vrefresh < MEDIA_DMRRS_FREQ_2) {
+			intel_dp->drrs_state.refresh_rate_array[DRRS_50HZ_RR] =
+						MEDIA_DMRRS_FREQ_1;
+			intel_dp->drrs_state.pixel_clock[DRRS_50HZ_RR] =
+						get_drrs_pclk(fixed_mode,
+						MEDIA_DMRRS_FREQ_1);
+			intel_dp->drrs_state.refresh_rate_array[DRRS_48HZ_RR] =
+						MEDIA_DMRRS_FREQ_2;
+			intel_dp->drrs_state.pixel_clock[DRRS_48HZ_RR] =
+						get_drrs_pclk(fixed_mode,
+						MEDIA_DMRRS_FREQ_2);
+		} else if (lowest_mode->vrefresh < MEDIA_DMRRS_FREQ_1) {
+			intel_dp->drrs_state.refresh_rate_array[DRRS_50HZ_RR] =
+						MEDIA_DMRRS_FREQ_1;
+			intel_dp->drrs_state.pixel_clock[DRRS_50HZ_RR] =
+						get_drrs_pclk(fixed_mode,
+						MEDIA_DMRRS_FREQ_1);
+		}
+	} else
+		DRM_INFO("DMRRS not supported.\n");
 }
 
 void
@@ -3859,6 +3891,10 @@ intel_dp_attach_drrs_properties(struct intel_dp *intel_dp,
 								"high_rr"},
 		{ intel_dp->drrs_state.refresh_rate_array[DRRS_LOW_RR],
 								"low_rr"},
+		{ intel_dp->drrs_state.refresh_rate_array[DRRS_50HZ_RR],
+								"50hz_rr"},
+		{ intel_dp->drrs_state.refresh_rate_array[DRRS_48HZ_RR],
+								"48hz_rr"},
 		/**
 		 * add more entries if more DRRS RRs supported.
 		 * The no.of entries should be equal to
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 7c22fcf..f0f944f 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -451,6 +451,11 @@ struct intel_hdmi {
 #define DP_MAX_DOWNSTREAM_PORTS		0x10
 
 /**
++ * Media refresh rates for dynamic switching
++ */
+#define MEDIA_DMRRS_FREQ_1 50
+#define MEDIA_DMRRS_FREQ_2 48
+/**
  * This enum is used to indicate the DRRS support type.
  * The values of the enum map 1-to-1 with the values from VBT.
  */
@@ -467,6 +472,8 @@ enum edp_panel_type {
 enum edp_drrs_refresh_rate_type {
 	DRRS_HIGH_RR,
 	DRRS_LOW_RR,
+	DRRS_50HZ_RR,
+	DRRS_48HZ_RR,
 	DRRS_MAX_RR, /* RR count */
 };
 /**
-- 
1.7.9.5

Re: [PATCH 0/6] Enabling DRRS support in the kernel

[Daniel Vetter]

On Tue, Nov 19, 2013 at 11:36:58AM +0530, Vandana Kannan wrote:
> Dynamic Refresh Rate Switching (DRRS) is a power conservation feature which     
> enables switching between low and high refresh rates based on the usage         
> scenario. This feature is applicable for internal eDP panel. Indication that    
> the panel can support DRRS is given by the panel EDID, which would list         
> multiple refresh rates for one resolution.                                      
> DRRS is of 2 types -                                                            
> Static DRRS involves execution of the entire mode set sequence to switch        
> between refresh rate.                                                           
> seamless DRRS involves refresh rate switching during runtime without any        
> blanking effect/mode set.                                                       
> The vendor fills in a VBT field indicating static/seamless DRRS based on the    
> panel spec. This information is needed to enable seamless DRRS in kernel.       
> The patch series supports idleness detection in display i915 driver and switch  
> to low refresh rate. It also provides set_property API for user space to         
> request for different refresh rates for active use cases like video playback    
> at 48/50 Hz.       
> 
> 
> Pradeep Bhat (5):
>   drm/i915: Adding VBT fields to support eDP DRRS feature
>   drm/i915: Parse EDID probed modes for DRRS support
>   drm/i915: Add support for DRRS set property to switch RR
>   drm/i915: Support to read DMRRS field from VBT structure
>   drm/i915: Adding support for DMRRS for media playback
> 
> Vandana Kannan (1):
>   drm/i915: Idleness detection for DRRS

My apologies for delaying my high-level maintainer review for so long -
there's been a bit a firedrill around here so it took a while to write it
all down.

Overall a nice patch series, but I think we need to shuffle a few things
around to better align with some of the longer-term driver architecture
reworks and goals:

- You add another copypaste of the code to deduce the reduced clock from
  the edid to intel_dp.c. Imo it's better to add that to intel_panel.c to
  struct intel_panel - we already track the panel fixed mode in there, so
  this would naturally fit.

- Imo we should track the reduced clock in the pipe config and also
  cross-check it in the state checker. That will lead to a bit of fun on
  bdw, so we need to special case the checker there so that it only checks
  that the clock matches either of the possible clocks.

  For this we need a bool downclock_available in struct intel_crtc_config
  and a 2nd set of m_n values, both set in the compute_config function for
  DP outputs.

  For consistency it'd be nice to at least move the downclock_available
  logic for lvds also over to that. But since we first need to clean up
  the dpll handling to make lvds downclocking sane that's imo not really a
  priority at all.

  The entire point behind all this pipe state tracking is to make sure we
  don't miss anything when fastbooting.

- The connector attribute is imo the wrong interface - userspace already
  supplies a mode attribute with dotclock to SetCrtc. Imo we simply need
  to fix up our fixed_mode logic (preferrably as a neat helper in
  intel_panel.c) to select the right one of the availabel downclocks, even
  when upscaling.

  The downside for now is that this will result in flickering. But we need
  a real flicker-free fast-update-path in our modeset code anyway to make
  fastboot happen for real. And a few other cool things. I'll increase
  the pain a bit in the hope that this moves forward again, so no quick
  hack please (even if it's very simple to do in the case of drrs).

- Finally a quick testcase which iterates through all the downclock modes
  in kms_flip - together with the cross-checking and all the vblank
  timing tests we already have that should give us solid test coverage. To
  keep test runtimes reasonable I think just a pageflipping test with time
  checking is more than enough.

Cheers, Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 0/6] Enabling DRRS support in the kernel

[Kannan, Vandana]

Hi Daniel,

	Thank you for your inputs. Please read our response below and let us know your opinion.

 - You add another copypaste of the code to deduce the reduced clock from
   the edid to intel_dp.c. Imo it's better to add that to intel_panel.c to
   struct intel_panel - we already track the panel fixed mode in there, so
   this would naturally fit.
	[Pradeep/Vandana] We will work to move the piece of code to deduce reduced clock from EDID to intel_panel.c. However, we will be making this change only for eDP at this point in time, and will work to rearrange the same for LVDS a little later. 

 - Imo we should track the reduced clock in the pipe config and also
   cross-check it in the state checker. That will lead to a bit of fun on
   bdw, so we need to special case the checker there so that it only checks
   that the clock matches either of the possible clocks.
 
   For this we need a bool downclock_available in struct intel_crtc_config
   and a 2nd set of m_n values, both set in the compute_config function for
   DP outputs.
	[Vandana/Pradeep]	Computing the 2nd set of M_N values in compute_config() for the  lowest refresh rate available can done. But in case of the use case of media playback at 50/48 Hz, which we have kept in mind during design/implementation, would mean that M_N values have to be computed initially and kept for all different refresh rates possible. The current implementation gives the flexibility of computing M_N as and when required by user space. If it is ok to keep an array of pre computed M_N values for different Refresh rates computed at intel_dp_compute_config then we could do this. Kindly let us know your opinion.
 
   For consistency it'd be nice to at least move the downclock_available
   logic for lvds also over to that. But since we first need to clean up
   the dpll handling to make lvds downclocking sane that's imo not really a
   priority at all.
	[Vandana/Pradeep]As mentioned above we will consider this on lower priority and not as part of this patch series.
 
   The entire point behind all this pipe state tracking is to make sure we
   don't miss anything when fastbooting.
 
 - The connector attribute is imo the wrong interface - userspace already
   supplies a mode attribute with dotclock to SetCrtc. Imo we simply need
   to fix up our fixed_mode logic (preferrably as a neat helper in
   intel_panel.c) to select the right one of the availabel downclocks, even
   when upscaling.
 
   The downside for now is that this will result in flickering. But we need
   a real flicker-free fast-update-path in our modeset code anyway to make
   fastboot happen for real. And a few other cool things. I'll increase
   the pain a bit in the hope that this moves forward again, so no quick
   hack please (even if it's very simple to do in the case of drrs).
	[Vandana/Pradeep]	This patch series is for seamless DRRS support and has to be a separate path from mode set as we just toggle the PIPE_CONF_RR_SWTICH for seamless RR transition without flicker. Complete modeset using setCrtc will result in partial blanking or flicker. We are not implementing fast boot as part of this series. 
Most eDP panels today which support multiple refresh rates, support seamless DRRS. This means that hardware capability is made use of by toggling a bit in pipe config to switch between refresh rates on the fly. The patch series is aimed to take advantage of this capability to switch refresh rates based on idleness or video playback requirement. Hence, we chose the connector attribute/ set property path. 
Also in order to support the Media refresh rates of 50/48 we thought it incorrect to populate those modes in probed_mode list as those values are not from the EDID. So in order for User space to know the media refresh rates supported we have exposed a set_property interface which makes User space aware of these media refresh rates. Also we do not intend to do a complete mode set on media use cases in which case we think using setCrtc is not needed. Using setCrtc will invariably result in intermittant blanking or flicker which cannot be avoided, and gives undesirable effect during playback. 
Seamless DRRS doesn't need a complete modeset and hence no flicker or temporary blanking. Changing the toggle RR bit in PIPE_CONF is faster. Also since BDW has only single M/N/TU register the current code takes care of it easily. Kindly let us know your opinion. Since Seamless DRRS for eDP is separate path from modeset we can keep the connector property attribute as it is.
 
 - Finally a quick testcase which iterates through all the downclock modes
   in kms_flip - together with the cross-checking and all the vblank
   timing tests we already have that should give us solid test coverage. To
   keep test runtimes reasonable I think just a pageflipping test with time
   checking is more than enough.
	[Vandana/Pradeep]We will look into this.

Thanks,
Vandana

 -----Original Message-----
 From: Daniel Vetter [mailto:daniel.vetter@ffwll.ch] On Behalf Of Daniel Vetter
 Sent: Tuesday, November 26, 2013 11:57 PM
 To: Kannan, Vandana
 Cc: intel-gfx@lists.freedesktop.org
 Subject: Re: [Intel-gfx] [PATCH 0/6] Enabling DRRS support in the kernel
 
 On Tue, Nov 19, 2013 at 11:36:58AM +0530, Vandana Kannan wrote:
 > Dynamic Refresh Rate Switching (DRRS) is a power conservation feature which
 > enables switching between low and high refresh rates based on the usage
 > scenario. This feature is applicable for internal eDP panel. Indication that
 > the panel can support DRRS is given by the panel EDID, which would list
 > multiple refresh rates for one resolution.
 > DRRS is of 2 types -
 > Static DRRS involves execution of the entire mode set sequence to switch
 > between refresh rate.
 > seamless DRRS involves refresh rate switching during runtime without any
 > blanking effect/mode set.
 > The vendor fills in a VBT field indicating static/seamless DRRS based on the
 > panel spec. This information is needed to enable seamless DRRS in kernel.
 > The patch series supports idleness detection in display i915 driver and switch
 > to low refresh rate. It also provides set_property API for user space to
 > request for different refresh rates for active use cases like video playback
 > at 48/50 Hz.
 >
 >
 > Pradeep Bhat (5):
 >   drm/i915: Adding VBT fields to support eDP DRRS feature
 >   drm/i915: Parse EDID probed modes for DRRS support
 >   drm/i915: Add support for DRRS set property to switch RR
 >   drm/i915: Support to read DMRRS field from VBT structure
 >   drm/i915: Adding support for DMRRS for media playback
 >
 > Vandana Kannan (1):
 >   drm/i915: Idleness detection for DRRS
 
 My apologies for delaying my high-level maintainer review for so long - there's been a bit a
 firedrill around here so it took a while to write it all down.
 
 Overall a nice patch series, but I think we need to shuffle a few things around to better
 align with some of the longer-term driver architecture reworks and goals:
 
 - You add another copypaste of the code to deduce the reduced clock from
   the edid to intel_dp.c. Imo it's better to add that to intel_panel.c to
   struct intel_panel - we already track the panel fixed mode in there, so
   this would naturally fit.
 
 - Imo we should track the reduced clock in the pipe config and also
   cross-check it in the state checker. That will lead to a bit of fun on
   bdw, so we need to special case the checker there so that it only checks
   that the clock matches either of the possible clocks.
 
   For this we need a bool downclock_available in struct intel_crtc_config
   and a 2nd set of m_n values, both set in the compute_config function for
   DP outputs.
 
   For consistency it'd be nice to at least move the downclock_available
   logic for lvds also over to that. But since we first need to clean up
   the dpll handling to make lvds downclocking sane that's imo not really a
   priority at all.
 
   The entire point behind all this pipe state tracking is to make sure we
   don't miss anything when fastbooting.
 
 - The connector attribute is imo the wrong interface - userspace already
   supplies a mode attribute with dotclock to SetCrtc. Imo we simply need
   to fix up our fixed_mode logic (preferrably as a neat helper in
   intel_panel.c) to select the right one of the availabel downclocks, even
   when upscaling.
 
   The downside for now is that this will result in flickering. But we need
   a real flicker-free fast-update-path in our modeset code anyway to make
   fastboot happen for real. And a few other cool things. I'll increase
   the pain a bit in the hope that this moves forward again, so no quick
   hack please (even if it's very simple to do in the case of drrs).
 
 - Finally a quick testcase which iterates through all the downclock modes
   in kms_flip - together with the cross-checking and all the vblank
   timing tests we already have that should give us solid test coverage. To
   keep test runtimes reasonable I think just a pageflipping test with time
   checking is more than enough.
 
 Cheers, Daniel
 --
 Daniel Vetter
 Software Engineer, Intel Corporation
 +41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 0/6] Enabling DRRS support in the kernel

[Daniel Vetter]

On Thu, Nov 28, 2013 at 10:22:59AM +0000, Kannan, Vandana wrote:
> Hi Daniel,
> 
> 	Thank you for your inputs. Please read our response below and let us know your opinion.

Can you please switch to a mail client that does proper quoting? It makes
reading your response a bit hard - I've fixed it up here quickly.


> 
>> - You add another copypaste of the code to deduce the reduced clock from
>>   the edid to intel_dp.c. Imo it's better to add that to intel_panel.c to
>>   struct intel_panel - we already track the panel fixed mode in there, so
>>   this would naturally fit.

>[Pradeep/Vandana] We will work to move the piece of code to deduce
>reduced clock from EDID to intel_panel.c. However, we will be
>making this change only for eDP at this point in time, and will
>work to rearrange the same for LVDS a little later. 

On my quick readthrough of your code it looked like it's identical code,
so two patches (first to extract the code from lvds, 2nd to use in in the
dp code) look like the sane choice. Just moving the place around where you
add the new copy doesn't help that much.

>> - Imo we should track the reduced clock in the pipe config and also
>>   cross-check it in the state checker. That will lead to a bit of fun on
>>   bdw, so we need to special case the checker there so that it only checks
>>   that the clock matches either of the possible clocks.
>> 
>>   For this we need a bool downclock_available in struct intel_crtc_config
>>   and a 2nd set of m_n values, both set in the compute_config function for
>>   DP outputs.
> 	[Vandana/Pradeep]	Computing the 2nd set of M_N values in
> 	compute_config() for the  lowest refresh rate available can done.
> 	But in case of the use case of media playback at 50/48 Hz, which
> 	we have kept in mind during design/implementation, would mean that
> 	M_N values have to be computed initially and kept for all
> 	different refresh rates possible. The current implementation gives
> 	the flexibility of computing M_N as and when required by user
> 	space. If it is ok to keep an array of pre computed M_N values for
> 	different Refresh rates computed at intel_dp_compute_config then
> 	we could do this. Kindly let us know your opinion.

Imo the pipe config should only contain the low/normal frequencies for
automatic switching. After all the switching should be transparent to
userspace since we're never in the lowfreq mode when there's activity.

>>   For consistency it'd be nice to at least move the downclock_available
>>   logic for lvds also over to that. But since we first need to clean up
>>   the dpll handling to make lvds downclocking sane that's imo not really a
>>   priority at all.
> 	[Vandana/Pradeep]As mentioned above we will consider this on lower
> 	priority and not as part of this patch series.

Yeah, like I've said this is out of scope. Switching the downclock_avail
bool though should simplify things a bit, so I'd include that.

>>   The entire point behind all this pipe state tracking is to make sure we
>>   don't miss anything when fastbooting.
>> 
>> - The connector attribute is imo the wrong interface - userspace already
>>   supplies a mode attribute with dotclock to SetCrtc. Imo we simply need
>>   to fix up our fixed_mode logic (preferrably as a neat helper in
>>   intel_panel.c) to select the right one of the availabel downclocks, even
>>   when upscaling.
>> 
>>   The downside for now is that this will result in flickering. But we need
>>   a real flicker-free fast-update-path in our modeset code anyway to make
>>   fastboot happen for real. And a few other cool things. I'll increase
>>   the pain a bit in the hope that this moves forward again, so no quick
>>   hack please (even if it's very simple to do in the case of drrs).
> 	[Vandana/Pradeep]	This patch series is for seamless DRRS
> 	support and has to be a separate path from mode set as we just
> 	toggle the PIPE_CONF_RR_SWTICH for seamless RR transition without
> 	flicker. Complete modeset using setCrtc will result in partial
> 	blanking or flicker. We are not implementing fast boot as part of
> 	this series.  Most eDP panels today which support multiple refresh
> 	rates, support seamless DRRS. This means that hardware capability
> 	is made use of by toggling a bit in pipe config to switch between
> 	refresh rates on the fly. The patch series is aimed to take
> 	advantage of this capability to switch refresh rates based on
> 	idleness or video playback requirement. Hence, we chose the
> 	connector attribute/ set property path.  Also in order to support
> 	the Media refresh rates of 50/48 we thought it incorrect to
> 	populate those modes in probed_mode list as those values are not
> 	from the EDID. So in order for User space to know the media
> 	refresh rates supported we have exposed a set_property interface
> 	which makes User space aware of these media refresh rates. Also we
> 	do not intend to do a complete mode set on media use cases in
> 	which case we think using setCrtc is not needed. Using setCrtc
> 	will invariably result in intermittant blanking or flicker which
> 	cannot be avoided, and gives undesirable effect during playback.
> 	Seamless DRRS doesn't need a complete modeset and hence no flicker
> 	or temporary blanking. Changing the toggle RR bit in PIPE_CONF is
> 	faster. Also since BDW has only single M/N/TU register the current
> 	code takes care of it easily. Kindly let us know your opinion.
> 	Since Seamless DRRS for eDP is separate path from modeset we can
> 	keep the connector property attribute as it is.

First the technical stuff:

- Adding the additional modes to the mode list is imo totally ok and as
  the design intents. We are already adding other modes from the vbt here
  if those are available. The only restriction is that the kernel may not
  add modes which don't work. But as long as the vbt tells us that 48Hz
  will work we can (and imo should) use it.

- Second changing the frequency changes the refresh rate. Atm both our
  userspace and the kernel support code assume that this can only be done
  through a SetCrtc call. So adjusting the dotclock is actually the right
  interface and we don't need any additional property.

Now the more political stuff:

- We have the long-term goal of solid fastboot support. We've the designed
  we've picked that actually means 95% effort to get flicker-free SetCrtc
  going and 5% actual code for fastboot. We're not there yet, there's only
  a preview available which is disabled by default and uses a few hacks.
  But generally all features that are relevant need to use the new
  infrastructure and help move things forward.

- Upstream has a time horizon of 5-10 years for the kernel/userspace
  interface. Which means quick hacks are not allowed. And in my opinion
  your property is a quick hack, which nicely simplified the
  implementation.

So in short I know that my request extends the scope of your patches. But
upstream also imposes differing constraints than a product tree.

>> - Finally a quick testcase which iterates through all the downclock modes
>>   in kms_flip - together with the cross-checking and all the vblank
>>   timing tests we already have that should give us solid test coverage. To
>>   keep test runtimes reasonable I think just a pageflipping test with time
>>   checking is more than enough.
>	[Vandana/Pradeep]We will look into this.

Good. Decent test case coverage with i-g-t tests is a requirement for
getting new features in. I've recently documented the reasons and
expectations for that:

http://blog.ffwll.ch/2013/11/testing-requirements-for-drmi915.html

Cheers, Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 0/6] Enabling DRRS support in the kernel

[Jesse Barnes]

On Thu, 28 Nov 2013 14:14:09 +0100
Daniel Vetter <daniel@ffwll.ch> wrote:
> > 	[Vandana/Pradeep]	This patch series is for seamless DRRS
> > 	support and has to be a separate path from mode set as we just
> > 	toggle the PIPE_CONF_RR_SWTICH for seamless RR transition without
> > 	flicker. Complete modeset using setCrtc will result in partial
> > 	blanking or flicker. We are not implementing fast boot as part of
> > 	this series.  Most eDP panels today which support multiple refresh
> > 	rates, support seamless DRRS. This means that hardware capability
> > 	is made use of by toggling a bit in pipe config to switch between
> > 	refresh rates on the fly. The patch series is aimed to take
> > 	advantage of this capability to switch refresh rates based on
> > 	idleness or video playback requirement. Hence, we chose the
> > 	connector attribute/ set property path.  Also in order to support
> > 	the Media refresh rates of 50/48 we thought it incorrect to
> > 	populate those modes in probed_mode list as those values are not
> > 	from the EDID. So in order for User space to know the media
> > 	refresh rates supported we have exposed a set_property interface
> > 	which makes User space aware of these media refresh rates. Also we
> > 	do not intend to do a complete mode set on media use cases in
> > 	which case we think using setCrtc is not needed. Using setCrtc
> > 	will invariably result in intermittant blanking or flicker which
> > 	cannot be avoided, and gives undesirable effect during playback.
> > 	Seamless DRRS doesn't need a complete modeset and hence no flicker
> > 	or temporary blanking. Changing the toggle RR bit in PIPE_CONF is
> > 	faster. Also since BDW has only single M/N/TU register the current
> > 	code takes care of it easily. Kindly let us know your opinion.
> > 	Since Seamless DRRS for eDP is separate path from modeset we can
> > 	keep the connector property attribute as it is.
> 
> First the technical stuff:
> 
> - Adding the additional modes to the mode list is imo totally ok and as
>   the design intents. We are already adding other modes from the vbt here
>   if those are available. The only restriction is that the kernel may not
>   add modes which don't work. But as long as the vbt tells us that 48Hz
>   will work we can (and imo should) use it.
> 
> - Second changing the frequency changes the refresh rate. Atm both our
>   userspace and the kernel support code assume that this can only be done
>   through a SetCrtc call. So adjusting the dotclock is actually the right
>   interface and we don't need any additional property.
> 
> Now the more political stuff:
> 
> - We have the long-term goal of solid fastboot support. We've the designed
>   we've picked that actually means 95% effort to get flicker-free SetCrtc
>   going and 5% actual code for fastboot. We're not there yet, there's only
>   a preview available which is disabled by default and uses a few hacks.
>   But generally all features that are relevant need to use the new
>   infrastructure and help move things forward.
> 
> - Upstream has a time horizon of 5-10 years for the kernel/userspace
>   interface. Which means quick hacks are not allowed. And in my opinion
>   your property is a quick hack, which nicely simplified the
>   implementation.
> 
> So in short I know that my request extends the scope of your patches. But
> upstream also imposes differing constraints than a product tree.

It should be possible to still merge the automatic, in-kernel only DRRS
bits though, right?  Then work on making dotclock/refresh changes from
mode sets flicker free (shouldn't be a massive amount of work).

-- 
Jesse Barnes, Intel Open Source Technology Center