[PATCH 1/3] drm/i915: cancel the hangcheck before runtime suspend

[PATCH 1/3] drm/i915: cancel the hangcheck before runtime suspend

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

The hangcheck function requires the hardware to be working, and if
we're suspending we're going to put the HW in D3 state.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index e7a6c84..70590b0 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -920,6 +920,7 @@ static int i915_runtime_suspend(struct device *device)
 
 	DRM_DEBUG_KMS("Suspending device\n");
 
+	del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
 	dev_priv->pm.suspended = true;
 	intel_opregion_notify_adapter(dev, PCI_D3cold);
 
-- 
1.8.3.1

[PATCH 2/3] drm/i915: release the GTT mmaps when going into D3

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

So we'll get a fault when someone tries to access the mmap, then we'll
wake up from D3.

v2: - Rebase
v3: - Use gtt active/inactive

Testcase: igt/pm_pc8/gem-mmap-gtt
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c |  2 ++
 drivers/gpu/drm/i915/i915_drv.h |  1 +
 drivers/gpu/drm/i915/i915_gem.c | 10 ++++++++++
 3 files changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 70590b0..23f8217 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -920,6 +920,8 @@ static int i915_runtime_suspend(struct device *device)
 
 	DRM_DEBUG_KMS("Suspending device\n");
 
+	i915_gem_release_all_mmaps(dev_priv);
+
 	del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
 	dev_priv->pm.suspended = true;
 	intel_opregion_notify_adapter(dev, PCI_D3cold);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fca2eb6..5e036be 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2013,6 +2013,7 @@ void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
 int __must_check i915_vma_unbind(struct i915_vma *vma);
 int __must_check i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj);
 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
+void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
 void i915_gem_lastclose(struct drm_device *dev);
 
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 66f8133..0d7c061 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1465,6 +1465,16 @@ out:
 	return ret;
 }
 
+void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
+{
+	struct i915_vma *vma;
+
+	list_for_each_entry(vma, &dev_priv->gtt.base.active_list, mm_list)
+		i915_gem_release_mmap(vma->obj);
+	list_for_each_entry(vma, &dev_priv->gtt.base.inactive_list, mm_list)
+		i915_gem_release_mmap(vma->obj);
+}
+
 /**
  * i915_gem_release_mmap - remove physical page mappings
  * @obj: obj in question
-- 
1.8.3.1

[PATCH 3/3] drm/i915: add runtime PM support on Haswell

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

Now that all the infrastructure is in place and all the tests from
pm_pc8 pass, we can finally enable the feature.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5e036be..5606f8d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1848,7 +1848,7 @@ struct drm_i915_file_private {
 #define HAS_FPGA_DBG_UNCLAIMED(dev)	(INTEL_INFO(dev)->has_fpga_dbg)
 #define HAS_PSR(dev)		(IS_HASWELL(dev) || IS_BROADWELL(dev))
 #define HAS_PC8(dev)		(IS_HASWELL(dev)) /* XXX HSW:ULX */
-#define HAS_RUNTIME_PM(dev)	false
+#define HAS_RUNTIME_PM(dev)	(IS_HASWELL(dev))
 
 #define INTEL_PCH_DEVICE_ID_MASK		0xff00
 #define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
-- 
1.8.3.1

Re: [PATCH 1/3] drm/i915: cancel the hangcheck before runtime suspend

[Rodrigo Vivi]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Fri, Dec 13, 2013 at 3:22 PM, Paulo Zanoni <przanoni@gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> The hangcheck function requires the hardware to be working, and if
> we're suspending we're going to put the HW in D3 state.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index e7a6c84..70590b0 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -920,6 +920,7 @@ static int i915_runtime_suspend(struct device *device)
>
>         DRM_DEBUG_KMS("Suspending device\n");
>
> +       del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
>         dev_priv->pm.suspended = true;
>         intel_opregion_notify_adapter(dev, PCI_D3cold);
>
> --
> 1.8.3.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br

Re: [PATCH 2/3] drm/i915: release the GTT mmaps when going into D3

[Rodrigo Vivi]

When I saw this I was afraid this force could break userspace somehow,
but Paulo explained me the release with pagefault mechanism. Thanks Paulo.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Fri, Dec 13, 2013 at 3:22 PM, Paulo Zanoni <przanoni@gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> So we'll get a fault when someone tries to access the mmap, then we'll
> wake up from D3.
>
> v2: - Rebase
> v3: - Use gtt active/inactive
>
> Testcase: igt/pm_pc8/gem-mmap-gtt
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.c |  2 ++
>  drivers/gpu/drm/i915/i915_drv.h |  1 +
>  drivers/gpu/drm/i915/i915_gem.c | 10 ++++++++++
>  3 files changed, 13 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 70590b0..23f8217 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -920,6 +920,8 @@ static int i915_runtime_suspend(struct device *device)
>
>         DRM_DEBUG_KMS("Suspending device\n");
>
> +       i915_gem_release_all_mmaps(dev_priv);
> +
>         del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
>         dev_priv->pm.suspended = true;
>         intel_opregion_notify_adapter(dev, PCI_D3cold);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index fca2eb6..5e036be 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2013,6 +2013,7 @@ void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
>  int __must_check i915_vma_unbind(struct i915_vma *vma);
>  int __must_check i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj);
>  int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
> +void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
>  void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
>  void i915_gem_lastclose(struct drm_device *dev);
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 66f8133..0d7c061 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -1465,6 +1465,16 @@ out:
>         return ret;
>  }
>
> +void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
> +{
> +       struct i915_vma *vma;
> +
> +       list_for_each_entry(vma, &dev_priv->gtt.base.active_list, mm_list)
> +               i915_gem_release_mmap(vma->obj);
> +       list_for_each_entry(vma, &dev_priv->gtt.base.inactive_list, mm_list)
> +               i915_gem_release_mmap(vma->obj);
> +}
> +
>  /**
>   * i915_gem_release_mmap - remove physical page mappings
>   * @obj: obj in question
> --
> 1.8.3.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br

Re: [PATCH 3/3] drm/i915: add runtime PM support on Haswell

[Rodrigo Vivi]

\o/
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Fri, Dec 13, 2013 at 3:22 PM, Paulo Zanoni <przanoni@gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> Now that all the infrastructure is in place and all the tests from
> pm_pc8 pass, we can finally enable the feature.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 5e036be..5606f8d 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1848,7 +1848,7 @@ struct drm_i915_file_private {
>  #define HAS_FPGA_DBG_UNCLAIMED(dev)    (INTEL_INFO(dev)->has_fpga_dbg)
>  #define HAS_PSR(dev)           (IS_HASWELL(dev) || IS_BROADWELL(dev))
>  #define HAS_PC8(dev)           (IS_HASWELL(dev)) /* XXX HSW:ULX */
> -#define HAS_RUNTIME_PM(dev)    false
> +#define HAS_RUNTIME_PM(dev)    (IS_HASWELL(dev))
>
>  #define INTEL_PCH_DEVICE_ID_MASK               0xff00
>  #define INTEL_PCH_IBX_DEVICE_ID_TYPE           0x3b00
> --
> 1.8.3.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br

Re: [PATCH 2/3] drm/i915: release the GTT mmaps when going into D3

[Daniel Vetter]

On Fri, Dec 13, 2013 at 04:22:40PM -0200, Rodrigo Vivi wrote:
> When I saw this I was afraid this force could break userspace somehow,
> but Paulo explained me the release with pagefault mechanism. Thanks Paulo.
> 
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

Merged all three patches with the small changes added to this one as per
our irc discussion.
-Daniel

> 
> On Fri, Dec 13, 2013 at 3:22 PM, Paulo Zanoni <przanoni@gmail.com> wrote:
> > From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> >
> > So we'll get a fault when someone tries to access the mmap, then we'll
> > wake up from D3.
> >
> > v2: - Rebase
> > v3: - Use gtt active/inactive
> >
> > Testcase: igt/pm_pc8/gem-mmap-gtt
> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_drv.c |  2 ++
> >  drivers/gpu/drm/i915/i915_drv.h |  1 +
> >  drivers/gpu/drm/i915/i915_gem.c | 10 ++++++++++
> >  3 files changed, 13 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> > index 70590b0..23f8217 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.c
> > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > @@ -920,6 +920,8 @@ static int i915_runtime_suspend(struct device *device)
> >
> >         DRM_DEBUG_KMS("Suspending device\n");
> >
> > +       i915_gem_release_all_mmaps(dev_priv);
> > +
> >         del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
> >         dev_priv->pm.suspended = true;
> >         intel_opregion_notify_adapter(dev, PCI_D3cold);
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index fca2eb6..5e036be 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -2013,6 +2013,7 @@ void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
> >  int __must_check i915_vma_unbind(struct i915_vma *vma);
> >  int __must_check i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj);
> >  int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
> > +void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
> >  void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
> >  void i915_gem_lastclose(struct drm_device *dev);
> >
> > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> > index 66f8133..0d7c061 100644
> > --- a/drivers/gpu/drm/i915/i915_gem.c
> > +++ b/drivers/gpu/drm/i915/i915_gem.c
> > @@ -1465,6 +1465,16 @@ out:
> >         return ret;
> >  }
> >
> > +void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
> > +{
> > +       struct i915_vma *vma;
> > +
> > +       list_for_each_entry(vma, &dev_priv->gtt.base.active_list, mm_list)
> > +               i915_gem_release_mmap(vma->obj);
> > +       list_for_each_entry(vma, &dev_priv->gtt.base.inactive_list, mm_list)
> > +               i915_gem_release_mmap(vma->obj);
> > +}
> > +
> >  /**
> >   * i915_gem_release_mmap - remove physical page mappings
> >   * @obj: obj in question
> > --
> > 1.8.3.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> 
> 
> -- 
> Rodrigo Vivi
> Blog: http://blog.vivi.eng.br
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch