From: Jesse Barnes <jbarnes@virtuousgeek.org>
To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/6] drm/i915: Replace hardcoded cacheline size with macro
Date: Wed, 2 Apr 2014 14:57:11 -0700 [thread overview]
Message-ID: <20140402145711.66469be9@jbarnes-desktop> (raw)
In-Reply-To: <1396452971-25654-1-git-send-email-chris@chris-wilson.co.uk>
On Wed, 2 Apr 2014 16:36:06 +0100
Chris Wilson <chris@chris-wilson.co.uk> wrote:
> For readibility and guess at the meaning behind the constants.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/intel_ringbuffer.c | 29 ++++++++++++++++-------------
> 1 file changed, 16 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 785f246d28a8..475391ce671a 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -33,6 +33,8 @@
> #include "i915_trace.h"
> #include "intel_drv.h"
>
> +#define CACHELINE_BYTES 64
> +
Are you sure it's 64 on every gen? It changes on the CPU side from
time to time... I thought it might have changed over time on the GPU
too but I haven't checked the specs.
Either way a doc ref would be nice here.
--
Jesse Barnes, Intel Open Source Technology Center
next prev parent reply other threads:[~2014-04-02 21:56 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-04-02 15:36 [PATCH 1/6] drm/i915: Replace hardcoded cacheline size with macro Chris Wilson
2014-04-02 15:36 ` [PATCH 2/6] drm/i915: Move all ring resets before setting the HWS page Chris Wilson
2014-04-02 21:58 ` Jesse Barnes
2014-04-03 15:18 ` Daniel Vetter
2014-04-02 15:36 ` [PATCH 3/6] drm/i915: Preserve ring buffers objects across resume Chris Wilson
2014-04-02 22:10 ` Jesse Barnes
2014-04-03 6:43 ` Chris Wilson
2014-04-02 15:36 ` [PATCH 4/6] drm/i915: Allow the module to load even if we fail to setup rings Chris Wilson
2014-04-02 22:11 ` Jesse Barnes
2014-04-03 6:42 ` Chris Wilson
2014-04-02 15:36 ` [PATCH 5/6] drm/i915: Mark device as wedged if we fail to resume Chris Wilson
2014-04-02 15:36 ` [PATCH 6/6] drm/i915: Include a little more information about why ring init fails Chris Wilson
2014-04-02 21:57 ` Jesse Barnes [this message]
2014-04-03 6:45 ` [PATCH 1/6] drm/i915: Replace hardcoded cacheline size with macro Chris Wilson
2014-04-03 15:16 ` Daniel Vetter
2014-04-03 15:23 ` Chris Wilson
2014-04-03 21:09 ` Daniel Vetter
-- strict thread matches above, loose matches on Subject: below --
2014-04-09 8:19 Chris Wilson
2014-04-22 12:35 ` Mateo Lozano, Oscar
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