From: Daniel Vetter <daniel@ffwll.ch>
To: Damien Lespiau <damien.lespiau@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 15/28] drm/i915/skl: Check the DDB state at modeset
Date: Wed, 5 Nov 2014 11:33:36 +0100 [thread overview]
Message-ID: <20141105103336.GE26941@phenom.ffwll.local> (raw)
In-Reply-To: <1415120825-4375-16-git-send-email-damien.lespiau@intel.com>
On Tue, Nov 04, 2014 at 05:06:52PM +0000, Damien Lespiau wrote:
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index ecba620..9ec1ab7 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -10509,6 +10509,56 @@ intel_pipe_config_compare(struct drm_device *dev,
> return true;
> }
>
> +static void check_wm_state(struct drm_device *dev)
> +{
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + struct skl_ddb_allocation hw_ddb, *sw_ddb;
> + struct intel_crtc *intel_crtc;
> + int plane;
> +
> + if (INTEL_INFO(dev)->gen < 9)
> + return;
> +
> + skl_ddb_get_hw_state(dev_priv, &hw_ddb);
> + sw_ddb = &dev_priv->wm.skl_hw.ddb;
This looks like a pretty nifty layering violation, with exposing the skl
function and all. I guess the long-term plan is to have just one wm
structure for everyone, as part of the plane state? And then we'll just
read out the plane state and cross-check that one?
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2014-11-05 10:33 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-11-04 17:06 [PATCH 00/28] SKL stage 1, a few more patches Damien Lespiau
2014-11-04 17:06 ` [PATCH 01/28] drm/i915/skl: Read the Memory Latency Values for WM computation Damien Lespiau
2014-11-05 10:25 ` Daniel Vetter
2014-11-05 10:29 ` Daniel Vetter
2014-11-04 17:06 ` [PATCH 02/28] drm/i915/skl: Register definitions and macros for SKL Watermark regs Damien Lespiau
2014-11-04 17:06 ` [PATCH 03/28] drm/i915/skl: Definition of SKL WM param structs for pipe/plane Damien Lespiau
2014-11-04 17:06 ` [PATCH 04/28] drm/i915/skl: Add DDB allocation management structures Damien Lespiau
2014-11-04 17:06 ` [PATCH 05/28] drm/i915/skl: SKL Watermark Computation Damien Lespiau
2014-11-04 17:06 ` [PATCH 06/28] drm/i915/skl: Allocate DDB portions for display planes Damien Lespiau
2014-11-04 17:06 ` [PATCH 07/28] drm/i915/skl: Program the DDB allocation Damien Lespiau
2014-11-04 17:06 ` [PATCH 08/28] drm/i915/skl: Read the pipe WM HW state Damien Lespiau
2014-11-04 17:06 ` [PATCH 09/28] drm/i915/gen9: Add 2us read latency to WM level Damien Lespiau
2014-11-04 17:06 ` [PATCH 10/28] drm/i915/gen9: Disable WM if corresponding latency is 0 Damien Lespiau
2014-11-04 17:06 ` [PATCH 11/28] drm/i915/skl: Store the new WM state at the very end of the update Damien Lespiau
2014-11-04 17:06 ` [PATCH 12/28] drm/i915/skl: Read back the DDB allocation hw state Damien Lespiau
2014-11-04 17:06 ` [PATCH 13/28] drm/i915/skl: Augment the latency debugfs files for SKL Damien Lespiau
2014-11-04 17:06 ` [PATCH 14/28] drm/i915/skl: Add a debugfs file to dump the DDB allocation Damien Lespiau
2014-11-04 17:06 ` [PATCH 15/28] drm/i915/skl: Check the DDB state at modeset Damien Lespiau
2014-11-05 10:33 ` Daniel Vetter [this message]
2014-11-04 17:06 ` [PATCH 16/28] drm/i915/skl: Make 'end' of the DDB allocation entry exclusive Damien Lespiau
2014-11-04 17:06 ` [PATCH 17/28] drm/i915/skl: Use a more descriptive parameter name in skl_compute_plane_wm() Damien Lespiau
2014-11-04 17:06 ` [PATCH 18/28] drm/i915/skl: Make res_blocks/lines intermediate values 32 bits Damien Lespiau
2014-11-04 17:06 ` [PATCH 19/28] drm/i915/skl: Reduce the number of holes in struct skl_wm_level Damien Lespiau
2014-11-04 17:06 ` [PATCH 20/28] drm/i915/skl: Move all the WM compute functions in one place Damien Lespiau
2014-11-04 17:06 ` [PATCH 21/28] drm/i915/skl: Rework when the transition WMs are computed Damien Lespiau
2014-11-04 17:06 ` [PATCH 22/28] drm/i915/skl: Correctly align skl_compute_plane_wm() arguments Damien Lespiau
2014-11-04 17:07 ` [PATCH 23/28] drm/i915/skl: Reduce the indentation level in skl_write_wm_values() Damien Lespiau
2014-11-04 17:07 ` [PATCH 24/28] drm/i915/skl: Stage the pipe DDB allocation Damien Lespiau
2014-11-04 17:07 ` [PATCH 25/28] drm/i915/skl: Flush the WM configuration Damien Lespiau
2014-11-04 17:07 ` [PATCH 26/28] drm/i915/skl: Log the order in which we flush the pipes in the WM code Damien Lespiau
2014-11-04 17:07 ` [PATCH 27/28] drm/i915/skl: Gen9 Forcewake Damien Lespiau
2014-11-04 17:07 ` [PATCH 28/28] drm/i915/skl: Enable Gen9 RC6 Damien Lespiau
2014-11-05 11:28 ` [PATCH 00/28] SKL stage 1, a few more patches Daniel Vetter
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20141105103336.GE26941@phenom.ffwll.local \
--to=daniel@ffwll.ch \
--cc=damien.lespiau@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox