* [PATCH 4/8] drm/i915: move rps irq enable/disable to i915_irq.c @ 2014-11-05 18:48 Imre Deak 2014-11-10 13:34 ` [PATCH 4.1] drm/i915: WARN if we receive any gen9 rps interrupts Imre Deak 0 siblings, 1 reply; 4+ messages in thread From: Imre Deak @ 2014-11-05 18:48 UTC (permalink / raw) To: intel-gfx; +Cc: shuang.he The logical place for these functions is in i915_irq.c next to the rest of PM interrupt handling functions. No functional change. Signed-off-by: Imre Deak <imre.deak@intel.com> --- drivers/gpu/drm/i915/i915_irq.c | 43 ++++++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_drv.h | 2 ++ drivers/gpu/drm/i915/intel_pm.c | 41 -------------------------------------- 3 files changed, 45 insertions(+), 41 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index b7ea3a8..ce4139e 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -138,6 +138,8 @@ static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */ POSTING_READ(type##IMR); \ } while (0) +static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir); + /* For display hotplug interrupt */ void ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask) @@ -200,11 +202,21 @@ void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) ilk_update_gt_irq(dev_priv, mask, 0); } +static u32 gen6_pm_iir(struct drm_i915_private *dev_priv) +{ + return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR; +} + static u32 gen6_pm_imr(struct drm_i915_private *dev_priv) { return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR; } +static u32 gen6_pm_ier(struct drm_i915_private *dev_priv) +{ + return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER; +} + /** * snb_update_pm_irq - update GEN6_PMIMR * @dev_priv: driver private @@ -243,6 +255,37 @@ void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) snb_update_pm_irq(dev_priv, mask, 0); } +void gen6_enable_rps_interrupts(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + + spin_lock_irq(&dev_priv->irq_lock); + WARN_ON(dev_priv->rps.pm_iir); + gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); + I915_WRITE(gen6_pm_iir(dev_priv), dev_priv->pm_rps_events); + spin_unlock_irq(&dev_priv->irq_lock); +} + +void gen6_disable_rps_interrupts(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + + I915_WRITE(GEN6_PMINTRMSK, INTEL_INFO(dev_priv)->gen >= 8 ? + ~GEN8_PMINTR_REDIRECT_TO_NON_DISP : ~0); + I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) & + ~dev_priv->pm_rps_events); + /* Complete PM interrupt masking here doesn't race with the rps work + * item again unmasking PM interrupts because that is using a different + * register (PMIMR) to mask PM interrupts. The only risk is in leaving + * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */ + + spin_lock_irq(&dev_priv->irq_lock); + dev_priv->rps.pm_iir = 0; + spin_unlock_irq(&dev_priv->irq_lock); + + I915_WRITE(gen6_pm_iir(dev_priv), dev_priv->pm_rps_events); +} + /** * ibx_display_interrupt_update - update SDEIMR * @dev_priv: driver private diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index a980fb3..6d275c9 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -791,6 +791,8 @@ void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); +void gen6_enable_rps_interrupts(struct drm_device *dev); +void gen6_disable_rps_interrupts(struct drm_device *dev); void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv); void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv); static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 0ab9f5d..9f67400 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4519,16 +4519,6 @@ void valleyview_set_rps(struct drm_device *dev, u8 val) trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val)); } -static u32 gen6_pm_iir(struct drm_i915_private *dev_priv) -{ - return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR; -} - -static u32 gen6_pm_ier(struct drm_i915_private *dev_priv) -{ - return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER; -} - static void gen9_disable_rps(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; @@ -4536,26 +4526,6 @@ static void gen9_disable_rps(struct drm_device *dev) I915_WRITE(GEN6_RC_CONTROL, 0); } -static void gen6_disable_rps_interrupts(struct drm_device *dev) -{ - struct drm_i915_private *dev_priv = dev->dev_private; - - I915_WRITE(GEN6_PMINTRMSK, INTEL_INFO(dev_priv)->gen >= 8 ? - ~GEN8_PMINTR_REDIRECT_TO_NON_DISP : ~0); - I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) & - ~dev_priv->pm_rps_events); - /* Complete PM interrupt masking here doesn't race with the rps work - * item again unmasking PM interrupts because that is using a different - * register (PMIMR) to mask PM interrupts. The only risk is in leaving - * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */ - - spin_lock_irq(&dev_priv->irq_lock); - dev_priv->rps.pm_iir = 0; - spin_unlock_irq(&dev_priv->irq_lock); - - I915_WRITE(gen6_pm_iir(dev_priv), dev_priv->pm_rps_events); -} - static void gen6_disable_rps(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; @@ -4651,17 +4621,6 @@ int intel_enable_rc6(const struct drm_device *dev) return i915.enable_rc6; } -static void gen6_enable_rps_interrupts(struct drm_device *dev) -{ - struct drm_i915_private *dev_priv = dev->dev_private; - - spin_lock_irq(&dev_priv->irq_lock); - WARN_ON(dev_priv->rps.pm_iir); - gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); - I915_WRITE(gen6_pm_iir(dev_priv), dev_priv->pm_rps_events); - spin_unlock_irq(&dev_priv->irq_lock); -} - static void parse_rp_state_cap(struct drm_i915_private *dev_priv, u32 rp_state_cap) { /* All of these values are in units of 50MHz */ -- 1.8.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 4.1] drm/i915: WARN if we receive any gen9 rps interrupts 2014-11-05 18:48 [PATCH 4/8] drm/i915: move rps irq enable/disable to i915_irq.c Imre Deak @ 2014-11-10 13:34 ` Imre Deak 2014-11-11 1:27 ` [PATCH 4.1] drm/i915: WARN if we receive any gen9 rps shuang.he 2014-11-11 10:32 ` [PATCH 4.1] drm/i915: WARN if we receive any gen9 rps interrupts Daniel Vetter 0 siblings, 2 replies; 4+ messages in thread From: Imre Deak @ 2014-11-10 13:34 UTC (permalink / raw) To: intel-gfx; +Cc: paulo.r.zanoni Paulo noticed that we don't support RPS on GEN9 yet, so WARN for and ignore any RPS interrupts on that platform. Signed-off-by: Imre Deak <imre.deak@intel.com> --- drivers/gpu/drm/i915/i915_irq.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 96d150f..729e9a3 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -1690,6 +1690,11 @@ static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) * the work queue. */ static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) { + /* TODO: RPS on GEN9 is not supported yet. */ + if (WARN_ONCE(INTEL_INFO(dev_priv)->gen == 9, + "GEN9: unexpected RPS IRQ\n")) + return; + if (pm_iir & dev_priv->pm_rps_events) { spin_lock(&dev_priv->irq_lock); dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events; -- 1.8.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH 4.1] drm/i915: WARN if we receive any gen9 rps 2014-11-10 13:34 ` [PATCH 4.1] drm/i915: WARN if we receive any gen9 rps interrupts Imre Deak @ 2014-11-11 1:27 ` shuang.he 2014-11-11 10:32 ` [PATCH 4.1] drm/i915: WARN if we receive any gen9 rps interrupts Daniel Vetter 1 sibling, 0 replies; 4+ messages in thread From: shuang.he @ 2014-11-11 1:27 UTC (permalink / raw) To: shuang.he, intel-gfx, imre.deak Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com) -------------------------------------Summary------------------------------------- Platform: baseline_drm_intel_nightly_pass_rate->patch_applied_pass_rate BYT: pass/total=277/348->277/348 PNV: pass/total=323/328->326/328 ILK: pass/total=328/330->330/330 IVB: pass/total=545/546->545/546 SNB: pass/total=558/563->559/563 HSW: pass/total=574/578->572/578 BDW: pass/total=435/435->434/435 -------------------------------------Detailed------------------------------------- test_platform: test_suite, test_case, result_with_drm_intel_nightly(count, machine_id...)...->result_with_patch_applied(count, machine_id)... PNV: Intel_gpu_tools, igt_gem_linear_blits_normal, NSPT(1, M23)PASS(6, M24) -> PASS(4, M24) PNV: Intel_gpu_tools, igt_gem_mmap_offset_exhaustion, DMESG_WARN(2, M23M24)PASS(14, M24M23M7) -> DMESG_WARN(1, M24)PASS(3, M24) PNV: Intel_gpu_tools, igt_gem_unref_active_buffers, DMESG_WARN(2, M23)PASS(14, M24M23M7) -> PASS(4, M24) ILK: Intel_gpu_tools, igt_kms_render_gpu-blit, DMESG_WARN(1, M26)PASS(15, M6M26M37) -> PASS(4, M37) ILK: Intel_gpu_tools, igt_kms_flip_wf_vblank-vs-dpms-interruptible, DMESG_WARN(1, M26)PASS(15, M6M26M37) -> PASS(4, M37) IVB: Intel_gpu_tools, igt_gem_bad_reloc_negative-reloc, NSPT(3, M4M34)PASS(7, M34M4) -> NSPT(2, M4)PASS(2, M4) IVB: Intel_gpu_tools, igt_kms_plane_plane-position-covered-pipe-A-plane-1, TIMEOUT(1, M34)PASS(6, M4) -> PASS(4, M4) SNB: Intel_gpu_tools, igt_kms_cursor_crc_cursor-256x256-sliding, DMESG_WARN(2, M35)PASS(5, M22M35) -> DMESG_WARN(1, M35)PASS(3, M35) HSW: Intel_gpu_tools, igt_gem_bad_reloc_negative-reloc, NSPT(4, M39M20M40)PASS(9, M40M39M20) -> NSPT(2, M40)PASS(2, M40) HSW: Intel_gpu_tools, igt_kms_cursor_crc_cursor-64x64-offscreen, DMESG_WARN(1, M39)PASS(6, M40M39) -> DMESG_WARN(1, M40)PASS(3, M40) BDW: Intel_gpu_tools, igt_gem_reset_stats_ban-bsd, PASS(16, M30M28M42) -> DMESG_WARN(1, M28)PASS(3, M28) _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 4.1] drm/i915: WARN if we receive any gen9 rps interrupts 2014-11-10 13:34 ` [PATCH 4.1] drm/i915: WARN if we receive any gen9 rps interrupts Imre Deak 2014-11-11 1:27 ` [PATCH 4.1] drm/i915: WARN if we receive any gen9 rps shuang.he @ 2014-11-11 10:32 ` Daniel Vetter 1 sibling, 0 replies; 4+ messages in thread From: Daniel Vetter @ 2014-11-11 10:32 UTC (permalink / raw) To: Imre Deak; +Cc: intel-gfx, paulo.r.zanoni On Mon, Nov 10, 2014 at 03:34:33PM +0200, Imre Deak wrote: > Paulo noticed that we don't support RPS on GEN9 yet, so WARN for and > ignore any RPS interrupts on that platform. > > Signed-off-by: Imre Deak <imre.deak@intel.com> Pulled in up to this one from this series, I'll wait for Paulo to double-check the new versions of the subsequent patches. Thanks, Daniel > --- > drivers/gpu/drm/i915/i915_irq.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index 96d150f..729e9a3 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -1690,6 +1690,11 @@ static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) > * the work queue. */ > static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) > { > + /* TODO: RPS on GEN9 is not supported yet. */ > + if (WARN_ONCE(INTEL_INFO(dev_priv)->gen == 9, > + "GEN9: unexpected RPS IRQ\n")) > + return; > + > if (pm_iir & dev_priv->pm_rps_events) { > spin_lock(&dev_priv->irq_lock); > dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events; > -- > 1.8.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2014-11-11 10:32 UTC | newest] Thread overview: 4+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2014-11-05 18:48 [PATCH 4/8] drm/i915: move rps irq enable/disable to i915_irq.c Imre Deak 2014-11-10 13:34 ` [PATCH 4.1] drm/i915: WARN if we receive any gen9 rps interrupts Imre Deak 2014-11-11 1:27 ` [PATCH 4.1] drm/i915: WARN if we receive any gen9 rps shuang.he 2014-11-11 10:32 ` [PATCH 4.1] drm/i915: WARN if we receive any gen9 rps interrupts Daniel Vetter
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