[PATCH 01/15] drm/i915: Make dp aux pack/unpack public outside intel_dp.c

[PATCH 01/15] drm/i915: Make dp aux pack/unpack public outside intel_dp.c

[Rodrigo Vivi]

No functional change. Just making it public for use outside intel_dp.c
Allowing split psr functions.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 15 +++++++--------
 1 file changed, 7 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 45b53ff..01834cd 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -227,8 +227,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
 	return MODE_OK;
 }
 
-static uint32_t
-pack_aux(const uint8_t *src, int src_bytes)
+uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
 {
 	int	i;
 	uint32_t v = 0;
@@ -240,8 +239,7 @@ pack_aux(const uint8_t *src, int src_bytes)
 	return v;
 }
 
-static void
-unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
+void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 {
 	int i;
 	if (dst_bytes > 4)
@@ -863,7 +861,8 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
 			/* Load the send data into the aux channel data registers */
 			for (i = 0; i < send_bytes; i += 4)
 				I915_WRITE(ch_data + i,
-					   pack_aux(send + i, send_bytes - i));
+					   intel_dp_pack_aux(send + i,
+							     send_bytes - i));
 
 			/* Send the command and wait for it to complete */
 			I915_WRITE(ch_ctl, send_ctl);
@@ -917,8 +916,8 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
 		recv_bytes = recv_size;
 
 	for (i = 0; i < recv_bytes; i += 4)
-		unpack_aux(I915_READ(ch_data + i),
-			   recv + i, recv_bytes - i);
+		intel_dp_unpack_aux(I915_READ(ch_data + i),
+				    recv + i, recv_bytes - i);
 
 	ret = recv_bytes;
 out:
@@ -2159,7 +2158,7 @@ static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
 	/* Setup AUX registers */
 	for (i = 0; i < sizeof(aux_msg); i += 4)
 		I915_WRITE(EDP_PSR_AUX_DATA1(dev) + i,
-			   pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
+			   intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
 
 	I915_WRITE(EDP_PSR_AUX_CTL(dev),
 		   DP_AUX_CH_CTL_TIME_OUT_400us |
-- 
1.9.3

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[PATCH 02/15] drm/i915: Introduce intel_psr.c

[Rodrigo Vivi]

No functional changes. Just cleaning and reorganizing it.

v2: Rebase it puting it to begin of psr rework. This helps to blame easily
at least latest changes.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/Makefile            |   1 +
 drivers/gpu/drm/i915/intel_ddi.c         |   4 +-
 drivers/gpu/drm/i915/intel_display.c     |   2 +-
 drivers/gpu/drm/i915/intel_dp.c          | 381 +----------------------------
 drivers/gpu/drm/i915/intel_drv.h         |  21 +-
 drivers/gpu/drm/i915/intel_frontbuffer.c |   4 +-
 drivers/gpu/drm/i915/intel_psr.c         | 408 +++++++++++++++++++++++++++++++
 7 files changed, 428 insertions(+), 393 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_psr.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 891e584..e4083e4 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -51,6 +51,7 @@ i915-y += intel_audio.o \
 	  intel_frontbuffer.o \
 	  intel_modes.o \
 	  intel_overlay.o \
+	  intel_psr.o \
 	  intel_sideband.o \
 	  intel_sprite.o
 i915-$(CONFIG_ACPI)		+= intel_acpi.o intel_opregion.o
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 68703ce..a5a8acd 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1228,7 +1228,7 @@ static void intel_enable_ddi(struct intel_encoder *intel_encoder)
 			intel_dp_stop_link_train(intel_dp);
 
 		intel_edp_backlight_on(intel_dp);
-		intel_edp_psr_enable(intel_dp);
+		intel_psr_enable(intel_dp);
 	}
 
 	if (intel_crtc->config.has_audio) {
@@ -1254,7 +1254,7 @@ static void intel_disable_ddi(struct intel_encoder *intel_encoder)
 	if (type == INTEL_OUTPUT_EDP) {
 		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 
-		intel_edp_psr_disable(intel_dp);
+		intel_psr_disable(intel_dp);
 		intel_edp_backlight_off(intel_dp);
 	}
 }
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 4706856..2ca6939 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12310,7 +12310,7 @@ static void intel_setup_outputs(struct drm_device *dev)
 	if (SUPPORTS_TV(dev))
 		intel_tv_init(dev);
 
-	intel_edp_psr_init(dev);
+	intel_psr_init(dev);
 
 	for_each_intel_encoder(dev, encoder) {
 		encoder->base.possible_crtcs = encoder->crtc_mask;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 01834cd..98f7ecd 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2066,385 +2066,6 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
 	}
 }
 
-static bool is_edp_psr(struct intel_dp *intel_dp)
-{
-	return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
-}
-
-static bool intel_edp_is_psr_enabled(struct drm_device *dev)
-{
-	struct drm_i915_private *dev_priv = dev->dev_private;
-
-	if (!HAS_PSR(dev))
-		return false;
-
-	return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
-}
-
-static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
-				    struct edp_vsc_psr *vsc_psr)
-{
-	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
-	struct drm_device *dev = dig_port->base.base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
-	u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
-	u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
-	uint32_t *data = (uint32_t *) vsc_psr;
-	unsigned int i;
-
-	/* As per BSPec (Pipe Video Data Island Packet), we need to disable
-	   the video DIP being updated before program video DIP data buffer
-	   registers for DIP being updated. */
-	I915_WRITE(ctl_reg, 0);
-	POSTING_READ(ctl_reg);
-
-	for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
-		if (i < sizeof(struct edp_vsc_psr))
-			I915_WRITE(data_reg + i, *data++);
-		else
-			I915_WRITE(data_reg + i, 0);
-	}
-
-	I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
-	POSTING_READ(ctl_reg);
-}
-
-static void intel_edp_psr_setup_vsc(struct intel_dp *intel_dp)
-{
-	struct edp_vsc_psr psr_vsc;
-
-	/* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
-	memset(&psr_vsc, 0, sizeof(psr_vsc));
-	psr_vsc.sdp_header.HB0 = 0;
-	psr_vsc.sdp_header.HB1 = 0x7;
-	psr_vsc.sdp_header.HB2 = 0x2;
-	psr_vsc.sdp_header.HB3 = 0x8;
-	intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
-}
-
-static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
-{
-	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
-	struct drm_device *dev = dig_port->base.base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	uint32_t aux_clock_divider;
-	int precharge = 0x3;
-	bool only_standby = false;
-	static const uint8_t aux_msg[] = {
-		[0] = DP_AUX_NATIVE_WRITE << 4,
-		[1] = DP_SET_POWER >> 8,
-		[2] = DP_SET_POWER & 0xff,
-		[3] = 1 - 1,
-		[4] = DP_SET_POWER_D0,
-	};
-	int i;
-
-	BUILD_BUG_ON(sizeof(aux_msg) > 20);
-
-	aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
-
-	if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
-		only_standby = true;
-
-	/* Enable PSR in sink */
-	if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
-		drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
-				   DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
-	else
-		drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
-				   DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
-
-	/* Setup AUX registers */
-	for (i = 0; i < sizeof(aux_msg); i += 4)
-		I915_WRITE(EDP_PSR_AUX_DATA1(dev) + i,
-			   intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
-
-	I915_WRITE(EDP_PSR_AUX_CTL(dev),
-		   DP_AUX_CH_CTL_TIME_OUT_400us |
-		   (sizeof(aux_msg) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
-		   (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
-		   (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
-}
-
-static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
-{
-	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
-	struct drm_device *dev = dig_port->base.base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	uint32_t max_sleep_time = 0x1f;
-	uint32_t idle_frames = 1;
-	uint32_t val = 0x0;
-	const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
-	bool only_standby = false;
-
-	if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
-		only_standby = true;
-
-	if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
-		val |= EDP_PSR_LINK_STANDBY;
-		val |= EDP_PSR_TP2_TP3_TIME_0us;
-		val |= EDP_PSR_TP1_TIME_0us;
-		val |= EDP_PSR_SKIP_AUX_EXIT;
-		val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
-	} else
-		val |= EDP_PSR_LINK_DISABLE;
-
-	I915_WRITE(EDP_PSR_CTL(dev), val |
-		   (IS_BROADWELL(dev) ? 0 : link_entry_time) |
-		   max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
-		   idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
-		   EDP_PSR_ENABLE);
-}
-
-static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
-{
-	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
-	struct drm_device *dev = dig_port->base.base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct drm_crtc *crtc = dig_port->base.base.crtc;
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-
-	lockdep_assert_held(&dev_priv->psr.lock);
-	WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
-	WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
-
-	dev_priv->psr.source_ok = false;
-
-	if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
-		DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
-		return false;
-	}
-
-	if (!i915.enable_psr) {
-		DRM_DEBUG_KMS("PSR disable by flag\n");
-		return false;
-	}
-
-	/* Below limitations aren't valid for Broadwell */
-	if (IS_BROADWELL(dev))
-		goto out;
-
-	if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
-	    S3D_ENABLE) {
-		DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
-		return false;
-	}
-
-	if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
-		DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
-		return false;
-	}
-
- out:
-	dev_priv->psr.source_ok = true;
-	return true;
-}
-
-static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
-{
-	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
-	struct drm_device *dev = intel_dig_port->base.base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
-
-	WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
-	WARN_ON(dev_priv->psr.active);
-	lockdep_assert_held(&dev_priv->psr.lock);
-
-	/* Enable/Re-enable PSR on the host */
-	intel_edp_psr_enable_source(intel_dp);
-
-	dev_priv->psr.active = true;
-}
-
-void intel_edp_psr_enable(struct intel_dp *intel_dp)
-{
-	struct drm_device *dev = intel_dp_to_dev(intel_dp);
-	struct drm_i915_private *dev_priv = dev->dev_private;
-
-	if (!HAS_PSR(dev)) {
-		DRM_DEBUG_KMS("PSR not supported on this platform\n");
-		return;
-	}
-
-	if (!is_edp_psr(intel_dp)) {
-		DRM_DEBUG_KMS("PSR not supported by this panel\n");
-		return;
-	}
-
-	mutex_lock(&dev_priv->psr.lock);
-	if (dev_priv->psr.enabled) {
-		DRM_DEBUG_KMS("PSR already in use\n");
-		goto unlock;
-	}
-
-	if (!intel_edp_psr_match_conditions(intel_dp))
-		goto unlock;
-
-	dev_priv->psr.busy_frontbuffer_bits = 0;
-
-	intel_edp_psr_setup_vsc(intel_dp);
-
-	/* Avoid continuous PSR exit by masking memup and hpd */
-	I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
-		   EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
-
-	/* Enable PSR on the panel */
-	intel_edp_psr_enable_sink(intel_dp);
-
-	dev_priv->psr.enabled = intel_dp;
-unlock:
-	mutex_unlock(&dev_priv->psr.lock);
-}
-
-void intel_edp_psr_disable(struct intel_dp *intel_dp)
-{
-	struct drm_device *dev = intel_dp_to_dev(intel_dp);
-	struct drm_i915_private *dev_priv = dev->dev_private;
-
-	mutex_lock(&dev_priv->psr.lock);
-	if (!dev_priv->psr.enabled) {
-		mutex_unlock(&dev_priv->psr.lock);
-		return;
-	}
-
-	if (dev_priv->psr.active) {
-		I915_WRITE(EDP_PSR_CTL(dev),
-			   I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
-
-		/* Wait till PSR is idle */
-		if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
-			       EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
-			DRM_ERROR("Timed out waiting for PSR Idle State\n");
-
-		dev_priv->psr.active = false;
-	} else {
-		WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
-	}
-
-	dev_priv->psr.enabled = NULL;
-	mutex_unlock(&dev_priv->psr.lock);
-
-	cancel_delayed_work_sync(&dev_priv->psr.work);
-}
-
-static void intel_edp_psr_work(struct work_struct *work)
-{
-	struct drm_i915_private *dev_priv =
-		container_of(work, typeof(*dev_priv), psr.work.work);
-	struct intel_dp *intel_dp = dev_priv->psr.enabled;
-
-	/* We have to make sure PSR is ready for re-enable
-	 * otherwise it keeps disabled until next full enable/disable cycle.
-	 * PSR might take some time to get fully disabled
-	 * and be ready for re-enable.
-	 */
-	if (wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev_priv->dev)) &
-		      EDP_PSR_STATUS_STATE_MASK) == 0, 50)) {
-		DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
-		return;
-	}
-
-	mutex_lock(&dev_priv->psr.lock);
-	intel_dp = dev_priv->psr.enabled;
-
-	if (!intel_dp)
-		goto unlock;
-
-	/*
-	 * The delayed work can race with an invalidate hence we need to
-	 * recheck. Since psr_flush first clears this and then reschedules we
-	 * won't ever miss a flush when bailing out here.
-	 */
-	if (dev_priv->psr.busy_frontbuffer_bits)
-		goto unlock;
-
-	intel_edp_psr_do_enable(intel_dp);
-unlock:
-	mutex_unlock(&dev_priv->psr.lock);
-}
-
-static void intel_edp_psr_do_exit(struct drm_device *dev)
-{
-	struct drm_i915_private *dev_priv = dev->dev_private;
-
-	if (dev_priv->psr.active) {
-		u32 val = I915_READ(EDP_PSR_CTL(dev));
-
-		WARN_ON(!(val & EDP_PSR_ENABLE));
-
-		I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
-
-		dev_priv->psr.active = false;
-	}
-
-}
-
-void intel_edp_psr_invalidate(struct drm_device *dev,
-			      unsigned frontbuffer_bits)
-{
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct drm_crtc *crtc;
-	enum pipe pipe;
-
-	mutex_lock(&dev_priv->psr.lock);
-	if (!dev_priv->psr.enabled) {
-		mutex_unlock(&dev_priv->psr.lock);
-		return;
-	}
-
-	crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
-	pipe = to_intel_crtc(crtc)->pipe;
-
-	intel_edp_psr_do_exit(dev);
-
-	frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
-
-	dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
-	mutex_unlock(&dev_priv->psr.lock);
-}
-
-void intel_edp_psr_flush(struct drm_device *dev,
-			 unsigned frontbuffer_bits)
-{
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct drm_crtc *crtc;
-	enum pipe pipe;
-
-	mutex_lock(&dev_priv->psr.lock);
-	if (!dev_priv->psr.enabled) {
-		mutex_unlock(&dev_priv->psr.lock);
-		return;
-	}
-
-	crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
-	pipe = to_intel_crtc(crtc)->pipe;
-	dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
-
-	/*
-	 * On Haswell sprite plane updates don't result in a psr invalidating
-	 * signal in the hardware. Which means we need to manually fake this in
-	 * software for all flushes, not just when we've seen a preceding
-	 * invalidation through frontbuffer rendering.
-	 */
-	if (IS_HASWELL(dev) &&
-	    (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
-		intel_edp_psr_do_exit(dev);
-
-	if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
-		schedule_delayed_work(&dev_priv->psr.work,
-				      msecs_to_jiffies(100));
-	mutex_unlock(&dev_priv->psr.lock);
-}
-
-void intel_edp_psr_init(struct drm_device *dev)
-{
-	struct drm_i915_private *dev_priv = dev->dev_private;
-
-	INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
-	mutex_init(&dev_priv->psr.lock);
-}
-
 static void intel_disable_dp(struct intel_encoder *encoder)
 {
 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
@@ -5115,7 +4736,7 @@ void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
 	 * hard to tell without seeing the user of this function of this code.
 	 * Check locking and ordering once that lands.
 	 */
-	if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
+	if (INTEL_INFO(dev)->gen < 8 && intel_psr_is_enabled(dev)) {
 		DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
 		return;
 	}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 8432ae2..ccfee9c 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -996,21 +996,16 @@ void intel_edp_backlight_off(struct intel_dp *intel_dp);
 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
 void intel_edp_panel_on(struct intel_dp *intel_dp);
 void intel_edp_panel_off(struct intel_dp *intel_dp);
-void intel_edp_psr_enable(struct intel_dp *intel_dp);
-void intel_edp_psr_disable(struct intel_dp *intel_dp);
 void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate);
-void intel_edp_psr_invalidate(struct drm_device *dev,
-			      unsigned frontbuffer_bits);
-void intel_edp_psr_flush(struct drm_device *dev,
-			 unsigned frontbuffer_bits);
-void intel_edp_psr_init(struct drm_device *dev);
-
 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
 void intel_dp_mst_suspend(struct drm_device *dev);
 void intel_dp_mst_resume(struct drm_device *dev);
 int intel_dp_max_link_bw(struct intel_dp *intel_dp);
 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
+uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
+void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes);
+
 /* intel_dp_mst.c */
 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
@@ -1114,6 +1109,16 @@ void intel_backlight_register(struct drm_device *dev);
 void intel_backlight_unregister(struct drm_device *dev);
 
 
+/* intel_psr.c */
+bool intel_psr_is_enabled(struct drm_device *dev);
+void intel_psr_enable(struct intel_dp *intel_dp);
+void intel_psr_disable(struct intel_dp *intel_dp);
+void intel_psr_invalidate(struct drm_device *dev,
+			      unsigned frontbuffer_bits);
+void intel_psr_flush(struct drm_device *dev,
+			 unsigned frontbuffer_bits);
+void intel_psr_init(struct drm_device *dev);
+
 /* intel_runtime_pm.c */
 int intel_power_domains_init(struct drm_i915_private *);
 void intel_power_domains_fini(struct drm_i915_private *);
diff --git a/drivers/gpu/drm/i915/intel_frontbuffer.c b/drivers/gpu/drm/i915/intel_frontbuffer.c
index 58cf2e6..79f6d72 100644
--- a/drivers/gpu/drm/i915/intel_frontbuffer.c
+++ b/drivers/gpu/drm/i915/intel_frontbuffer.c
@@ -156,7 +156,7 @@ void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
 
 	intel_mark_fb_busy(dev, obj->frontbuffer_bits, ring);
 
-	intel_edp_psr_invalidate(dev, obj->frontbuffer_bits);
+	intel_psr_invalidate(dev, obj->frontbuffer_bits);
 }
 
 /**
@@ -182,7 +182,7 @@ void intel_frontbuffer_flush(struct drm_device *dev,
 
 	intel_mark_fb_busy(dev, frontbuffer_bits, NULL);
 
-	intel_edp_psr_flush(dev, frontbuffer_bits);
+	intel_psr_flush(dev, frontbuffer_bits);
 
 	/*
 	 * FIXME: Unconditional fbc flushing here is a rather gross hack and
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
new file mode 100644
index 0000000..7b3ed91
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -0,0 +1,408 @@
+/*
+ * Copyright © 2014 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <drm/drmP.h>
+
+#include "intel_drv.h"
+#include "i915_drv.h"
+
+static bool is_edp_psr(struct intel_dp *intel_dp)
+{
+	return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
+}
+
+bool intel_psr_is_enabled(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	if (!HAS_PSR(dev))
+		return false;
+
+	return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
+}
+
+static void intel_psr_write_vsc(struct intel_dp *intel_dp,
+				    struct edp_vsc_psr *vsc_psr)
+{
+	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+	struct drm_device *dev = dig_port->base.base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
+	u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
+	u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
+	uint32_t *data = (uint32_t *) vsc_psr;
+	unsigned int i;
+
+	/* As per BSPec (Pipe Video Data Island Packet), we need to disable
+	   the video DIP being updated before program video DIP data buffer
+	   registers for DIP being updated. */
+	I915_WRITE(ctl_reg, 0);
+	POSTING_READ(ctl_reg);
+
+	for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
+		if (i < sizeof(struct edp_vsc_psr))
+			I915_WRITE(data_reg + i, *data++);
+		else
+			I915_WRITE(data_reg + i, 0);
+	}
+
+	I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
+	POSTING_READ(ctl_reg);
+}
+
+static void intel_psr_setup_vsc(struct intel_dp *intel_dp)
+{
+	struct edp_vsc_psr psr_vsc;
+
+	/* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
+	memset(&psr_vsc, 0, sizeof(psr_vsc));
+	psr_vsc.sdp_header.HB0 = 0;
+	psr_vsc.sdp_header.HB1 = 0x7;
+	psr_vsc.sdp_header.HB2 = 0x2;
+	psr_vsc.sdp_header.HB3 = 0x8;
+	intel_psr_write_vsc(intel_dp, &psr_vsc);
+}
+
+static void intel_psr_enable_sink(struct intel_dp *intel_dp)
+{
+	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+	struct drm_device *dev = dig_port->base.base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	uint32_t aux_clock_divider;
+	int precharge = 0x3;
+	bool only_standby = false;
+	static const uint8_t aux_msg[] = {
+		[0] = DP_AUX_NATIVE_WRITE << 4,
+		[1] = DP_SET_POWER >> 8,
+		[2] = DP_SET_POWER & 0xff,
+		[3] = 1 - 1,
+		[4] = DP_SET_POWER_D0,
+	};
+	int i;
+
+	BUILD_BUG_ON(sizeof(aux_msg) > 20);
+
+	aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
+
+	if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
+		only_standby = true;
+
+	/* Enable PSR in sink */
+	if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
+		drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
+				   DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
+	else
+		drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
+				   DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
+
+	/* Setup AUX registers */
+	for (i = 0; i < sizeof(aux_msg); i += 4)
+		I915_WRITE(EDP_PSR_AUX_DATA1(dev) + i,
+			   intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
+
+	I915_WRITE(EDP_PSR_AUX_CTL(dev),
+		   DP_AUX_CH_CTL_TIME_OUT_400us |
+		   (sizeof(aux_msg) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
+		   (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
+		   (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
+}
+
+static void intel_psr_enable_source(struct intel_dp *intel_dp)
+{
+	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+	struct drm_device *dev = dig_port->base.base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	uint32_t max_sleep_time = 0x1f;
+	uint32_t idle_frames = 1;
+	uint32_t val = 0x0;
+	const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
+	bool only_standby = false;
+
+	if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
+		only_standby = true;
+
+	if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
+		val |= EDP_PSR_LINK_STANDBY;
+		val |= EDP_PSR_TP2_TP3_TIME_0us;
+		val |= EDP_PSR_TP1_TIME_0us;
+		val |= EDP_PSR_SKIP_AUX_EXIT;
+		val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
+	} else
+		val |= EDP_PSR_LINK_DISABLE;
+
+	I915_WRITE(EDP_PSR_CTL(dev), val |
+		   (IS_BROADWELL(dev) ? 0 : link_entry_time) |
+		   max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
+		   idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
+		   EDP_PSR_ENABLE);
+}
+
+static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
+{
+	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+	struct drm_device *dev = dig_port->base.base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_crtc *crtc = dig_port->base.base.crtc;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+
+	lockdep_assert_held(&dev_priv->psr.lock);
+	WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
+	WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
+
+	dev_priv->psr.source_ok = false;
+
+	if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
+		DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
+		return false;
+	}
+
+	if (!i915.enable_psr) {
+		DRM_DEBUG_KMS("PSR disable by flag\n");
+		return false;
+	}
+
+	/* Below limitations aren't valid for Broadwell */
+	if (IS_BROADWELL(dev))
+		goto out;
+
+	if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
+	    S3D_ENABLE) {
+		DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
+		return false;
+	}
+
+	if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
+		DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
+		return false;
+	}
+
+ out:
+	dev_priv->psr.source_ok = true;
+	return true;
+}
+
+static void intel_psr_do_enable(struct intel_dp *intel_dp)
+{
+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+	struct drm_device *dev = intel_dig_port->base.base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
+	WARN_ON(dev_priv->psr.active);
+	lockdep_assert_held(&dev_priv->psr.lock);
+
+	/* Enable/Re-enable PSR on the host */
+	intel_psr_enable_source(intel_dp);
+
+	dev_priv->psr.active = true;
+}
+
+void intel_psr_enable(struct intel_dp *intel_dp)
+{
+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+	struct drm_device *dev = intel_dig_port->base.base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	if (!HAS_PSR(dev)) {
+		DRM_DEBUG_KMS("PSR not supported on this platform\n");
+		return;
+	}
+
+	if (!is_edp_psr(intel_dp)) {
+		DRM_DEBUG_KMS("PSR not supported by this panel\n");
+		return;
+	}
+
+	mutex_lock(&dev_priv->psr.lock);
+	if (dev_priv->psr.enabled) {
+		DRM_DEBUG_KMS("PSR already in use\n");
+		goto unlock;
+	}
+
+	if (!intel_psr_match_conditions(intel_dp))
+		goto unlock;
+
+	dev_priv->psr.busy_frontbuffer_bits = 0;
+
+	intel_psr_setup_vsc(intel_dp);
+
+	/* Avoid continuous PSR exit by masking memup and hpd */
+	I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
+		   EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
+
+	/* Enable PSR on the panel */
+	intel_psr_enable_sink(intel_dp);
+
+	dev_priv->psr.enabled = intel_dp;
+unlock:
+	mutex_unlock(&dev_priv->psr.lock);
+}
+
+void intel_psr_disable(struct intel_dp *intel_dp)
+{
+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+	struct drm_device *dev = intel_dig_port->base.base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	mutex_lock(&dev_priv->psr.lock);
+	if (!dev_priv->psr.enabled) {
+		mutex_unlock(&dev_priv->psr.lock);
+		return;
+	}
+
+	if (dev_priv->psr.active) {
+		I915_WRITE(EDP_PSR_CTL(dev),
+			   I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
+
+		/* Wait till PSR is idle */
+		if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
+			       EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
+			DRM_ERROR("Timed out waiting for PSR Idle State\n");
+
+		dev_priv->psr.active = false;
+	} else {
+		WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
+	}
+
+	dev_priv->psr.enabled = NULL;
+	mutex_unlock(&dev_priv->psr.lock);
+
+	cancel_delayed_work_sync(&dev_priv->psr.work);
+}
+
+static void intel_psr_work(struct work_struct *work)
+{
+	struct drm_i915_private *dev_priv =
+		container_of(work, typeof(*dev_priv), psr.work.work);
+	struct intel_dp *intel_dp = dev_priv->psr.enabled;
+
+	/* We have to make sure PSR is ready for re-enable
+	 * otherwise it keeps disabled until next full enable/disable cycle.
+	 * PSR might take some time to get fully disabled
+	 * and be ready for re-enable.
+	 */
+	if (wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev_priv->dev)) &
+		      EDP_PSR_STATUS_STATE_MASK) == 0, 50)) {
+		DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
+		return;
+	}
+
+	mutex_lock(&dev_priv->psr.lock);
+	intel_dp = dev_priv->psr.enabled;
+
+	if (!intel_dp)
+		goto unlock;
+
+	/*
+	 * The delayed work can race with an invalidate hence we need to
+	 * recheck. Since psr_flush first clears this and then reschedules we
+	 * won't ever miss a flush when bailing out here.
+	 */
+	if (dev_priv->psr.busy_frontbuffer_bits)
+		goto unlock;
+
+	intel_psr_do_enable(intel_dp);
+unlock:
+	mutex_unlock(&dev_priv->psr.lock);
+}
+
+static void intel_psr_exit(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	if (dev_priv->psr.active) {
+		u32 val = I915_READ(EDP_PSR_CTL(dev));
+
+		WARN_ON(!(val & EDP_PSR_ENABLE));
+
+		I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
+
+		dev_priv->psr.active = false;
+	}
+
+}
+
+void intel_psr_invalidate(struct drm_device *dev,
+			      unsigned frontbuffer_bits)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_crtc *crtc;
+	enum pipe pipe;
+
+	mutex_lock(&dev_priv->psr.lock);
+	if (!dev_priv->psr.enabled) {
+		mutex_unlock(&dev_priv->psr.lock);
+		return;
+	}
+
+	crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
+	pipe = to_intel_crtc(crtc)->pipe;
+
+	intel_psr_exit(dev);
+
+	frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
+
+	dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
+	mutex_unlock(&dev_priv->psr.lock);
+}
+
+void intel_psr_flush(struct drm_device *dev,
+			 unsigned frontbuffer_bits)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_crtc *crtc;
+	enum pipe pipe;
+
+	mutex_lock(&dev_priv->psr.lock);
+	if (!dev_priv->psr.enabled) {
+		mutex_unlock(&dev_priv->psr.lock);
+		return;
+	}
+
+	crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
+	pipe = to_intel_crtc(crtc)->pipe;
+	dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
+
+	/*
+	 * On Haswell sprite plane updates don't result in a psr invalidating
+	 * signal in the hardware. Which means we need to manually fake this in
+	 * software for all flushes, not just when we've seen a preceding
+	 * invalidation through frontbuffer rendering.
+	 */
+	if (IS_HASWELL(dev) &&
+	    (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
+		intel_psr_exit(dev);
+
+	if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
+		schedule_delayed_work(&dev_priv->psr.work,
+				      msecs_to_jiffies(100));
+	mutex_unlock(&dev_priv->psr.lock);
+}
+
+void intel_psr_init(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	INIT_DELAYED_WORK(&dev_priv->psr.work, intel_psr_work);
+	mutex_init(&dev_priv->psr.lock);
+}
-- 
1.9.3

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 02/15] drm/i915: Introduce intel_psr.c

[R, Durgadoss]

>-----Original Message-----
>From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of Rodrigo Vivi
>Sent: Friday, November 14, 2014 10:22 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Vivi, Rodrigo
>Subject: [Intel-gfx] [PATCH 02/15] drm/i915: Introduce intel_psr.c
>
>No functional changes. Just cleaning and reorganizing it.
>
>v2: Rebase it puting it to begin of psr rework. This helps to blame easily
>at least latest changes.
>
>Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>---
> drivers/gpu/drm/i915/Makefile            |   1 +
> drivers/gpu/drm/i915/intel_ddi.c         |   4 +-
> drivers/gpu/drm/i915/intel_display.c     |   2 +-
> drivers/gpu/drm/i915/intel_dp.c          | 381 +----------------------------
> drivers/gpu/drm/i915/intel_drv.h         |  21 +-
> drivers/gpu/drm/i915/intel_frontbuffer.c |   4 +-
> drivers/gpu/drm/i915/intel_psr.c         | 408 +++++++++++++++++++++++++++++++
> 7 files changed, 428 insertions(+), 393 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/intel_psr.c
>
>diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
>index 891e584..e4083e4 100644
>--- a/drivers/gpu/drm/i915/Makefile
>+++ b/drivers/gpu/drm/i915/Makefile
>@@ -51,6 +51,7 @@ i915-y += intel_audio.o \
> 	  intel_frontbuffer.o \
> 	  intel_modes.o \
> 	  intel_overlay.o \
>+	  intel_psr.o \
> 	  intel_sideband.o \
> 	  intel_sprite.o
> i915-$(CONFIG_ACPI)		+= intel_acpi.o intel_opregion.o
>diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
>index 68703ce..a5a8acd 100644
>--- a/drivers/gpu/drm/i915/intel_ddi.c
>+++ b/drivers/gpu/drm/i915/intel_ddi.c
>@@ -1228,7 +1228,7 @@ static void intel_enable_ddi(struct intel_encoder *intel_encoder)
> 			intel_dp_stop_link_train(intel_dp);
>
> 		intel_edp_backlight_on(intel_dp);
>-		intel_edp_psr_enable(intel_dp);
>+		intel_psr_enable(intel_dp);
> 	}
>
> 	if (intel_crtc->config.has_audio) {
>@@ -1254,7 +1254,7 @@ static void intel_disable_ddi(struct intel_encoder *intel_encoder)
> 	if (type == INTEL_OUTPUT_EDP) {
> 		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>
>-		intel_edp_psr_disable(intel_dp);
>+		intel_psr_disable(intel_dp);
> 		intel_edp_backlight_off(intel_dp);
> 	}
> }
>diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>index 4706856..2ca6939 100644
>--- a/drivers/gpu/drm/i915/intel_display.c
>+++ b/drivers/gpu/drm/i915/intel_display.c
>@@ -12310,7 +12310,7 @@ static void intel_setup_outputs(struct drm_device *dev)
> 	if (SUPPORTS_TV(dev))
> 		intel_tv_init(dev);
>
>-	intel_edp_psr_init(dev);
>+	intel_psr_init(dev);
>
> 	for_each_intel_encoder(dev, encoder) {
> 		encoder->base.possible_crtcs = encoder->crtc_mask;
>diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>index 01834cd..98f7ecd 100644
>--- a/drivers/gpu/drm/i915/intel_dp.c
>+++ b/drivers/gpu/drm/i915/intel_dp.c
>@@ -2066,385 +2066,6 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
> 	}
> }
>
>-static bool is_edp_psr(struct intel_dp *intel_dp)
>-{
>-	return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
>-}
>-
>-static bool intel_edp_is_psr_enabled(struct drm_device *dev)
>-{
>-	struct drm_i915_private *dev_priv = dev->dev_private;
>-
>-	if (!HAS_PSR(dev))
>-		return false;
>-
>-	return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
>-}
>-
>-static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
>-				    struct edp_vsc_psr *vsc_psr)
>-{
>-	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>-	struct drm_device *dev = dig_port->base.base.dev;
>-	struct drm_i915_private *dev_priv = dev->dev_private;
>-	struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
>-	u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
>-	u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
>-	uint32_t *data = (uint32_t *) vsc_psr;
>-	unsigned int i;
>-
>-	/* As per BSPec (Pipe Video Data Island Packet), we need to disable
>-	   the video DIP being updated before program video DIP data buffer
>-	   registers for DIP being updated. */
>-	I915_WRITE(ctl_reg, 0);
>-	POSTING_READ(ctl_reg);
>-
>-	for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
>-		if (i < sizeof(struct edp_vsc_psr))
>-			I915_WRITE(data_reg + i, *data++);
>-		else
>-			I915_WRITE(data_reg + i, 0);
>-	}
>-
>-	I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
>-	POSTING_READ(ctl_reg);
>-}
>-
>-static void intel_edp_psr_setup_vsc(struct intel_dp *intel_dp)
>-{
>-	struct edp_vsc_psr psr_vsc;
>-
>-	/* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
>-	memset(&psr_vsc, 0, sizeof(psr_vsc));
>-	psr_vsc.sdp_header.HB0 = 0;
>-	psr_vsc.sdp_header.HB1 = 0x7;
>-	psr_vsc.sdp_header.HB2 = 0x2;
>-	psr_vsc.sdp_header.HB3 = 0x8;
>-	intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
>-}
>-
>-static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
>-{
>-	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>-	struct drm_device *dev = dig_port->base.base.dev;
>-	struct drm_i915_private *dev_priv = dev->dev_private;
>-	uint32_t aux_clock_divider;
>-	int precharge = 0x3;
>-	bool only_standby = false;
>-	static const uint8_t aux_msg[] = {
>-		[0] = DP_AUX_NATIVE_WRITE << 4,
>-		[1] = DP_SET_POWER >> 8,
>-		[2] = DP_SET_POWER & 0xff,
>-		[3] = 1 - 1,
>-		[4] = DP_SET_POWER_D0,
>-	};
>-	int i;
>-
>-	BUILD_BUG_ON(sizeof(aux_msg) > 20);
>-
>-	aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
>-
>-	if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
>-		only_standby = true;
>-
>-	/* Enable PSR in sink */
>-	if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
>-		drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
>-				   DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
>-	else
>-		drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
>-				   DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
>-
>-	/* Setup AUX registers */
>-	for (i = 0; i < sizeof(aux_msg); i += 4)
>-		I915_WRITE(EDP_PSR_AUX_DATA1(dev) + i,
>-			   intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
>-
>-	I915_WRITE(EDP_PSR_AUX_CTL(dev),
>-		   DP_AUX_CH_CTL_TIME_OUT_400us |
>-		   (sizeof(aux_msg) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
>-		   (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
>-		   (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
>-}
>-
>-static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
>-{
>-	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>-	struct drm_device *dev = dig_port->base.base.dev;
>-	struct drm_i915_private *dev_priv = dev->dev_private;
>-	uint32_t max_sleep_time = 0x1f;
>-	uint32_t idle_frames = 1;
>-	uint32_t val = 0x0;
>-	const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
>-	bool only_standby = false;
>-
>-	if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
>-		only_standby = true;
>-
>-	if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
>-		val |= EDP_PSR_LINK_STANDBY;
>-		val |= EDP_PSR_TP2_TP3_TIME_0us;
>-		val |= EDP_PSR_TP1_TIME_0us;
>-		val |= EDP_PSR_SKIP_AUX_EXIT;
>-		val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
>-	} else
>-		val |= EDP_PSR_LINK_DISABLE;
>-
>-	I915_WRITE(EDP_PSR_CTL(dev), val |
>-		   (IS_BROADWELL(dev) ? 0 : link_entry_time) |
>-		   max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
>-		   idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
>-		   EDP_PSR_ENABLE);
>-}
>-
>-static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
>-{
>-	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>-	struct drm_device *dev = dig_port->base.base.dev;
>-	struct drm_i915_private *dev_priv = dev->dev_private;
>-	struct drm_crtc *crtc = dig_port->base.base.crtc;
>-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>-
>-	lockdep_assert_held(&dev_priv->psr.lock);
>-	WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
>-	WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
>-
>-	dev_priv->psr.source_ok = false;
>-
>-	if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
>-		DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
>-		return false;
>-	}
>-
>-	if (!i915.enable_psr) {
>-		DRM_DEBUG_KMS("PSR disable by flag\n");
>-		return false;
>-	}
>-
>-	/* Below limitations aren't valid for Broadwell */
>-	if (IS_BROADWELL(dev))
>-		goto out;
>-
>-	if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
>-	    S3D_ENABLE) {
>-		DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
>-		return false;
>-	}
>-
>-	if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
>-		DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
>-		return false;
>-	}
>-
>- out:
>-	dev_priv->psr.source_ok = true;
>-	return true;
>-}
>-
>-static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
>-{
>-	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>-	struct drm_device *dev = intel_dig_port->base.base.dev;
>-	struct drm_i915_private *dev_priv = dev->dev_private;
>-
>-	WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
>-	WARN_ON(dev_priv->psr.active);
>-	lockdep_assert_held(&dev_priv->psr.lock);
>-
>-	/* Enable/Re-enable PSR on the host */
>-	intel_edp_psr_enable_source(intel_dp);
>-
>-	dev_priv->psr.active = true;
>-}
>-
>-void intel_edp_psr_enable(struct intel_dp *intel_dp)
>-{
>-	struct drm_device *dev = intel_dp_to_dev(intel_dp);
>-	struct drm_i915_private *dev_priv = dev->dev_private;
>-
>-	if (!HAS_PSR(dev)) {
>-		DRM_DEBUG_KMS("PSR not supported on this platform\n");
>-		return;
>-	}
>-
>-	if (!is_edp_psr(intel_dp)) {
>-		DRM_DEBUG_KMS("PSR not supported by this panel\n");
>-		return;
>-	}
>-
>-	mutex_lock(&dev_priv->psr.lock);
>-	if (dev_priv->psr.enabled) {
>-		DRM_DEBUG_KMS("PSR already in use\n");
>-		goto unlock;
>-	}
>-
>-	if (!intel_edp_psr_match_conditions(intel_dp))
>-		goto unlock;
>-
>-	dev_priv->psr.busy_frontbuffer_bits = 0;
>-
>-	intel_edp_psr_setup_vsc(intel_dp);
>-
>-	/* Avoid continuous PSR exit by masking memup and hpd */
>-	I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
>-		   EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
>-
>-	/* Enable PSR on the panel */
>-	intel_edp_psr_enable_sink(intel_dp);
>-
>-	dev_priv->psr.enabled = intel_dp;
>-unlock:
>-	mutex_unlock(&dev_priv->psr.lock);
>-}
>-
>-void intel_edp_psr_disable(struct intel_dp *intel_dp)
>-{
>-	struct drm_device *dev = intel_dp_to_dev(intel_dp);
>-	struct drm_i915_private *dev_priv = dev->dev_private;
>-
>-	mutex_lock(&dev_priv->psr.lock);
>-	if (!dev_priv->psr.enabled) {
>-		mutex_unlock(&dev_priv->psr.lock);
>-		return;
>-	}
>-
>-	if (dev_priv->psr.active) {
>-		I915_WRITE(EDP_PSR_CTL(dev),
>-			   I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
>-
>-		/* Wait till PSR is idle */
>-		if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
>-			       EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
>-			DRM_ERROR("Timed out waiting for PSR Idle State\n");
>-
>-		dev_priv->psr.active = false;
>-	} else {
>-		WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
>-	}
>-
>-	dev_priv->psr.enabled = NULL;
>-	mutex_unlock(&dev_priv->psr.lock);
>-
>-	cancel_delayed_work_sync(&dev_priv->psr.work);
>-}
>-
>-static void intel_edp_psr_work(struct work_struct *work)
>-{
>-	struct drm_i915_private *dev_priv =
>-		container_of(work, typeof(*dev_priv), psr.work.work);
>-	struct intel_dp *intel_dp = dev_priv->psr.enabled;
>-
>-	/* We have to make sure PSR is ready for re-enable
>-	 * otherwise it keeps disabled until next full enable/disable cycle.
>-	 * PSR might take some time to get fully disabled
>-	 * and be ready for re-enable.
>-	 */
>-	if (wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev_priv->dev)) &
>-		      EDP_PSR_STATUS_STATE_MASK) == 0, 50)) {
>-		DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
>-		return;
>-	}
>-
>-	mutex_lock(&dev_priv->psr.lock);
>-	intel_dp = dev_priv->psr.enabled;
>-
>-	if (!intel_dp)
>-		goto unlock;
>-
>-	/*
>-	 * The delayed work can race with an invalidate hence we need to
>-	 * recheck. Since psr_flush first clears this and then reschedules we
>-	 * won't ever miss a flush when bailing out here.
>-	 */
>-	if (dev_priv->psr.busy_frontbuffer_bits)
>-		goto unlock;
>-
>-	intel_edp_psr_do_enable(intel_dp);
>-unlock:
>-	mutex_unlock(&dev_priv->psr.lock);
>-}
>-
>-static void intel_edp_psr_do_exit(struct drm_device *dev)
>-{
>-	struct drm_i915_private *dev_priv = dev->dev_private;
>-
>-	if (dev_priv->psr.active) {
>-		u32 val = I915_READ(EDP_PSR_CTL(dev));
>-
>-		WARN_ON(!(val & EDP_PSR_ENABLE));
>-
>-		I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
>-
>-		dev_priv->psr.active = false;
>-	}
>-
>-}
>-
>-void intel_edp_psr_invalidate(struct drm_device *dev,
>-			      unsigned frontbuffer_bits)
>-{
>-	struct drm_i915_private *dev_priv = dev->dev_private;
>-	struct drm_crtc *crtc;
>-	enum pipe pipe;
>-
>-	mutex_lock(&dev_priv->psr.lock);
>-	if (!dev_priv->psr.enabled) {
>-		mutex_unlock(&dev_priv->psr.lock);
>-		return;
>-	}
>-
>-	crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
>-	pipe = to_intel_crtc(crtc)->pipe;
>-
>-	intel_edp_psr_do_exit(dev);
>-
>-	frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
>-
>-	dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
>-	mutex_unlock(&dev_priv->psr.lock);
>-}
>-
>-void intel_edp_psr_flush(struct drm_device *dev,
>-			 unsigned frontbuffer_bits)
>-{
>-	struct drm_i915_private *dev_priv = dev->dev_private;
>-	struct drm_crtc *crtc;
>-	enum pipe pipe;
>-
>-	mutex_lock(&dev_priv->psr.lock);
>-	if (!dev_priv->psr.enabled) {
>-		mutex_unlock(&dev_priv->psr.lock);
>-		return;
>-	}
>-
>-	crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
>-	pipe = to_intel_crtc(crtc)->pipe;
>-	dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
>-
>-	/*
>-	 * On Haswell sprite plane updates don't result in a psr invalidating
>-	 * signal in the hardware. Which means we need to manually fake this in
>-	 * software for all flushes, not just when we've seen a preceding
>-	 * invalidation through frontbuffer rendering.
>-	 */
>-	if (IS_HASWELL(dev) &&
>-	    (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
>-		intel_edp_psr_do_exit(dev);
>-
>-	if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
>-		schedule_delayed_work(&dev_priv->psr.work,
>-				      msecs_to_jiffies(100));
>-	mutex_unlock(&dev_priv->psr.lock);
>-}
>-
>-void intel_edp_psr_init(struct drm_device *dev)
>-{
>-	struct drm_i915_private *dev_priv = dev->dev_private;
>-
>-	INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
>-	mutex_init(&dev_priv->psr.lock);
>-}
>-
> static void intel_disable_dp(struct intel_encoder *encoder)
> {
> 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
>@@ -5115,7 +4736,7 @@ void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
> 	 * hard to tell without seeing the user of this function of this code.
> 	 * Check locking and ordering once that lands.
> 	 */
>-	if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
>+	if (INTEL_INFO(dev)->gen < 8 && intel_psr_is_enabled(dev)) {

Shouldn't we do <= 8 to cover CHV ?

Also, I see that we are converting the 'static' _is_enabled function into a
non-static (exported) one and use 'psr.enabled' variable. (patch 9/15)
In this case, shouldn't we protect this function using psr.lock ?
[actually a comment on patch 9/15, but the caller is here]

Thanks,
Durga

> 		DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
> 		return;
> 	}
>diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
>index 8432ae2..ccfee9c 100644
>--- a/drivers/gpu/drm/i915/intel_drv.h
>+++ b/drivers/gpu/drm/i915/intel_drv.h
>@@ -996,21 +996,16 @@ void intel_edp_backlight_off(struct intel_dp *intel_dp);
> void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
> void intel_edp_panel_on(struct intel_dp *intel_dp);
> void intel_edp_panel_off(struct intel_dp *intel_dp);
>-void intel_edp_psr_enable(struct intel_dp *intel_dp);
>-void intel_edp_psr_disable(struct intel_dp *intel_dp);
> void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate);
>-void intel_edp_psr_invalidate(struct drm_device *dev,
>-			      unsigned frontbuffer_bits);
>-void intel_edp_psr_flush(struct drm_device *dev,
>-			 unsigned frontbuffer_bits);
>-void intel_edp_psr_init(struct drm_device *dev);
>-
> void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
> void intel_dp_mst_suspend(struct drm_device *dev);
> void intel_dp_mst_resume(struct drm_device *dev);
> int intel_dp_max_link_bw(struct intel_dp *intel_dp);
> void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
> void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
>+uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
>+void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes);
>+
> /* intel_dp_mst.c */
> int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
> void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
>@@ -1114,6 +1109,16 @@ void intel_backlight_register(struct drm_device *dev);
> void intel_backlight_unregister(struct drm_device *dev);
>
>
>+/* intel_psr.c */
>+bool intel_psr_is_enabled(struct drm_device *dev);
>+void intel_psr_enable(struct intel_dp *intel_dp);
>+void intel_psr_disable(struct intel_dp *intel_dp);
>+void intel_psr_invalidate(struct drm_device *dev,
>+			      unsigned frontbuffer_bits);
>+void intel_psr_flush(struct drm_device *dev,
>+			 unsigned frontbuffer_bits);
>+void intel_psr_init(struct drm_device *dev);
>+
> /* intel_runtime_pm.c */
> int intel_power_domains_init(struct drm_i915_private *);
> void intel_power_domains_fini(struct drm_i915_private *);
>diff --git a/drivers/gpu/drm/i915/intel_frontbuffer.c b/drivers/gpu/drm/i915/intel_frontbuffer.c
>index 58cf2e6..79f6d72 100644
>--- a/drivers/gpu/drm/i915/intel_frontbuffer.c
>+++ b/drivers/gpu/drm/i915/intel_frontbuffer.c
>@@ -156,7 +156,7 @@ void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
>
> 	intel_mark_fb_busy(dev, obj->frontbuffer_bits, ring);
>
>-	intel_edp_psr_invalidate(dev, obj->frontbuffer_bits);
>+	intel_psr_invalidate(dev, obj->frontbuffer_bits);
> }
>
> /**
>@@ -182,7 +182,7 @@ void intel_frontbuffer_flush(struct drm_device *dev,
>
> 	intel_mark_fb_busy(dev, frontbuffer_bits, NULL);
>
>-	intel_edp_psr_flush(dev, frontbuffer_bits);
>+	intel_psr_flush(dev, frontbuffer_bits);
>
> 	/*
> 	 * FIXME: Unconditional fbc flushing here is a rather gross hack and
>diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
>new file mode 100644
>index 0000000..7b3ed91
>--- /dev/null
>+++ b/drivers/gpu/drm/i915/intel_psr.c
>@@ -0,0 +1,408 @@
>+/*
>+ * Copyright © 2014 Intel Corporation
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice (including the next
>+ * paragraph) shall be included in all copies or substantial portions of the
>+ * Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
>+ * DEALINGS IN THE SOFTWARE.
>+ */
>+
>+#include <drm/drmP.h>
>+
>+#include "intel_drv.h"
>+#include "i915_drv.h"
>+
>+static bool is_edp_psr(struct intel_dp *intel_dp)
>+{
>+	return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
>+}
>+
>+bool intel_psr_is_enabled(struct drm_device *dev)
>+{
>+	struct drm_i915_private *dev_priv = dev->dev_private;
>+
>+	if (!HAS_PSR(dev))
>+		return false;
>+
>+	return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
>+}
>+
>+static void intel_psr_write_vsc(struct intel_dp *intel_dp,
>+				    struct edp_vsc_psr *vsc_psr)
>+{
>+	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>+	struct drm_device *dev = dig_port->base.base.dev;
>+	struct drm_i915_private *dev_priv = dev->dev_private;
>+	struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
>+	u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
>+	u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
>+	uint32_t *data = (uint32_t *) vsc_psr;
>+	unsigned int i;
>+
>+	/* As per BSPec (Pipe Video Data Island Packet), we need to disable
>+	   the video DIP being updated before program video DIP data buffer
>+	   registers for DIP being updated. */
>+	I915_WRITE(ctl_reg, 0);
>+	POSTING_READ(ctl_reg);
>+
>+	for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
>+		if (i < sizeof(struct edp_vsc_psr))
>+			I915_WRITE(data_reg + i, *data++);
>+		else
>+			I915_WRITE(data_reg + i, 0);
>+	}
>+
>+	I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
>+	POSTING_READ(ctl_reg);
>+}
>+
>+static void intel_psr_setup_vsc(struct intel_dp *intel_dp)
>+{
>+	struct edp_vsc_psr psr_vsc;
>+
>+	/* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
>+	memset(&psr_vsc, 0, sizeof(psr_vsc));
>+	psr_vsc.sdp_header.HB0 = 0;
>+	psr_vsc.sdp_header.HB1 = 0x7;
>+	psr_vsc.sdp_header.HB2 = 0x2;
>+	psr_vsc.sdp_header.HB3 = 0x8;
>+	intel_psr_write_vsc(intel_dp, &psr_vsc);
>+}
>+
>+static void intel_psr_enable_sink(struct intel_dp *intel_dp)
>+{
>+	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>+	struct drm_device *dev = dig_port->base.base.dev;
>+	struct drm_i915_private *dev_priv = dev->dev_private;
>+	uint32_t aux_clock_divider;
>+	int precharge = 0x3;
>+	bool only_standby = false;
>+	static const uint8_t aux_msg[] = {
>+		[0] = DP_AUX_NATIVE_WRITE << 4,
>+		[1] = DP_SET_POWER >> 8,
>+		[2] = DP_SET_POWER & 0xff,
>+		[3] = 1 - 1,
>+		[4] = DP_SET_POWER_D0,
>+	};
>+	int i;
>+
>+	BUILD_BUG_ON(sizeof(aux_msg) > 20);
>+
>+	aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
>+
>+	if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
>+		only_standby = true;
>+
>+	/* Enable PSR in sink */
>+	if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
>+		drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
>+				   DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
>+	else
>+		drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
>+				   DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
>+
>+	/* Setup AUX registers */
>+	for (i = 0; i < sizeof(aux_msg); i += 4)
>+		I915_WRITE(EDP_PSR_AUX_DATA1(dev) + i,
>+			   intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
>+
>+	I915_WRITE(EDP_PSR_AUX_CTL(dev),
>+		   DP_AUX_CH_CTL_TIME_OUT_400us |
>+		   (sizeof(aux_msg) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
>+		   (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
>+		   (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
>+}
>+
>+static void intel_psr_enable_source(struct intel_dp *intel_dp)
>+{
>+	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>+	struct drm_device *dev = dig_port->base.base.dev;
>+	struct drm_i915_private *dev_priv = dev->dev_private;
>+	uint32_t max_sleep_time = 0x1f;
>+	uint32_t idle_frames = 1;
>+	uint32_t val = 0x0;
>+	const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
>+	bool only_standby = false;
>+
>+	if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
>+		only_standby = true;
>+
>+	if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
>+		val |= EDP_PSR_LINK_STANDBY;
>+		val |= EDP_PSR_TP2_TP3_TIME_0us;
>+		val |= EDP_PSR_TP1_TIME_0us;
>+		val |= EDP_PSR_SKIP_AUX_EXIT;
>+		val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
>+	} else
>+		val |= EDP_PSR_LINK_DISABLE;
>+
>+	I915_WRITE(EDP_PSR_CTL(dev), val |
>+		   (IS_BROADWELL(dev) ? 0 : link_entry_time) |
>+		   max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
>+		   idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
>+		   EDP_PSR_ENABLE);
>+}
>+
>+static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
>+{
>+	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>+	struct drm_device *dev = dig_port->base.base.dev;
>+	struct drm_i915_private *dev_priv = dev->dev_private;
>+	struct drm_crtc *crtc = dig_port->base.base.crtc;
>+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>+
>+	lockdep_assert_held(&dev_priv->psr.lock);
>+	WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
>+	WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
>+
>+	dev_priv->psr.source_ok = false;
>+
>+	if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
>+		DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
>+		return false;
>+	}
>+
>+	if (!i915.enable_psr) {
>+		DRM_DEBUG_KMS("PSR disable by flag\n");
>+		return false;
>+	}
>+
>+	/* Below limitations aren't valid for Broadwell */
>+	if (IS_BROADWELL(dev))
>+		goto out;
>+
>+	if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
>+	    S3D_ENABLE) {
>+		DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
>+		return false;
>+	}
>+
>+	if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
>+		DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
>+		return false;
>+	}
>+
>+ out:
>+	dev_priv->psr.source_ok = true;
>+	return true;
>+}
>+
>+static void intel_psr_do_enable(struct intel_dp *intel_dp)
>+{
>+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>+	struct drm_device *dev = intel_dig_port->base.base.dev;
>+	struct drm_i915_private *dev_priv = dev->dev_private;
>+
>+	WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
>+	WARN_ON(dev_priv->psr.active);
>+	lockdep_assert_held(&dev_priv->psr.lock);
>+
>+	/* Enable/Re-enable PSR on the host */
>+	intel_psr_enable_source(intel_dp);
>+
>+	dev_priv->psr.active = true;
>+}
>+
>+void intel_psr_enable(struct intel_dp *intel_dp)
>+{
>+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>+	struct drm_device *dev = intel_dig_port->base.base.dev;
>+	struct drm_i915_private *dev_priv = dev->dev_private;
>+
>+	if (!HAS_PSR(dev)) {
>+		DRM_DEBUG_KMS("PSR not supported on this platform\n");
>+		return;
>+	}
>+
>+	if (!is_edp_psr(intel_dp)) {
>+		DRM_DEBUG_KMS("PSR not supported by this panel\n");
>+		return;
>+	}
>+
>+	mutex_lock(&dev_priv->psr.lock);
>+	if (dev_priv->psr.enabled) {
>+		DRM_DEBUG_KMS("PSR already in use\n");
>+		goto unlock;
>+	}
>+
>+	if (!intel_psr_match_conditions(intel_dp))
>+		goto unlock;
>+
>+	dev_priv->psr.busy_frontbuffer_bits = 0;
>+
>+	intel_psr_setup_vsc(intel_dp);
>+
>+	/* Avoid continuous PSR exit by masking memup and hpd */
>+	I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
>+		   EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
>+
>+	/* Enable PSR on the panel */
>+	intel_psr_enable_sink(intel_dp);
>+
>+	dev_priv->psr.enabled = intel_dp;
>+unlock:
>+	mutex_unlock(&dev_priv->psr.lock);
>+}
>+
>+void intel_psr_disable(struct intel_dp *intel_dp)
>+{
>+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>+	struct drm_device *dev = intel_dig_port->base.base.dev;
>+	struct drm_i915_private *dev_priv = dev->dev_private;
>+
>+	mutex_lock(&dev_priv->psr.lock);
>+	if (!dev_priv->psr.enabled) {
>+		mutex_unlock(&dev_priv->psr.lock);
>+		return;
>+	}
>+
>+	if (dev_priv->psr.active) {
>+		I915_WRITE(EDP_PSR_CTL(dev),
>+			   I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
>+
>+		/* Wait till PSR is idle */
>+		if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
>+			       EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
>+			DRM_ERROR("Timed out waiting for PSR Idle State\n");
>+
>+		dev_priv->psr.active = false;
>+	} else {
>+		WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
>+	}
>+
>+	dev_priv->psr.enabled = NULL;
>+	mutex_unlock(&dev_priv->psr.lock);
>+
>+	cancel_delayed_work_sync(&dev_priv->psr.work);
>+}
>+
>+static void intel_psr_work(struct work_struct *work)
>+{
>+	struct drm_i915_private *dev_priv =
>+		container_of(work, typeof(*dev_priv), psr.work.work);
>+	struct intel_dp *intel_dp = dev_priv->psr.enabled;
>+
>+	/* We have to make sure PSR is ready for re-enable
>+	 * otherwise it keeps disabled until next full enable/disable cycle.
>+	 * PSR might take some time to get fully disabled
>+	 * and be ready for re-enable.
>+	 */
>+	if (wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev_priv->dev)) &
>+		      EDP_PSR_STATUS_STATE_MASK) == 0, 50)) {
>+		DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
>+		return;
>+	}
>+
>+	mutex_lock(&dev_priv->psr.lock);
>+	intel_dp = dev_priv->psr.enabled;
>+
>+	if (!intel_dp)
>+		goto unlock;
>+
>+	/*
>+	 * The delayed work can race with an invalidate hence we need to
>+	 * recheck. Since psr_flush first clears this and then reschedules we
>+	 * won't ever miss a flush when bailing out here.
>+	 */
>+	if (dev_priv->psr.busy_frontbuffer_bits)
>+		goto unlock;
>+
>+	intel_psr_do_enable(intel_dp);
>+unlock:
>+	mutex_unlock(&dev_priv->psr.lock);
>+}
>+
>+static void intel_psr_exit(struct drm_device *dev)
>+{
>+	struct drm_i915_private *dev_priv = dev->dev_private;
>+
>+	if (dev_priv->psr.active) {
>+		u32 val = I915_READ(EDP_PSR_CTL(dev));
>+
>+		WARN_ON(!(val & EDP_PSR_ENABLE));
>+
>+		I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
>+
>+		dev_priv->psr.active = false;
>+	}
>+
>+}
>+
>+void intel_psr_invalidate(struct drm_device *dev,
>+			      unsigned frontbuffer_bits)
>+{
>+	struct drm_i915_private *dev_priv = dev->dev_private;
>+	struct drm_crtc *crtc;
>+	enum pipe pipe;
>+
>+	mutex_lock(&dev_priv->psr.lock);
>+	if (!dev_priv->psr.enabled) {
>+		mutex_unlock(&dev_priv->psr.lock);
>+		return;
>+	}
>+
>+	crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
>+	pipe = to_intel_crtc(crtc)->pipe;
>+
>+	intel_psr_exit(dev);
>+
>+	frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
>+
>+	dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
>+	mutex_unlock(&dev_priv->psr.lock);
>+}
>+
>+void intel_psr_flush(struct drm_device *dev,
>+			 unsigned frontbuffer_bits)
>+{
>+	struct drm_i915_private *dev_priv = dev->dev_private;
>+	struct drm_crtc *crtc;
>+	enum pipe pipe;
>+
>+	mutex_lock(&dev_priv->psr.lock);
>+	if (!dev_priv->psr.enabled) {
>+		mutex_unlock(&dev_priv->psr.lock);
>+		return;
>+	}
>+
>+	crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
>+	pipe = to_intel_crtc(crtc)->pipe;
>+	dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
>+
>+	/*
>+	 * On Haswell sprite plane updates don't result in a psr invalidating
>+	 * signal in the hardware. Which means we need to manually fake this in
>+	 * software for all flushes, not just when we've seen a preceding
>+	 * invalidation through frontbuffer rendering.
>+	 */
>+	if (IS_HASWELL(dev) &&
>+	    (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
>+		intel_psr_exit(dev);
>+
>+	if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
>+		schedule_delayed_work(&dev_priv->psr.work,
>+				      msecs_to_jiffies(100));
>+	mutex_unlock(&dev_priv->psr.lock);
>+}
>+
>+void intel_psr_init(struct drm_device *dev)
>+{
>+	struct drm_i915_private *dev_priv = dev->dev_private;
>+
>+	INIT_DELAYED_WORK(&dev_priv->psr.work, intel_psr_work);
>+	mutex_init(&dev_priv->psr.lock);
>+}
>--
>1.9.3
>
>_______________________________________________
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[PATCH 03/15] drm/i915: Add PSR docbook

[Rodrigo Vivi]

Let's document PSR a bit. No functional changes.

v2: Add actual DocBook entry and accept Daniel's improvements.

Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 Documentation/DocBook/drm.tmpl   |  5 +++
 drivers/gpu/drm/i915/intel_psr.c | 73 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 78 insertions(+)

diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl
index 9449cd6..a1168a8 100644
--- a/Documentation/DocBook/drm.tmpl
+++ b/Documentation/DocBook/drm.tmpl
@@ -3893,6 +3893,11 @@ int num_ioctls;</synopsis>
 !Idrivers/gpu/drm/i915/intel_audio.c
       </sect2>
       <sect2>
+	<title>Panel Self Refresh PSR (PSR/SRD)</title>
+!Pdrivers/gpu/drm/i915/intel_psr.c Panel Self Refresh (PSR/SRD)
+!Idrivers/gpu/drm/i915/intel_psr.c
+      </sect2>
+      <sect2>
         <title>DPIO</title>
 !Pdrivers/gpu/drm/i915/i915_reg.h DPIO
 	<table id="dpiox2">
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 7b3ed91..716b8a9 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -21,6 +21,36 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
+/**
+ * DOC: Panel Self Refresh (PSR/SRD)
+ *
+ * Since Haswell Display controller supports Panel Self-Refresh on display
+ * panels witch have a remote frame buffer (RFB) implemented according to PSR
+ * spec in eDP1.3. PSR feature allows the display to go to lower standby states
+ * when system is idle but display is on as it eliminates display refresh
+ * request to DDR memory completely as long as the frame buffer for that
+ * display is unchanged.
+ *
+ * Panel Self Refresh must be supported by both Hardware (source) and
+ * Panel (sink).
+ *
+ * PSR saves power by caching the framebuffer in the panel RFB, which allows us
+ * to power down the link and memory controller. For DSI panels the same idea
+ * is called "manual mode".
+ *
+ * The implementation uses the hardware-based PSR support which automatically
+ * enters/exits self-refresh mode. The hardware takes care of sending the
+ * required DP aux message and could even retrain the link (that part isn't
+ * enabled yet though). The hardware also keeps track of any frontbuffer
+ * changes to know when to exit self-refresh mode again. Unfortunately that
+ * part doesn't work too well, hence why the i915 PSR support uses the
+ * software frontbuffer tracking to make sure it doesn't miss a screen
+ * update. For this integration intel_psr_invalidate() and intel_psr_flush()
+ * get called by the frontbuffer tracking code. Note that because of locking
+ * issues the self-refresh re-enable code is done from a work queue, which
+ * must be correctly synchronized/cancelled when shutting down the pipe."
+ */
+
 #include <drm/drmP.h>
 
 #include "intel_drv.h"
@@ -217,6 +247,12 @@ static void intel_psr_do_enable(struct intel_dp *intel_dp)
 	dev_priv->psr.active = true;
 }
 
+/**
+ * intel_psr_enable - Enable PSR
+ * @intel_dp: Intel DP
+ *
+ * This function can only be called after the pipe is fully trained and enabled.
+ */
 void intel_psr_enable(struct intel_dp *intel_dp)
 {
 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
@@ -258,6 +294,12 @@ unlock:
 	mutex_unlock(&dev_priv->psr.lock);
 }
 
+/**
+ * intel_psr_disable - Disable PSR
+ * @intel_dp: Intel DP
+ *
+ * This function needs to be called before disabling pipe.
+ */
 void intel_psr_disable(struct intel_dp *intel_dp)
 {
 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
@@ -342,6 +384,18 @@ static void intel_psr_exit(struct drm_device *dev)
 
 }
 
+/**
+ * intel_psr_invalidate - Invalidade PSR
+ * @dev: DRM device
+ * @frontbuffer_bits: frontbuffer plane tracking bits
+ *
+ * Since the hardware frontbuffer tracking has gaps we need to integrate
+ * with the software frontbuffer tracking. This function gets called every
+ * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be
+ * disabled if the frontbuffer mask contains a buffer relevant to PSR.
+ *
+ * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits."
+ */
 void intel_psr_invalidate(struct drm_device *dev,
 			      unsigned frontbuffer_bits)
 {
@@ -366,6 +420,18 @@ void intel_psr_invalidate(struct drm_device *dev,
 	mutex_unlock(&dev_priv->psr.lock);
 }
 
+/**
+ * intel_psr_flush - Flush PSR
+ * @dev: DRM device
+ * @frontbuffer_bits: frontbuffer plane tracking bits
+ *
+ * Since the hardware frontbuffer tracking has gaps we need to integrate
+ * with the software frontbuffer tracking. This function gets called every
+ * time frontbuffer rendering has completed and flushed out to memory. PSR
+ * can be enabled again if no other frontbuffer relevant to PSR is dirty.
+ *
+ * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits.
+ */
 void intel_psr_flush(struct drm_device *dev,
 			 unsigned frontbuffer_bits)
 {
@@ -399,6 +465,13 @@ void intel_psr_flush(struct drm_device *dev,
 	mutex_unlock(&dev_priv->psr.lock);
 }
 
+/**
+ * intel_psr_init - Init basic PSR work and mutex.
+ * @dev: DRM device
+ *
+ * This function is  called only once at driver load to initialize basic
+ * PSR stuff.
+ */
 void intel_psr_init(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
-- 
1.9.3

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Re: [PATCH 03/15] drm/i915: Add PSR docbook

[R, Durgadoss]

>-----Original Message-----
>From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of Rodrigo Vivi
>Sent: Friday, November 14, 2014 10:22 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Daniel Vetter; Vivi, Rodrigo
>Subject: [Intel-gfx] [PATCH 03/15] drm/i915: Add PSR docbook
>
>Let's document PSR a bit. No functional changes.
>
>v2: Add actual DocBook entry and accept Daniel's improvements.
>
>Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
>Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>---
> Documentation/DocBook/drm.tmpl   |  5 +++
> drivers/gpu/drm/i915/intel_psr.c | 73 ++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 78 insertions(+)
>
>diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl
>index 9449cd6..a1168a8 100644
>--- a/Documentation/DocBook/drm.tmpl
>+++ b/Documentation/DocBook/drm.tmpl
>@@ -3893,6 +3893,11 @@ int num_ioctls;</synopsis>
> !Idrivers/gpu/drm/i915/intel_audio.c
>       </sect2>
>       <sect2>
>+	<title>Panel Self Refresh PSR (PSR/SRD)</title>
>+!Pdrivers/gpu/drm/i915/intel_psr.c Panel Self Refresh (PSR/SRD)
>+!Idrivers/gpu/drm/i915/intel_psr.c
>+      </sect2>
>+      <sect2>
>         <title>DPIO</title>
> !Pdrivers/gpu/drm/i915/i915_reg.h DPIO
> 	<table id="dpiox2">
>diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
>index 7b3ed91..716b8a9 100644
>--- a/drivers/gpu/drm/i915/intel_psr.c
>+++ b/drivers/gpu/drm/i915/intel_psr.c
>@@ -21,6 +21,36 @@
>  * DEALINGS IN THE SOFTWARE.
>  */
>
>+/**
>+ * DOC: Panel Self Refresh (PSR/SRD)
>+ *
>+ * Since Haswell Display controller supports Panel Self-Refresh on display
>+ * panels witch have a remote frame buffer (RFB) implemented according to PSR

s/witch/which ;)

oh, I see that this is already merged, anyway..

Thanks,
Durga

>+ * spec in eDP1.3. PSR feature allows the display to go to lower standby states
>+ * when system is idle but display is on as it eliminates display refresh
>+ * request to DDR memory completely as long as the frame buffer for that
>+ * display is unchanged.
>+ *
>+ * Panel Self Refresh must be supported by both Hardware (source) and
>+ * Panel (sink).
>+ *
>+ * PSR saves power by caching the framebuffer in the panel RFB, which allows us
>+ * to power down the link and memory controller. For DSI panels the same idea
>+ * is called "manual mode".
>+ *
>+ * The implementation uses the hardware-based PSR support which automatically
>+ * enters/exits self-refresh mode. The hardware takes care of sending the
>+ * required DP aux message and could even retrain the link (that part isn't
>+ * enabled yet though). The hardware also keeps track of any frontbuffer
>+ * changes to know when to exit self-refresh mode again. Unfortunately that
>+ * part doesn't work too well, hence why the i915 PSR support uses the
>+ * software frontbuffer tracking to make sure it doesn't miss a screen
>+ * update. For this integration intel_psr_invalidate() and intel_psr_flush()
>+ * get called by the frontbuffer tracking code. Note that because of locking
>+ * issues the self-refresh re-enable code is done from a work queue, which
>+ * must be correctly synchronized/cancelled when shutting down the pipe."
>+ */
>+
> #include <drm/drmP.h>
>
> #include "intel_drv.h"
>@@ -217,6 +247,12 @@ static void intel_psr_do_enable(struct intel_dp *intel_dp)
> 	dev_priv->psr.active = true;
> }
>
>+/**
>+ * intel_psr_enable - Enable PSR
>+ * @intel_dp: Intel DP
>+ *
>+ * This function can only be called after the pipe is fully trained and enabled.
>+ */
> void intel_psr_enable(struct intel_dp *intel_dp)
> {
> 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>@@ -258,6 +294,12 @@ unlock:
> 	mutex_unlock(&dev_priv->psr.lock);
> }
>
>+/**
>+ * intel_psr_disable - Disable PSR
>+ * @intel_dp: Intel DP
>+ *
>+ * This function needs to be called before disabling pipe.
>+ */
> void intel_psr_disable(struct intel_dp *intel_dp)
> {
> 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>@@ -342,6 +384,18 @@ static void intel_psr_exit(struct drm_device *dev)
>
> }
>
>+/**
>+ * intel_psr_invalidate - Invalidade PSR
>+ * @dev: DRM device
>+ * @frontbuffer_bits: frontbuffer plane tracking bits
>+ *
>+ * Since the hardware frontbuffer tracking has gaps we need to integrate
>+ * with the software frontbuffer tracking. This function gets called every
>+ * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be
>+ * disabled if the frontbuffer mask contains a buffer relevant to PSR.
>+ *
>+ * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits."
>+ */
> void intel_psr_invalidate(struct drm_device *dev,
> 			      unsigned frontbuffer_bits)
> {
>@@ -366,6 +420,18 @@ void intel_psr_invalidate(struct drm_device *dev,
> 	mutex_unlock(&dev_priv->psr.lock);
> }
>
>+/**
>+ * intel_psr_flush - Flush PSR
>+ * @dev: DRM device
>+ * @frontbuffer_bits: frontbuffer plane tracking bits
>+ *
>+ * Since the hardware frontbuffer tracking has gaps we need to integrate
>+ * with the software frontbuffer tracking. This function gets called every
>+ * time frontbuffer rendering has completed and flushed out to memory. PSR
>+ * can be enabled again if no other frontbuffer relevant to PSR is dirty.
>+ *
>+ * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits.
>+ */
> void intel_psr_flush(struct drm_device *dev,
> 			 unsigned frontbuffer_bits)
> {
>@@ -399,6 +465,13 @@ void intel_psr_flush(struct drm_device *dev,
> 	mutex_unlock(&dev_priv->psr.lock);
> }
>
>+/**
>+ * intel_psr_init - Init basic PSR work and mutex.
>+ * @dev: DRM device
>+ *
>+ * This function is  called only once at driver load to initialize basic
>+ * PSR stuff.
>+ */
> void intel_psr_init(struct drm_device *dev)
> {
> 	struct drm_i915_private *dev_priv = dev->dev_private;
>--
>1.9.3
>
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[PATCH 04/15] drm/i915: Parse VBT PSR block.

[Rodrigo Vivi]

PSR (aka SRD) block is defined at VBT and currently being used.
Mainly/At-least to configure the amount of idle_frames require to get
back to PSR Entry.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h   | 16 ++++++++++++++
 drivers/gpu/drm/i915/intel_bios.c | 45 +++++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_bios.h | 22 ++++++++++++++++++-
 3 files changed, 82 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3f3035c..573f084 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1310,6 +1310,13 @@ enum drrs_support_type {
 	SEAMLESS_DRRS_SUPPORT = 2
 };
 
+enum psr_lines_to_wait {
+	PSR_0_LINES_TO_WAIT = 0,
+	PSR_1_LINE_TO_WAIT,
+	PSR_4_LINES_TO_WAIT,
+	PSR_8_LINES_TO_WAIT
+};
+
 struct intel_vbt_data {
 	struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
 	struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
@@ -1339,6 +1346,15 @@ struct intel_vbt_data {
 	struct edp_power_seq edp_pps;
 
 	struct {
+		bool full_link;
+		bool require_aux_wakeup;
+		int idle_frames;
+		enum psr_lines_to_wait lines_to_wait;
+		int tp1_wakeup_time;
+		int tp2_tp3_wakeup_time;
+	} psr;
+
+	struct {
 		u16 pwm_freq_hz;
 		bool present;
 		bool active_low_pwm;
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index a4bd90f..3f17825 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -664,6 +664,50 @@ parse_edp(struct drm_i915_private *dev_priv, struct bdb_header *bdb)
 	}
 }
 
+static void
+parse_psr(struct drm_i915_private *dev_priv, struct bdb_header *bdb)
+{
+	struct bdb_psr *psr;
+	struct psr_table *psr_table;
+
+	psr = find_section(bdb, BDB_PSR);
+	if (!psr) {
+		DRM_DEBUG_KMS("No PSR BDB found.\n");
+		return;
+	}
+
+	psr_table = &psr->psr_table[panel_type];
+
+	dev_priv->vbt.psr.full_link = psr_table->full_link;
+	dev_priv->vbt.psr.require_aux_wakeup = psr_table->require_aux_to_wakeup;
+
+	/* Allowed VBT values goes from 0 to 15 */
+	dev_priv->vbt.psr.idle_frames = psr_table->idle_frames < 0 ? 0 :
+		psr_table->idle_frames > 15 ? 15 : psr_table->idle_frames;
+
+	switch (psr_table->lines_to_wait) {
+	case 0:
+		dev_priv->vbt.psr.lines_to_wait = PSR_0_LINES_TO_WAIT;
+		break;
+	case 1:
+		dev_priv->vbt.psr.lines_to_wait = PSR_1_LINE_TO_WAIT;
+		break;
+	case 2:
+		dev_priv->vbt.psr.lines_to_wait = PSR_4_LINES_TO_WAIT;
+		break;
+	case 3:
+		dev_priv->vbt.psr.lines_to_wait = PSR_8_LINES_TO_WAIT;
+		break;
+	default:
+		DRM_DEBUG_KMS("VBT has unknown PSR lines to wait %u\n",
+			      psr_table->lines_to_wait);
+		break;
+	}
+
+	dev_priv->vbt.psr.tp1_wakeup_time = psr_table->tp1_wakeup_time;
+	dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table->tp2_tp3_wakeup_time;
+}
+
 static u8 *goto_next_sequence(u8 *data, int *size)
 {
 	u16 len;
@@ -1241,6 +1285,7 @@ intel_parse_bios(struct drm_device *dev)
 	parse_device_mapping(dev_priv, bdb);
 	parse_driver_features(dev_priv, bdb);
 	parse_edp(dev_priv, bdb);
+	parse_psr(dev_priv, bdb);
 	parse_mipi(dev_priv, bdb);
 	parse_ddi_ports(dev_priv, bdb);
 
diff --git a/drivers/gpu/drm/i915/intel_bios.h b/drivers/gpu/drm/i915/intel_bios.h
index 7603765..de01167 100644
--- a/drivers/gpu/drm/i915/intel_bios.h
+++ b/drivers/gpu/drm/i915/intel_bios.h
@@ -80,7 +80,7 @@ struct vbios_data {
 #define BDB_EXT_MMIO_REGS	  6
 #define BDB_SWF_IO		  7
 #define BDB_SWF_MMIO		  8
-#define BDB_DOT_CLOCK_TABLE	  9
+#define BDB_PSR			  9
 #define BDB_MODE_REMOVAL_TABLE	 10
 #define BDB_CHILD_DEVICE_TABLE	 11
 #define BDB_DRIVER_FEATURES	 12
@@ -556,6 +556,26 @@ struct bdb_edp {
 	u16 edp_t3_optimization;
 } __packed;
 
+struct psr_table {
+	/* Feature bits */
+	u8 full_link:1;
+	u8 require_aux_to_wakeup:1;
+	u8 feature_bits_rsvd:6;
+
+	/* Wait times */
+	u8 idle_frames:4;
+	u8 lines_to_wait:3;
+	u8 wait_times_rsvd:1;
+
+	/* TP wake up time in multiple of 100 */
+	u16 tp1_wakeup_time;
+	u16 tp2_tp3_wakeup_time;
+} __packed;
+
+struct bdb_psr {
+	struct psr_table psr_table[16];
+} __packed;
+
 void intel_setup_bios(struct drm_device *dev);
 int intel_parse_bios(struct drm_device *dev);
 
-- 
1.9.3

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Re: [PATCH 04/15] drm/i915: Parse VBT PSR block.

[Damien Lespiau]

On Fri, Nov 14, 2014 at 08:52:30AM -0800, Rodrigo Vivi wrote:
> +struct psr_table {
> +	/* Feature bits */
> +	u8 full_link:1;
> +	u8 require_aux_to_wakeup:1;
> +	u8 feature_bits_rsvd:6;
> +
> +	/* Wait times */
> +	u8 idle_frames:4;
> +	u8 lines_to_wait:3;
> +	u8 wait_times_rsvd:1;
> +
> +	/* TP wake up time in multiple of 100 */
> +	u16 tp1_wakeup_time;
> +	u16 tp2_tp3_wakeup_time;
> +} __packed;

...

> +	/* Allowed VBT values goes from 0 to 15 */
> +	dev_priv->vbt.psr.idle_frames = psr_table->idle_frames < 0 ? 0 :
> +		psr_table->idle_frames > 15 ? 15 : psr_table->idle_frames;


smatch gives a warning here saying those conditions are always true.
psr_table->idle_frames being 4 bits in a bitfield, we can see that
smatch may well be right.

-- 
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[PATCH 05/15] drm/i915: HSW/BDW PSR Set idle_frames = VBT + 1

[Rodrigo Vivi]

Let's use VBT + 1 now we parse it.

v2: fix subject

v3: rebase over intel_psr and without counting on previous fix

Cc: Arthur Runyan <arthur.j.runyan@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_psr.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 716b8a9..576568e 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -163,7 +163,12 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp)
 	struct drm_device *dev = dig_port->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	uint32_t max_sleep_time = 0x1f;
-	uint32_t idle_frames = 1;
+	/* Lately it was identified that depending on panel idle frame count
+	 * calculated at HW can be off by 1. So let's use what came
+	 * from VBT + 1 and at minimum 2 to be on the safe side.
+	 */
+	uint32_t idle_frames = dev_priv->vbt.psr.idle_frames ?
+			       dev_priv->vbt.psr.idle_frames + 1 : 2;
 	uint32_t val = 0x0;
 	const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
 	bool only_standby = false;
-- 
1.9.3

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[PATCH 06/15] drm/i915: PSR get full link off x standby from VBT

[Rodrigo Vivi]

OEMs can specify if full_link might be always enabled, i.e. only_standby
over VBT.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_psr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 576568e..e706c9d 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -120,7 +120,7 @@ static void intel_psr_enable_sink(struct intel_dp *intel_dp)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	uint32_t aux_clock_divider;
 	int precharge = 0x3;
-	bool only_standby = false;
+	bool only_standby = dev_priv->vbt.psr.full_link;
 	static const uint8_t aux_msg[] = {
 		[0] = DP_AUX_NATIVE_WRITE << 4,
 		[1] = DP_SET_POWER >> 8,
-- 
1.9.3

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Re: [PATCH 06/15] drm/i915: PSR get full link off x standby from VBT

[R, Durgadoss]

>-----Original Message-----
>From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of Rodrigo Vivi
>Sent: Friday, November 14, 2014 10:23 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Vivi, Rodrigo
>Subject: [Intel-gfx] [PATCH 06/15] drm/i915: PSR get full link off x standby from VBT
>
>OEMs can specify if full_link might be always enabled, i.e. only_standby
>over VBT.
>
>Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

I have not looked at/tried these VBT bits myself. If that's ok then,

For patches 4,5,6:
Reviewed-by: Durgadoss R <durgadoss.r@intel.com>

Thanks,
Durga

>---
> drivers/gpu/drm/i915/intel_psr.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
>index 576568e..e706c9d 100644
>--- a/drivers/gpu/drm/i915/intel_psr.c
>+++ b/drivers/gpu/drm/i915/intel_psr.c
>@@ -120,7 +120,7 @@ static void intel_psr_enable_sink(struct intel_dp *intel_dp)
> 	struct drm_i915_private *dev_priv = dev->dev_private;
> 	uint32_t aux_clock_divider;
> 	int precharge = 0x3;
>-	bool only_standby = false;
>+	bool only_standby = dev_priv->vbt.psr.full_link;
> 	static const uint8_t aux_msg[] = {
> 		[0] = DP_AUX_NATIVE_WRITE << 4,
> 		[1] = DP_SET_POWER >> 8,
>--
>1.9.3
>
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Re: [PATCH 06/15] drm/i915: PSR get full link off x standby from VBT

[Daniel Vetter]

On Tue, Nov 18, 2014 at 06:21:18PM +0000, R, Durgadoss wrote:
> 
> >-----Original Message-----
> >From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of Rodrigo Vivi
> >Sent: Friday, November 14, 2014 10:23 PM
> >To: intel-gfx@lists.freedesktop.org
> >Cc: Vivi, Rodrigo
> >Subject: [Intel-gfx] [PATCH 06/15] drm/i915: PSR get full link off x standby from VBT
> >
> >OEMs can specify if full_link might be always enabled, i.e. only_standby
> >over VBT.
> >
> >Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> 
> I have not looked at/tried these VBT bits myself. If that's ok then,

I'm confused: Do you mean you didn't work yet with these vbt entries or
that you don't have access to the spec? If the later please fix that asap
- the important part in reviewing vbt patches is to make sure at least 2
person have the right spec ;-)

Thanks, Daniel
-- 
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Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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[PATCH 07/15] drm/i915: PSR skip aux on wake up as defined by VBT.

[Rodrigo Vivi]

Let's always skip aux on exit unless specified at VBT we need it.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_psr.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index e706c9d..4cfe7a4 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -180,11 +180,13 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp)
 		val |= EDP_PSR_LINK_STANDBY;
 		val |= EDP_PSR_TP2_TP3_TIME_0us;
 		val |= EDP_PSR_TP1_TIME_0us;
-		val |= EDP_PSR_SKIP_AUX_EXIT;
 		val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
 	} else
 		val |= EDP_PSR_LINK_DISABLE;
 
+	if (!dev_priv->vbt.psr.require_aux_wakeup)
+		val |= EDP_PSR_SKIP_AUX_EXIT;
+
 	I915_WRITE(EDP_PSR_CTL(dev), val |
 		   (IS_BROADWELL(dev) ? 0 : link_entry_time) |
 		   max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
-- 
1.9.3

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Re: [PATCH 07/15] drm/i915: PSR skip aux on wake up as defined by VBT.

[Rodrigo Vivi]

Please ignore this patch for now.

On SDP platforms VBT isn't set so we get a false positive on this
value causing frozen screens.

On Fri, Nov 14, 2014 at 8:52 AM, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> Let's always skip aux on exit unless specified at VBT we need it.
>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_psr.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index e706c9d..4cfe7a4 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -180,11 +180,13 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp)
>                 val |= EDP_PSR_LINK_STANDBY;
>                 val |= EDP_PSR_TP2_TP3_TIME_0us;
>                 val |= EDP_PSR_TP1_TIME_0us;
> -               val |= EDP_PSR_SKIP_AUX_EXIT;
>                 val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
>         } else
>                 val |= EDP_PSR_LINK_DISABLE;
>
> +       if (!dev_priv->vbt.psr.require_aux_wakeup)
> +               val |= EDP_PSR_SKIP_AUX_EXIT;
> +
>         I915_WRITE(EDP_PSR_CTL(dev), val |
>                    (IS_BROADWELL(dev) ? 0 : link_entry_time) |
>                    max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
> --
> 1.9.3
>
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-- 
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[PATCH 08/15] drm/i915: remove PSR BDW single frame update.

[Rodrigo Vivi]

Single frame update is a feature available on BDW for PSR that allows
Source to send Sink only one frame and get it updated. Usually useful
when page fliping. However with our frontbuffer tracking where we force
psr exit on flips we don't need this feature.

Also after it got added here many workaround was added to documentation
to mask some bits when using single frame update. So the safest thing
is to just stop using it.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_psr.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 4cfe7a4..66d24c2 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -180,7 +180,6 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp)
 		val |= EDP_PSR_LINK_STANDBY;
 		val |= EDP_PSR_TP2_TP3_TIME_0us;
 		val |= EDP_PSR_TP1_TIME_0us;
-		val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
 	} else
 		val |= EDP_PSR_LINK_DISABLE;
 
-- 
1.9.3

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Re: [PATCH 08/15] drm/i915: remove PSR BDW single frame update.

[R, Durgadoss]

>-----Original Message-----
>From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of Rodrigo Vivi
>Sent: Friday, November 14, 2014 10:23 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Vivi, Rodrigo
>Subject: [Intel-gfx] [PATCH 08/15] drm/i915: remove PSR BDW single frame update.
>
>Single frame update is a feature available on BDW for PSR that allows
>Source to send Sink only one frame and get it updated. Usually useful
>when page fliping. However with our frontbuffer tracking where we force

flipping

>psr exit on flips we don't need this feature.
>
>Also after it got added here many workaround was added to documentation
>to mask some bits when using single frame update. So the safest thing
>is to just stop using it.
>
>Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Again, I have not looked at the BDW spec. But the commit message
sounds reasonable. So,

Reviewed-by: Durgadoss R <durgadoss.r@intel.com>

Thanks,
Durga

>---
> drivers/gpu/drm/i915/intel_psr.c | 1 -
> 1 file changed, 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
>index 4cfe7a4..66d24c2 100644
>--- a/drivers/gpu/drm/i915/intel_psr.c
>+++ b/drivers/gpu/drm/i915/intel_psr.c
>@@ -180,7 +180,6 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp)
> 		val |= EDP_PSR_LINK_STANDBY;
> 		val |= EDP_PSR_TP2_TP3_TIME_0us;
> 		val |= EDP_PSR_TP1_TIME_0us;
>-		val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
> 	} else
> 		val |= EDP_PSR_LINK_DISABLE;
>
>--
>1.9.3
>
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[PATCH] drm/i915: remove PSR BDW single frame update.

[Rodrigo Vivi]

Single frame update is a feature available on BDW for PSR that allows
Source to send Sink only one frame and get it updated. Usually useful
when page flipping. However with our frontbuffer tracking where we force
psr exit on flips we don't need this feature.

Also after it got added here many workaround was added to documentation
to mask some bits when using single frame update. So the safest thing
is to just stop using it.

v2: Rebase after removing skip aux one and fixing typo on commit message.

Reviewed-by: Durgadoss R <durgadoss.r@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_psr.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index e706c9d..843762a 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -181,7 +181,6 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp)
 		val |= EDP_PSR_TP2_TP3_TIME_0us;
 		val |= EDP_PSR_TP1_TIME_0us;
 		val |= EDP_PSR_SKIP_AUX_EXIT;
-		val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
 	} else
 		val |= EDP_PSR_LINK_DISABLE;
 
-- 
1.9.3

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Re: [PATCH] drm/i915: remove PSR BDW single frame update.

[shuang.he]

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                 -2              369/369              367/369
ILK              +2-19              384/386              367/386
SNB                 -9              459/459              450/459
IVB                 -32              535/545              503/545
BYT                 -1              290/290              289/290
HSW                 -40              592/592              552/592
BDW                 -20              302/302              282/302
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
PNV  igt_drv_hangman_error-state-capture-render      TIMEOUT(27, M25M7M23)PASS(10, M23M25M7)      TIMEOUT(1, M25)PASS(3, M25)
PNV  igt_drv_missed_irq_hang      TIMEOUT(36, M23M25M7)PASS(1, M23)      TIMEOUT(1, M25)PASS(3, M25)
ILK  igt_drv_hangman_error-state-basic      TIMEOUT(18, M37M26)PASS(4, M26)      TIMEOUT(1, M26)PASS(3, M26)
ILK  igt_drv_hangman_error-state-capture-bsd      TIMEOUT(7, M26M37)PASS(1, M26)      TIMEOUT(1, M26)PASS(3, M26)
ILK  igt_drv_hangman_error-state-capture-render      PASS(1, M26)      TIMEOUT(1, M26)PASS(3, M26)
ILK  igt_drv_missed_irq_hang      PASS(1, M26)      TIMEOUT(1, M26)PASS(3, M26)
ILK  igt_gem_reset_stats_ban-render      PASS(4, M26)      TIMEOUT(1, M26)PASS(3, M26)
ILK  igt_gem_reset_stats_close-pending-fork-render      PASS(1, M26)      TIMEOUT(1, M26)PASS(3, M26)
ILK  igt_gem_reset_stats_close-pending-fork-reverse-render      PASS(1, M26)      TIMEOUT(1, M26)PASS(3, M26)
ILK  igt_gem_reset_stats_close-pending-render      PASS(1, M26)      TIMEOUT(1, M26)PASS(3, M26)
ILK  igt_gem_reset_stats_reset-count-render      PASS(1, M26)      TIMEOUT(1, M26)PASS(3, M26)
ILK  igt_gem_reset_stats_reset-stats-render      PASS(1, M26)      TIMEOUT(1, M26)PASS(3, M26)
ILK  igt_gem_workarounds_reset      PASS(1, M26)      TIMEOUT(1, M26)PASS(3, M26)
ILK  igt_kms_flip_nonexisting-fb      DMESG_WARN(1, M26)      PASS(4, M26)
ILK  igt_kms_flip_rcs-wf_vblank-vs-dpms-interruptible      PASS(1, M26)      DMESG_WARN(3, M26)PASS(1, M26)
ILK  igt_kms_render_direct-render      PASS(1, M26)      DMESG_WARN(2, M26)PASS(2, M26)
ILK  igt_kms_flip_bcs-flip-vs-modeset-interruptible      DMESG_WARN(1, M26)PASS(3, M26)      DMESG_WARN(3, M26)PASS(1, M26)
ILK  igt_kms_flip_busy-flip-interruptible      PASS(1, M26)      DMESG_WARN(1, M26)PASS(3, M26)
ILK  igt_kms_flip_flip-vs-panning      NSPT(1, M26)      PASS(4, M26)
ILK  igt_kms_flip_flip-vs-rmfb-interruptible      PASS(1, M26)      DMESG_WARN(3, M26)PASS(1, M26)
ILK  igt_kms_flip_plain-flip-ts-check-interruptible      PASS(1, M26)      DMESG_WARN(1, M26)PASS(3, M26)
ILK  igt_kms_flip_vblank-vs-hang      PASS(1, M26)      TIMEOUT(1, M26)PASS(3, M26)
ILK  igt_kms_flip_vblank-vs-hang-interruptible      PASS(1, M26)      TIMEOUT(1, M26)PASS(3, M26)
SNB  igt_drv_hangman_error-state-basic      TIMEOUT(24, M35M22)PASS(1, M35)      TIMEOUT(1, M35)PASS(3, M35)
SNB  igt_drv_hangman_error-state-capture-bsd      TIMEOUT(24, M35M22)PASS(1, M35)      TIMEOUT(1, M35)PASS(3, M35)
SNB  igt_drv_hangman_error-state-capture-render      TIMEOUT(8, M35M22)PASS(1, M35)      TIMEOUT(1, M35)PASS(3, M35)
SNB  igt_drv_missed_irq_hang      PASS(1, M35)      TIMEOUT(1, M35)PASS(3, M35)
SNB  igt_gem_reset_stats_reset-count-render      PASS(1, M35)      TIMEOUT(1, M35)PASS(3, M35)
SNB  igt_gem_reset_stats_unrelated-ctx-render      PASS(1, M35)      TIMEOUT(1, M35)PASS(3, M35)
SNB  igt_kms_pipe_crc_basic_hang-read-crc-pipe-A      PASS(4, M35)      TIMEOUT(1, M35)PASS(3, M35)
SNB  igt_kms_pipe_crc_basic_hang-read-crc-pipe-B      PASS(1, M35)      TIMEOUT(1, M35)PASS(3, M35)
SNB  igt_pm_rps_min-max-config-idle      PASS(1, M35)      FAIL(1, M35)PASS(3, M35)
IVB  igt_drv_hangman_error-state-basic      TIMEOUT(21, M34M21M4)PASS(4, M21)      TIMEOUT(1, M21)PASS(3, M21)
IVB  igt_drv_hangman_error-state-capture-blt      TIMEOUT(20, M34M21M4)PASS(1, M21)      TIMEOUT(1, M21)PASS(3, M21)
IVB  igt_drv_hangman_error-state-capture-bsd      TIMEOUT(1, M34)PASS(1, M21)      TIMEOUT(1, M21)PASS(3, M21)
IVB  igt_drv_hangman_error-state-capture-render      PASS(1, M21)      TIMEOUT(1, M21)PASS(3, M21)
IVB  igt_drv_missed_irq_hang      PASS(1, M21)      TIMEOUT(1, M21)PASS(3, M21)
IVB  igt_gem_bad_reloc_negative-reloc      PASS(1, M21)      NSPT(1, M21)PASS(3, M21)
IVB  igt_gem_reset_stats_ban-ctx-render      DMESG_WARN(2, M21)PASS(2, M21)      TIMEOUT(1, M21)PASS(3, M21)
IVB  igt_gem_reset_stats_ban-render      DMESG_WARN(2, M21)PASS(2, M21)      TIMEOUT(1, M21)PASS(3, M21)
IVB  igt_gem_reset_stats_close-pending-blt      PASS(1, M21)      TIMEOUT(1, M21)PASS(3, M21)
IVB  igt_gem_reset_stats_close-pending-bsd      PASS(1, M21)      TIMEOUT(1, M21)PASS(3, M21)
IVB  igt_gem_reset_stats_close-pending-ctx-render      PASS(1, M21)      TIMEOUT(1, M21)PASS(3, M21)
IVB  igt_gem_reset_stats_close-pending-fork-blt      PASS(1, M21)      TIMEOUT(1, M21)PASS(3, M21)
IVB  igt_gem_reset_stats_close-pending-fork-bsd      PASS(1, M21)      TIMEOUT(1, M21)PASS(3, M21)
IVB  igt_gem_reset_stats_close-pending-fork-render      PASS(1, M21)      TIMEOUT(1, M21)PASS(3, M21)
IVB  igt_gem_reset_stats_close-pending-fork-reverse-blt      PASS(1, M21)      TIMEOUT(1, M21)PASS(3, M21)
IVB  igt_gem_reset_stats_close-pending-fork-reverse-bsd      PASS(1, M21)      TIMEOUT(1, M21)PASS(3, M21)
IVB  igt_gem_reset_stats_close-pending-fork-reverse-render      PASS(1, M21)      TIMEOUT(1, M21)PASS(3, M21)
IVB  igt_gem_reset_stats_close-pending-render      PASS(1, M21)      TIMEOUT(1, M21)PASS(3, M21)
IVB  igt_gem_reset_stats_reset-count-blt      PASS(1, M21)      TIMEOUT(1, M21)PASS(3, M21)
IVB  igt_gem_reset_stats_reset-count-bsd      PASS(1, M21)      TIMEOUT(1, M21)PASS(3, M21)
IVB  igt_gem_reset_stats_reset-count-ctx-render      PASS(1, M21)      TIMEOUT(1, M21)PASS(3, M21)
IVB  igt_gem_reset_stats_reset-count-render      PASS(1, M21)      TIMEOUT(1, M21)PASS(3, M21)
IVB  igt_gem_reset_stats_reset-stats-blt      PASS(1, M21)      TIMEOUT(1, M21)PASS(3, M21)
IVB  igt_gem_reset_stats_reset-stats-bsd      PASS(1, M21)      TIMEOUT(1, M21)PASS(3, M21)
IVB  igt_gem_reset_stats_reset-stats-ctx-render      PASS(1, M21)      TIMEOUT(1, M21)PASS(3, M21)
IVB  igt_gem_reset_stats_reset-stats-render      PASS(1, M21)      TIMEOUT(1, M21)PASS(3, M21)
IVB  igt_gem_reset_stats_unrelated-ctx-render      PASS(1, M21)      TIMEOUT(1, M21)PASS(3, M21)
IVB  igt_gem_workarounds_reset      PASS(4, M21)      TIMEOUT(1, M21)PASS(3, M21)
IVB  igt_kms_pipe_crc_basic_hang-read-crc-pipe-A      PASS(1, M21)      TIMEOUT(1, M21)PASS(3, M21)
IVB  igt_kms_pipe_crc_basic_hang-read-crc-pipe-B      PASS(1, M21)      TIMEOUT(1, M21)PASS(3, M21)
IVB  igt_kms_pipe_crc_basic_hang-read-crc-pipe-C      PASS(1, M21)      TIMEOUT(1, M21)PASS(3, M21)
IVB  igt_pm_rps_min-max-config-idle      PASS(1, M21)      FAIL(1, M21)PASS(3, M21)
BYT  igt_drv_missed_irq_hang      TIMEOUT(38, M36M31)PASS(2, M36M31)      TIMEOUT(1, M31)PASS(3, M31)
HSW  igt_drv_hangman_error-state-basic      TIMEOUT(13, M20M40)PASS(4, M19M40)      TIMEOUT(1, M20)PASS(3, M20)
HSW  igt_drv_hangman_error-state-capture-blt      TIMEOUT(7, M20M40)PASS(1, M19)      TIMEOUT(1, M20)PASS(3, M20)
HSW  igt_drv_hangman_error-state-capture-bsd      PASS(1, M19)      TIMEOUT(1, M20)PASS(3, M20)
HSW  igt_drv_hangman_error-state-capture-render      PASS(1, M19)      TIMEOUT(1, M20)PASS(3, M20)
HSW  igt_drv_hangman_error-state-capture-vebox      PASS(1, M19)      TIMEOUT(1, M20)PASS(3, M20)
HSW  igt_gem_reset_stats_ban-ctx-render      PASS(1, M19)      TIMEOUT(1, M20)PASS(3, M20)
HSW  igt_gem_reset_stats_ban-render      PASS(1, M19)      TIMEOUT(1, M20)PASS(3, M20)
HSW  igt_gem_reset_stats_ban-vebox      PASS(1, M19)      TIMEOUT(1, M20)PASS(3, M20)
HSW  igt_gem_reset_stats_close-pending-blt      PASS(1, M19)      TIMEOUT(1, M20)PASS(3, M20)
HSW  igt_gem_reset_stats_close-pending-bsd      PASS(1, M19)      TIMEOUT(1, M20)PASS(3, M20)
HSW  igt_gem_reset_stats_close-pending-ctx-render      PASS(1, M19)      TIMEOUT(1, M20)PASS(3, M20)
HSW  igt_gem_reset_stats_close-pending-fork-blt      PASS(1, M19)      TIMEOUT(1, M20)PASS(3, M20)
HSW  igt_gem_reset_stats_close-pending-fork-bsd      PASS(1, M19)      TIMEOUT(1, M20)PASS(3, M20)
HSW  igt_gem_reset_stats_close-pending-fork-render      PASS(1, M19)      TIMEOUT(1, M20)PASS(3, M20)
HSW  igt_gem_reset_stats_close-pending-fork-reverse-blt      PASS(1, M19)      TIMEOUT(1, M20)PASS(3, M20)
HSW  igt_gem_reset_stats_close-pending-fork-reverse-bsd      PASS(1, M19)      TIMEOUT(1, M20)PASS(3, M20)
HSW  igt_gem_reset_stats_close-pending-fork-reverse-render      PASS(1, M19)      TIMEOUT(1, M20)PASS(3, M20)
HSW  igt_gem_reset_stats_close-pending-fork-reverse-vebox      PASS(1, M19)      TIMEOUT(1, M20)PASS(3, M20)
HSW  igt_gem_reset_stats_close-pending-render      PASS(1, M19)      TIMEOUT(1, M20)PASS(3, M20)
HSW  igt_gem_reset_stats_close-pending-vebox      PASS(1, M19)      TIMEOUT(1, M20)PASS(3, M20)
HSW  igt_gem_reset_stats_reset-count-blt      PASS(1, M19)      TIMEOUT(1, M20)PASS(3, M20)
HSW  igt_gem_reset_stats_reset-count-bsd      PASS(1, M19)      TIMEOUT(1, M20)PASS(3, M20)
HSW  igt_gem_reset_stats_reset-count-ctx-render      PASS(1, M19)      TIMEOUT(1, M20)PASS(3, M20)
HSW  igt_gem_reset_stats_reset-count-render      PASS(1, M19)      TIMEOUT(1, M20)PASS(3, M20)
HSW  igt_gem_reset_stats_reset-count-vebox      PASS(1, M19)      TIMEOUT(1, M20)PASS(3, M20)
HSW  igt_gem_reset_stats_reset-stats-blt      PASS(1, M19)      TIMEOUT(1, M20)PASS(3, M20)
HSW  igt_gem_reset_stats_reset-stats-bsd      PASS(1, M19)      TIMEOUT(1, M20)PASS(3, M20)
HSW  igt_gem_reset_stats_reset-stats-ctx-render      PASS(1, M19)      TIMEOUT(1, M20)PASS(3, M20)
HSW  igt_gem_reset_stats_reset-stats-render      PASS(1, M19)      TIMEOUT(1, M20)PASS(2, M20)
HSW  igt_gem_reset_stats_reset-stats-vebox      PASS(1, M19)      TIMEOUT(1, M20)PASS(3, M20)
HSW  igt_gem_workarounds_reset      PASS(4, M19M40)      TIMEOUT(1, M20)PASS(3, M20)
HSW  igt_kms_pipe_crc_basic_hang-read-crc-pipe-A      PASS(1, M19)      TIMEOUT(1, M20)PASS(3, M20)
HSW  igt_kms_pipe_crc_basic_hang-read-crc-pipe-B      PASS(1, M19)      TIMEOUT(1, M20)PASS(3, M20)
HSW  igt_kms_pipe_crc_basic_hang-read-crc-pipe-C      PASS(1, M19)      TIMEOUT(1, M20)PASS(3, M20)
HSW  igt_pm_rps_min-max-config-idle      PASS(4, M19M40)      FAIL(1, M20)PASS(3, M20)
HSW  igt_drv_missed_irq_hang      PASS(1, M19)      TIMEOUT(1, M20)PASS(3, M20)
HSW  igt_gem_reset_stats_ban-bsd      PASS(4, M19M40)      TIMEOUT(1, M20)PASS(3, M20)
HSW  igt_kms_flip_flip-vs-modeset-vs-hang      PASS(1, M19)      TIMEOUT(1, M20)PASS(3, M20)
HSW  igt_kms_flip_flip-vs-modeset-vs-hang-interruptible      PASS(1, M19)      TIMEOUT(1, M20)PASS(3, M20)
HSW  igt_kms_flip_flip-vs-panning-vs-hang      PASS(1, M19)      TIMEOUT(1, M20)PASS(3, M20)
BDW  igt_drv_hangman_error-state-basic      TIMEOUT(18, M28M30)PASS(4, M28M30)      TIMEOUT(1, M30)PASS(3, M30)
BDW  igt_drv_hangman_error-state-capture-blt      TIMEOUT(17, M28M30)PASS(1, M28)      TIMEOUT(1, M30)PASS(3, M30)
BDW  igt_drv_hangman_error-state-capture-bsd      TIMEOUT(1, M28)PASS(1, M28)      TIMEOUT(1, M30)PASS(3, M30)
BDW  igt_drv_hangman_error-state-capture-render      PASS(1, M28)      TIMEOUT(1, M30)PASS(3, M30)
BDW  igt_drv_hangman_error-state-capture-vebox      PASS(1, M28)      TIMEOUT(1, M30)PASS(3, M30)
BDW  igt_gem_reset_stats_ban-blt      PASS(1, M28)      TIMEOUT(1, M30)PASS(3, M30)
BDW  igt_gem_reset_stats_ban-bsd      PASS(1, M28)      TIMEOUT(1, M30)PASS(3, M30)
BDW  igt_gem_reset_stats_ban-ctx-render      PASS(1, M28)      TIMEOUT(1, M30)PASS(3, M30)
BDW  igt_gem_reset_stats_ban-render      PASS(1, M28)      TIMEOUT(1, M30)PASS(3, M30)
BDW  igt_gem_reset_stats_ban-vebox      PASS(1, M28)      TIMEOUT(1, M30)PASS(3, M30)
BDW  igt_gem_reset_stats_close-pending-blt      PASS(1, M28)      TIMEOUT(1, M30)PASS(3, M30)
BDW  igt_gem_reset_stats_close-pending-bsd      PASS(1, M28)      TIMEOUT(1, M30)PASS(3, M30)
BDW  igt_gem_reset_stats_close-pending-ctx-render      PASS(1, M28)      TIMEOUT(1, M30)PASS(3, M30)
BDW  igt_gem_reset_stats_close-pending-fork-blt      PASS(1, M28)      TIMEOUT(1, M30)PASS(3, M30)
BDW  igt_gem_reset_stats_close-pending-fork-bsd      PASS(1, M28)      TIMEOUT(1, M30)PASS(3, M30)
BDW  igt_gem_reset_stats_close-pending-fork-render      PASS(1, M28)      TIMEOUT(1, M30)PASS(3, M30)
BDW  igt_gem_reset_stats_close-pending-fork-reverse-blt      PASS(1, M28)      TIMEOUT(1, M30)PASS(3, M30)
BDW  igt_gem_reset_stats_close-pending-fork-reverse-bsd      PASS(1, M28)      TIMEOUT(1, M30)PASS(3, M30)
BDW  igt_gem_reset_stats_close-pending-fork-reverse-render      PASS(1, M28)      TIMEOUT(1, M30)PASS(3, M30)
BDW  igt_gem_reset_stats_close-pending-fork-reverse-vebox      PASS(1, M28)      TIMEOUT(1, M30)PASS(3, M30)
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[PATCH 09/15] drm/i915: Fix intel_psr_is_enabled function and document it.

[Rodrigo Vivi]

This function can be used to check if psr feature got enabled.
However on HSW and BDW we currently force psr exit by disabling
EDP_PSR_ENABLE bit at EDP_PSR_CTL(dev). So this function was actually
returning the active/inactive state that is different from the enable/disable
meaning and had the risk of false negative.

So let's just return the presence of intel_dp at dev_priv->psr.enabled.

It would be more easy to just check this presence directly but let's keep
it more organized.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_psr.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 66d24c2..c296a89 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -61,6 +61,16 @@ static bool is_edp_psr(struct intel_dp *intel_dp)
 	return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
 }
 
+/**
+ * intel_psr_is_enabled - Is PSR enabled?
+ * @dev: DRM Device
+ *
+ * This function can be used to verify if PSR feature is enabled.
+ * Since on Haswell+ we force the exit by disabling
+ * EDP_PSR_ENABLE bit at EDP_PSR_CTL(dev)
+ * the most reliable way to export if psr feature is enabled is to
+ * check the presence of intel_dp at dev_priv->psr.enabled.
+ */
 bool intel_psr_is_enabled(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -68,7 +78,7 @@ bool intel_psr_is_enabled(struct drm_device *dev)
 	if (!HAS_PSR(dev))
 		return false;
 
-	return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
+	return (bool)dev_priv->psr.enabled;
 }
 
 static void intel_psr_write_vsc(struct intel_dp *intel_dp,
-- 
1.9.3

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Re: [PATCH 09/15] drm/i915: Fix intel_psr_is_enabled function and document it.

[R, Durgadoss]

>-----Original Message-----
>From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of Rodrigo Vivi
>Sent: Friday, November 14, 2014 10:23 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Vivi, Rodrigo
>Subject: [Intel-gfx] [PATCH 09/15] drm/i915: Fix intel_psr_is_enabled function and document it.
>
>This function can be used to check if psr feature got enabled.
>However on HSW and BDW we currently force psr exit by disabling
>EDP_PSR_ENABLE bit at EDP_PSR_CTL(dev). So this function was actually
>returning the active/inactive state that is different from the enable/disable
>meaning and had the risk of false negative.
>
>So let's just return the presence of intel_dp at dev_priv->psr.enabled.
>
>It would be more easy to just check this presence directly but let's keep
>it more organized.

Agreed, but shouldn't we protect it using psr.lock ?

Thanks,
Durga

>
>Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>---
> drivers/gpu/drm/i915/intel_psr.c | 12 +++++++++++-
> 1 file changed, 11 insertions(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
>index 66d24c2..c296a89 100644
>--- a/drivers/gpu/drm/i915/intel_psr.c
>+++ b/drivers/gpu/drm/i915/intel_psr.c
>@@ -61,6 +61,16 @@ static bool is_edp_psr(struct intel_dp *intel_dp)
> 	return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
> }
>
>+/**
>+ * intel_psr_is_enabled - Is PSR enabled?
>+ * @dev: DRM Device
>+ *
>+ * This function can be used to verify if PSR feature is enabled.
>+ * Since on Haswell+ we force the exit by disabling
>+ * EDP_PSR_ENABLE bit at EDP_PSR_CTL(dev)
>+ * the most reliable way to export if psr feature is enabled is to
>+ * check the presence of intel_dp at dev_priv->psr.enabled.
>+ */
> bool intel_psr_is_enabled(struct drm_device *dev)
> {
> 	struct drm_i915_private *dev_priv = dev->dev_private;
>@@ -68,7 +78,7 @@ bool intel_psr_is_enabled(struct drm_device *dev)
> 	if (!HAS_PSR(dev))
> 		return false;
>
>-	return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
>+	return (bool)dev_priv->psr.enabled;
> }
>
> static void intel_psr_write_vsc(struct intel_dp *intel_dp,
>--
>1.9.3
>
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Re: [PATCH 09/15] drm/i915: Fix intel_psr_is_enabled function and document it.

[Daniel Vetter]

On Tue, Nov 18, 2014 at 06:24:30PM +0000, R, Durgadoss wrote:
> >-----Original Message-----
> >From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of Rodrigo Vivi
> >Sent: Friday, November 14, 2014 10:23 PM
> >To: intel-gfx@lists.freedesktop.org
> >Cc: Vivi, Rodrigo
> >Subject: [Intel-gfx] [PATCH 09/15] drm/i915: Fix intel_psr_is_enabled function and document it.
> >
> >This function can be used to check if psr feature got enabled.
> >However on HSW and BDW we currently force psr exit by disabling
> >EDP_PSR_ENABLE bit at EDP_PSR_CTL(dev). So this function was actually
> >returning the active/inactive state that is different from the enable/disable
> >meaning and had the risk of false negative.
> >
> >So let's just return the presence of intel_dp at dev_priv->psr.enabled.
> >
> >It would be more easy to just check this presence directly but let's keep
> >it more organized.
> 
> Agreed, but shouldn't we protect it using psr.lock ?

This function is used by DRRS and in a pretty crazy way. Sprinkling docs
and locking over it won't make this any better, what we need is some state
bits in the pipe config so that PSR and DRRS don't step on each anothers
feet. This kind of stuff here doesn't really work as soon as you throw in
the atomic check/commit semeantics we'll eventually have.

If possible I'd vote to just drop this, DRRS isn't enabled by default
currently anyway.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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[PATCH] drm/i915: Remove intel_psr_is_enabled function.

[Rodrigo Vivi]

This function was in use to check if psr feature got enabled.
However on HSW and BDW we currently force psr exit by disabling
EDP_PSR_ENABLE bit at EDP_PSR_CTL(dev). So this function was actually
returning the active/inactive state that is different from the enable/disable
meaning and had the risk of false negative.

But anyway this check with DRRS was dangerous, since DRRS could try to get enabled
before PSR gets there. So let's just remove it for now.
A propper syncronization mechanism must be implemented later probably
using pipe config.

Cc: Daniel Vetter <daniel@ffwll.ch>
Cc: Durgadoss R <durgadoss.r@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c  |  9 ++-------
 drivers/gpu/drm/i915/intel_drv.h |  1 -
 drivers/gpu/drm/i915/intel_psr.c | 10 ----------
 3 files changed, 2 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 46731da..5be6f5e 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4761,14 +4761,9 @@ void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
 	}
 
 	/*
-	 * FIXME: This needs proper synchronization with psr state. But really
-	 * hard to tell without seeing the user of this function of this code.
-	 * Check locking and ordering once that lands.
+	 * FIXME: This needs proper synchronization with psr state for some
+	 * platforms that cannot have PSR and DRRS enabled at the same time.
 	 */
-	if (INTEL_INFO(dev)->gen < 8 && intel_psr_is_enabled(dev)) {
-		DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
-		return;
-	}
 
 	encoder = intel_attached_encoder(&intel_connector->base);
 	intel_dp = enc_to_intel_dp(&encoder->base);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d1f9b63..7feded0 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1113,7 +1113,6 @@ void intel_backlight_unregister(struct drm_device *dev);
 
 
 /* intel_psr.c */
-bool intel_psr_is_enabled(struct drm_device *dev);
 void intel_psr_enable(struct intel_dp *intel_dp);
 void intel_psr_disable(struct intel_dp *intel_dp);
 void intel_psr_invalidate(struct drm_device *dev,
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 843762a..576ad02 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -61,16 +61,6 @@ static bool is_edp_psr(struct intel_dp *intel_dp)
 	return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
 }
 
-bool intel_psr_is_enabled(struct drm_device *dev)
-{
-	struct drm_i915_private *dev_priv = dev->dev_private;
-
-	if (!HAS_PSR(dev))
-		return false;
-
-	return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
-}
-
 static void intel_psr_write_vsc(struct intel_dp *intel_dp,
 				    struct edp_vsc_psr *vsc_psr)
 {
-- 
1.9.3

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Re: [PATCH] drm/i915: Remove intel_psr_is_enabled function.

[R, Durgadoss]

>-----Original Message-----
>From: Vivi, Rodrigo
>Sent: Wednesday, November 19, 2014 9:05 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Vivi, Rodrigo; Daniel Vetter; R, Durgadoss
>Subject: [PATCH] drm/i915: Remove intel_psr_is_enabled function.
>
>This function was in use to check if psr feature got enabled.
>However on HSW and BDW we currently force psr exit by disabling

s/psr/PSR

>EDP_PSR_ENABLE bit at EDP_PSR_CTL(dev). So this function was actually
>returning the active/inactive state that is different from the enable/disable
>meaning and had the risk of false negative.
>
>But anyway this check with DRRS was dangerous, since DRRS could try to get enabled
>before PSR gets there. So let's just remove it for now.
>A propper syncronization mechanism must be implemented later probably
>using pipe config.

Proper synchronization..

With that,

Reviewed-by: Durgadoss R <durgadoss.r@intel.com>

Thanks,
Durga

>
>Cc: Daniel Vetter <daniel@ffwll.ch>
>Cc: Durgadoss R <durgadoss.r@intel.com>
>Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>---
> drivers/gpu/drm/i915/intel_dp.c  |  9 ++-------
> drivers/gpu/drm/i915/intel_drv.h |  1 -
> drivers/gpu/drm/i915/intel_psr.c | 10 ----------
> 3 files changed, 2 insertions(+), 18 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>index 46731da..5be6f5e 100644
>--- a/drivers/gpu/drm/i915/intel_dp.c
>+++ b/drivers/gpu/drm/i915/intel_dp.c
>@@ -4761,14 +4761,9 @@ void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
> 	}
>
> 	/*
>-	 * FIXME: This needs proper synchronization with psr state. But really
>-	 * hard to tell without seeing the user of this function of this code.
>-	 * Check locking and ordering once that lands.
>+	 * FIXME: This needs proper synchronization with psr state for some
>+	 * platforms that cannot have PSR and DRRS enabled at the same time.
> 	 */
>-	if (INTEL_INFO(dev)->gen < 8 && intel_psr_is_enabled(dev)) {
>-		DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
>-		return;
>-	}
>
> 	encoder = intel_attached_encoder(&intel_connector->base);
> 	intel_dp = enc_to_intel_dp(&encoder->base);
>diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
>index d1f9b63..7feded0 100644
>--- a/drivers/gpu/drm/i915/intel_drv.h
>+++ b/drivers/gpu/drm/i915/intel_drv.h
>@@ -1113,7 +1113,6 @@ void intel_backlight_unregister(struct drm_device *dev);
>
>
> /* intel_psr.c */
>-bool intel_psr_is_enabled(struct drm_device *dev);
> void intel_psr_enable(struct intel_dp *intel_dp);
> void intel_psr_disable(struct intel_dp *intel_dp);
> void intel_psr_invalidate(struct drm_device *dev,
>diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
>index 843762a..576ad02 100644
>--- a/drivers/gpu/drm/i915/intel_psr.c
>+++ b/drivers/gpu/drm/i915/intel_psr.c
>@@ -61,16 +61,6 @@ static bool is_edp_psr(struct intel_dp *intel_dp)
> 	return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
> }
>
>-bool intel_psr_is_enabled(struct drm_device *dev)
>-{
>-	struct drm_i915_private *dev_priv = dev->dev_private;
>-
>-	if (!HAS_PSR(dev))
>-		return false;
>-
>-	return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
>-}
>-
> static void intel_psr_write_vsc(struct intel_dp *intel_dp,
> 				    struct edp_vsc_psr *vsc_psr)
> {
>--
>1.9.3

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[PATCH] drm/i915: Remove intel_psr_is_enabled function.

[Rodrigo Vivi]

This function was in use to check if PSR feature got enabled.
However on HSW and BDW we currently force psr exit by disabling
EDP_PSR_ENABLE bit at EDP_PSR_CTL(dev). So this function was actually
returning the active/inactive state that is different from the enable/disable
meaning and had the risk of false negative.

But anyway this check with DRRS was dangerous, since DRRS could try to get enabled
before PSR gets there. So let's just remove it for now.
A proper synchronization mechanism must be implemented later probably
using pipe config.

Cc: Daniel Vetter <daniel@ffwll.ch>
Reviewed-by: Durgadoss R <durgadoss.r@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c  |  9 ++-------
 drivers/gpu/drm/i915/intel_drv.h |  1 -
 drivers/gpu/drm/i915/intel_psr.c | 10 ----------
 3 files changed, 2 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 46731da..5be6f5e 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4761,14 +4761,9 @@ void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
 	}
 
 	/*
-	 * FIXME: This needs proper synchronization with psr state. But really
-	 * hard to tell without seeing the user of this function of this code.
-	 * Check locking and ordering once that lands.
+	 * FIXME: This needs proper synchronization with psr state for some
+	 * platforms that cannot have PSR and DRRS enabled at the same time.
 	 */
-	if (INTEL_INFO(dev)->gen < 8 && intel_psr_is_enabled(dev)) {
-		DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
-		return;
-	}
 
 	encoder = intel_attached_encoder(&intel_connector->base);
 	intel_dp = enc_to_intel_dp(&encoder->base);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d1f9b63..7feded0 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1113,7 +1113,6 @@ void intel_backlight_unregister(struct drm_device *dev);
 
 
 /* intel_psr.c */
-bool intel_psr_is_enabled(struct drm_device *dev);
 void intel_psr_enable(struct intel_dp *intel_dp);
 void intel_psr_disable(struct intel_dp *intel_dp);
 void intel_psr_invalidate(struct drm_device *dev,
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 843762a..576ad02 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -61,16 +61,6 @@ static bool is_edp_psr(struct intel_dp *intel_dp)
 	return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
 }
 
-bool intel_psr_is_enabled(struct drm_device *dev)
-{
-	struct drm_i915_private *dev_priv = dev->dev_private;
-
-	if (!HAS_PSR(dev))
-		return false;
-
-	return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
-}
-
 static void intel_psr_write_vsc(struct intel_dp *intel_dp,
 				    struct edp_vsc_psr *vsc_psr)
 {
-- 
1.9.3

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Re: [PATCH] drm/i915: Remove intel_psr_is_enabled function.

[shuang.he]

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                 -2              369/369              367/369
ILK              +2-13              384/386              373/386
SNB                 -9              459/459              450/459
IVB                 -32              535/535              503/535
BYT                 -1              290/290              289/290
HSW                 -27              312/312              285/312
BDW                 -21              303/303              282/303
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
PNV  igt_drv_hangman_error-state-capture-render      TIMEOUT(27, M25M7M23)PASS(10, M23M25M7)      TIMEOUT(1, M7)PASS(3, M7)
PNV  igt_drv_missed_irq_hang      TIMEOUT(36, M23M25M7)PASS(1, M23)      TIMEOUT(1, M7)PASS(3, M7)
ILK  igt_drv_hangman_error-state-basic      TIMEOUT(18, M37M26)PASS(4, M26)      TIMEOUT(1, M37)PASS(3, M37)
ILK  igt_drv_hangman_error-state-capture-bsd      TIMEOUT(7, M26M37)PASS(1, M26)      TIMEOUT(1, M37)PASS(3, M37)
ILK  igt_drv_hangman_error-state-capture-render      PASS(1, M26)      TIMEOUT(1, M37)PASS(3, M37)
ILK  igt_drv_missed_irq_hang      PASS(1, M26)      TIMEOUT(1, M37)PASS(3, M37)
ILK  igt_gem_reset_stats_ban-render      PASS(4, M26)      TIMEOUT(1, M37)PASS(3, M37)
ILK  igt_gem_reset_stats_close-pending-fork-render      PASS(1, M26)      TIMEOUT(1, M37)PASS(3, M37)
ILK  igt_gem_reset_stats_close-pending-fork-reverse-render      PASS(1, M26)      TIMEOUT(1, M37)PASS(3, M37)
ILK  igt_gem_reset_stats_close-pending-render      PASS(1, M26)      TIMEOUT(1, M37)PASS(3, M37)
ILK  igt_gem_reset_stats_reset-count-render      PASS(1, M26)      TIMEOUT(1, M37)PASS(3, M37)
ILK  igt_gem_reset_stats_reset-stats-render      PASS(1, M26)      TIMEOUT(1, M37)PASS(3, M37)
ILK  igt_gem_workarounds_reset      PASS(1, M26)      TIMEOUT(1, M37)PASS(3, M37)
ILK  igt_kms_flip_nonexisting-fb      DMESG_WARN(1, M26)      PASS(4, M37)
ILK  igt_kms_flip_flip-vs-panning      NSPT(1, M26)      PASS(4, M37)
ILK  igt_kms_flip_vblank-vs-hang      PASS(1, M26)      TIMEOUT(1, M37)PASS(3, M37)
ILK  igt_kms_flip_vblank-vs-hang-interruptible      PASS(1, M26)      TIMEOUT(1, M37)PASS(3, M37)
SNB  igt_drv_hangman_error-state-basic      TIMEOUT(24, M35M22)PASS(1, M35)      TIMEOUT(1, M22)PASS(3, M22)
SNB  igt_drv_hangman_error-state-capture-bsd      TIMEOUT(24, M35M22)PASS(1, M35)      TIMEOUT(1, M22)PASS(3, M22)
SNB  igt_drv_hangman_error-state-capture-render      TIMEOUT(8, M35M22)PASS(1, M35)      TIMEOUT(1, M22)PASS(3, M22)
SNB  igt_drv_missed_irq_hang      PASS(1, M35)      TIMEOUT(1, M22)PASS(3, M22)
SNB  igt_gem_reset_stats_reset-count-render      PASS(1, M35)      TIMEOUT(1, M22)PASS(3, M22)
SNB  igt_gem_reset_stats_unrelated-ctx-render      PASS(1, M35)      TIMEOUT(1, M22)PASS(3, M22)
SNB  igt_kms_pipe_crc_basic_hang-read-crc-pipe-A      PASS(4, M35)      TIMEOUT(1, M22)PASS(3, M22)
SNB  igt_kms_pipe_crc_basic_hang-read-crc-pipe-B      PASS(1, M35)      TIMEOUT(1, M22)PASS(3, M22)
SNB  igt_pm_rps_min-max-config-idle      PASS(1, M35)      FAIL(1, M22)PASS(3, M22)
IVB  igt_drv_hangman_error-state-basic      TIMEOUT(21, M34M21M4)PASS(4, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_drv_hangman_error-state-capture-blt      TIMEOUT(20, M34M21M4)PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_drv_hangman_error-state-capture-bsd      TIMEOUT(1, M34)PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_drv_hangman_error-state-capture-render      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_drv_missed_irq_hang      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_bad_reloc_negative-reloc      PASS(1, M21)      NSPT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_ban-ctx-render      DMESG_WARN(2, M21)PASS(2, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_ban-render      DMESG_WARN(2, M21)PASS(2, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_close-pending-blt      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_close-pending-bsd      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_close-pending-ctx-render      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_close-pending-fork-blt      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_close-pending-fork-bsd      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_close-pending-fork-render      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_close-pending-fork-reverse-blt      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_close-pending-fork-reverse-bsd      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_close-pending-fork-reverse-render      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_close-pending-render      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_reset-count-blt      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_reset-count-bsd      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_reset-count-ctx-render      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_reset-count-render      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_reset-stats-blt      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_reset-stats-bsd      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_reset-stats-ctx-render      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_reset-stats-render      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_unrelated-ctx-render      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_workarounds_reset      PASS(4, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_kms_pipe_crc_basic_hang-read-crc-pipe-A      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_kms_pipe_crc_basic_hang-read-crc-pipe-B      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_kms_pipe_crc_basic_hang-read-crc-pipe-C      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_pm_rps_min-max-config-idle      PASS(1, M21)      FAIL(1, M34)PASS(3, M34)
BYT  igt_drv_missed_irq_hang      TIMEOUT(38, M36M31)PASS(2, M36M31)      TIMEOUT(1, M36)PASS(3, M36)
HSW  igt_drv_hangman_error-state-capture-bsd      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_drv_hangman_error-state-capture-render      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_drv_hangman_error-state-capture-vebox      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_ban-ctx-render      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_ban-render      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_ban-vebox      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_close-pending-blt      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_close-pending-bsd      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_close-pending-ctx-render      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_close-pending-fork-blt      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_close-pending-fork-bsd      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_close-pending-fork-render      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_close-pending-fork-reverse-blt      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_close-pending-fork-reverse-bsd      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_close-pending-fork-reverse-render      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_close-pending-fork-reverse-vebox      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_close-pending-render      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_close-pending-vebox      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_reset-count-blt      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_reset-count-bsd      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_reset-count-ctx-render      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_reset-count-render      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_reset-count-vebox      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_reset-stats-blt      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_reset-stats-bsd      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_reset-stats-ctx-render      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_reset-stats-render      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
BDW  igt_drv_hangman_error-state-basic      TIMEOUT(18, M28M30)PASS(4, M28M30)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_drv_hangman_error-state-capture-blt      TIMEOUT(17, M28M30)PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_drv_hangman_error-state-capture-bsd      TIMEOUT(1, M28)PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_drv_hangman_error-state-capture-render      PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_drv_hangman_error-state-capture-vebox      PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_gem_reset_stats_ban-blt      PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_gem_reset_stats_ban-bsd      PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_gem_reset_stats_ban-ctx-render      PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_gem_reset_stats_ban-render      PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_gem_reset_stats_ban-vebox      PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_gem_reset_stats_close-pending-blt      PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_gem_reset_stats_close-pending-bsd      PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_gem_reset_stats_close-pending-ctx-render      PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_gem_reset_stats_close-pending-fork-blt      PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_gem_reset_stats_close-pending-fork-bsd      PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_gem_reset_stats_close-pending-fork-render      PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_gem_reset_stats_close-pending-fork-reverse-blt      PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_gem_reset_stats_close-pending-fork-reverse-bsd      PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_gem_reset_stats_close-pending-fork-reverse-render      PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_gem_reset_stats_close-pending-fork-reverse-vebox      PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_gem_reset_stats_close-pending-fork-vebox      PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
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Re: [PATCH] drm/i915: Remove intel_psr_is_enabled function.

[Daniel Vetter]

On Thu, Nov 20, 2014 at 02:22:08AM -0800, Rodrigo Vivi wrote:
> This function was in use to check if PSR feature got enabled.
> However on HSW and BDW we currently force psr exit by disabling
> EDP_PSR_ENABLE bit at EDP_PSR_CTL(dev). So this function was actually
> returning the active/inactive state that is different from the enable/disable
> meaning and had the risk of false negative.
> 
> But anyway this check with DRRS was dangerous, since DRRS could try to get enabled
> before PSR gets there. So let's just remove it for now.
> A proper synchronization mechanism must be implemented later probably
> using pipe config.

Patch changelog is missing. Not that important just for spelling fixes,
but still nice to mention when that's really the only thing that's
changed.
-Daniel

> 
> Cc: Daniel Vetter <daniel@ffwll.ch>
> Reviewed-by: Durgadoss R <durgadoss.r@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c  |  9 ++-------
>  drivers/gpu/drm/i915/intel_drv.h |  1 -
>  drivers/gpu/drm/i915/intel_psr.c | 10 ----------
>  3 files changed, 2 insertions(+), 18 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 46731da..5be6f5e 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -4761,14 +4761,9 @@ void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
>  	}
>  
>  	/*
> -	 * FIXME: This needs proper synchronization with psr state. But really
> -	 * hard to tell without seeing the user of this function of this code.
> -	 * Check locking and ordering once that lands.
> +	 * FIXME: This needs proper synchronization with psr state for some
> +	 * platforms that cannot have PSR and DRRS enabled at the same time.
>  	 */
> -	if (INTEL_INFO(dev)->gen < 8 && intel_psr_is_enabled(dev)) {
> -		DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
> -		return;
> -	}
>  
>  	encoder = intel_attached_encoder(&intel_connector->base);
>  	intel_dp = enc_to_intel_dp(&encoder->base);
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index d1f9b63..7feded0 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1113,7 +1113,6 @@ void intel_backlight_unregister(struct drm_device *dev);
>  
>  
>  /* intel_psr.c */
> -bool intel_psr_is_enabled(struct drm_device *dev);
>  void intel_psr_enable(struct intel_dp *intel_dp);
>  void intel_psr_disable(struct intel_dp *intel_dp);
>  void intel_psr_invalidate(struct drm_device *dev,
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 843762a..576ad02 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -61,16 +61,6 @@ static bool is_edp_psr(struct intel_dp *intel_dp)
>  	return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
>  }
>  
> -bool intel_psr_is_enabled(struct drm_device *dev)
> -{
> -	struct drm_i915_private *dev_priv = dev->dev_private;
> -
> -	if (!HAS_PSR(dev))
> -		return false;
> -
> -	return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
> -}
> -
>  static void intel_psr_write_vsc(struct intel_dp *intel_dp,
>  				    struct edp_vsc_psr *vsc_psr)
>  {
> -- 
> 1.9.3
> 

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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[PATCH] drm/i915: Remove intel_psr_is_enabled function.

[Rodrigo Vivi]

This function was in use to check if PSR feature got enabled.
However on HSW and BDW we currently force psr exit by disabling
EDP_PSR_ENABLE bit at EDP_PSR_CTL(dev). So this function was actually
returning the active/inactive state that is different from the enable/disable
meaning and had the risk of false negative.

But anyway this check with DRRS was dangerous, since DRRS could try to get enabled
before PSR gets there. So let's just remove it for now.
A proper synchronization mechanism must be implemented later probably
using pipe config.

v2: Fixing a typo on commit description.

Cc: Daniel Vetter <daniel@ffwll.ch>
Reviewed-by: Durgadoss R <durgadoss.r@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c  |  9 ++-------
 drivers/gpu/drm/i915/intel_drv.h |  1 -
 drivers/gpu/drm/i915/intel_psr.c | 10 ----------
 3 files changed, 2 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 46731da..5be6f5e 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4761,14 +4761,9 @@ void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
 	}
 
 	/*
-	 * FIXME: This needs proper synchronization with psr state. But really
-	 * hard to tell without seeing the user of this function of this code.
-	 * Check locking and ordering once that lands.
+	 * FIXME: This needs proper synchronization with psr state for some
+	 * platforms that cannot have PSR and DRRS enabled at the same time.
 	 */
-	if (INTEL_INFO(dev)->gen < 8 && intel_psr_is_enabled(dev)) {
-		DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
-		return;
-	}
 
 	encoder = intel_attached_encoder(&intel_connector->base);
 	intel_dp = enc_to_intel_dp(&encoder->base);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d1f9b63..7feded0 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1113,7 +1113,6 @@ void intel_backlight_unregister(struct drm_device *dev);
 
 
 /* intel_psr.c */
-bool intel_psr_is_enabled(struct drm_device *dev);
 void intel_psr_enable(struct intel_dp *intel_dp);
 void intel_psr_disable(struct intel_dp *intel_dp);
 void intel_psr_invalidate(struct drm_device *dev,
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 843762a..576ad02 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -61,16 +61,6 @@ static bool is_edp_psr(struct intel_dp *intel_dp)
 	return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
 }
 
-bool intel_psr_is_enabled(struct drm_device *dev)
-{
-	struct drm_i915_private *dev_priv = dev->dev_private;
-
-	if (!HAS_PSR(dev))
-		return false;
-
-	return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
-}
-
 static void intel_psr_write_vsc(struct intel_dp *intel_dp,
 				    struct edp_vsc_psr *vsc_psr)
 {
-- 
1.9.3

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Re: [PATCH] drm/i915: Remove intel_psr_is_enabled function.

[shuang.he]

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                 -2              369/369              367/369
ILK              +2-13              384/386              373/386
SNB                 -9              459/459              450/459
IVB                 -32              535/535              503/535
BYT                 -1              290/290              289/290
HSW                 -27              312/312              285/312
BDW                 -21              303/303              282/303
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
PNV  igt_drv_hangman_error-state-capture-render      TIMEOUT(27, M25M7M23)PASS(10, M23M25M7)      TIMEOUT(1, M7)PASS(3, M7)
PNV  igt_drv_missed_irq_hang      TIMEOUT(36, M23M25M7)PASS(1, M23)      TIMEOUT(1, M7)PASS(3, M7)
ILK  igt_drv_hangman_error-state-basic      TIMEOUT(18, M37M26)PASS(4, M26)      TIMEOUT(1, M37)PASS(3, M37)
ILK  igt_drv_hangman_error-state-capture-bsd      TIMEOUT(7, M26M37)PASS(1, M26)      TIMEOUT(1, M37)PASS(3, M37)
ILK  igt_drv_hangman_error-state-capture-render      PASS(1, M26)      TIMEOUT(1, M37)PASS(3, M37)
ILK  igt_drv_missed_irq_hang      PASS(1, M26)      TIMEOUT(1, M37)PASS(3, M37)
ILK  igt_gem_reset_stats_ban-render      PASS(4, M26)      TIMEOUT(1, M37)PASS(3, M37)
ILK  igt_gem_reset_stats_close-pending-fork-render      PASS(1, M26)      TIMEOUT(1, M37)PASS(3, M37)
ILK  igt_gem_reset_stats_close-pending-fork-reverse-render      PASS(1, M26)      TIMEOUT(1, M37)PASS(3, M37)
ILK  igt_gem_reset_stats_close-pending-render      PASS(1, M26)      TIMEOUT(1, M37)PASS(3, M37)
ILK  igt_gem_reset_stats_reset-count-render      PASS(1, M26)      TIMEOUT(1, M37)PASS(3, M37)
ILK  igt_gem_reset_stats_reset-stats-render      PASS(1, M26)      TIMEOUT(1, M37)PASS(3, M37)
ILK  igt_gem_workarounds_reset      PASS(1, M26)      TIMEOUT(1, M37)PASS(3, M37)
ILK  igt_kms_flip_nonexisting-fb      DMESG_WARN(1, M26)      PASS(4, M37)
ILK  igt_kms_flip_flip-vs-panning      NSPT(1, M26)      PASS(4, M37)
ILK  igt_kms_flip_vblank-vs-hang      PASS(1, M26)      TIMEOUT(1, M37)PASS(3, M37)
ILK  igt_kms_flip_vblank-vs-hang-interruptible      PASS(1, M26)      TIMEOUT(1, M37)PASS(3, M37)
SNB  igt_drv_hangman_error-state-basic      TIMEOUT(24, M35M22)PASS(1, M35)      TIMEOUT(1, M22)PASS(3, M22)
SNB  igt_drv_hangman_error-state-capture-bsd      TIMEOUT(24, M35M22)PASS(1, M35)      TIMEOUT(1, M22)PASS(3, M22)
SNB  igt_drv_hangman_error-state-capture-render      TIMEOUT(8, M35M22)PASS(1, M35)      TIMEOUT(1, M22)PASS(3, M22)
SNB  igt_drv_missed_irq_hang      PASS(1, M35)      TIMEOUT(1, M22)PASS(3, M22)
SNB  igt_gem_reset_stats_reset-count-render      PASS(1, M35)      TIMEOUT(1, M22)PASS(3, M22)
SNB  igt_gem_reset_stats_unrelated-ctx-render      PASS(1, M35)      TIMEOUT(1, M22)PASS(3, M22)
SNB  igt_kms_pipe_crc_basic_hang-read-crc-pipe-A      PASS(4, M35)      TIMEOUT(1, M22)PASS(3, M22)
SNB  igt_kms_pipe_crc_basic_hang-read-crc-pipe-B      PASS(1, M35)      TIMEOUT(1, M22)PASS(3, M22)
SNB  igt_pm_rps_min-max-config-idle      PASS(1, M35)      FAIL(1, M22)PASS(3, M22)
IVB  igt_drv_hangman_error-state-basic      TIMEOUT(21, M34M21M4)PASS(4, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_drv_hangman_error-state-capture-blt      TIMEOUT(20, M34M21M4)PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_drv_hangman_error-state-capture-bsd      TIMEOUT(1, M34)PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_drv_hangman_error-state-capture-render      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_drv_missed_irq_hang      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_bad_reloc_negative-reloc      PASS(1, M21)      NSPT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_ban-ctx-render      DMESG_WARN(2, M21)PASS(2, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_ban-render      DMESG_WARN(2, M21)PASS(2, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_close-pending-blt      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_close-pending-bsd      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_close-pending-ctx-render      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_close-pending-fork-blt      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_close-pending-fork-bsd      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_close-pending-fork-render      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_close-pending-fork-reverse-blt      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_close-pending-fork-reverse-bsd      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_close-pending-fork-reverse-render      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_close-pending-render      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_reset-count-blt      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_reset-count-bsd      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_reset-count-ctx-render      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_reset-count-render      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_reset-stats-blt      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_reset-stats-bsd      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_reset-stats-ctx-render      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_reset-stats-render      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_unrelated-ctx-render      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_workarounds_reset      PASS(4, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_kms_pipe_crc_basic_hang-read-crc-pipe-A      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_kms_pipe_crc_basic_hang-read-crc-pipe-B      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_kms_pipe_crc_basic_hang-read-crc-pipe-C      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_pm_rps_min-max-config-idle      PASS(1, M21)      FAIL(1, M34)PASS(3, M34)
BYT  igt_drv_missed_irq_hang      TIMEOUT(38, M36M31)PASS(2, M36M31)      TIMEOUT(1, M36)PASS(3, M36)
HSW  igt_drv_hangman_error-state-capture-bsd      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_drv_hangman_error-state-capture-render      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_drv_hangman_error-state-capture-vebox      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_ban-ctx-render      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_ban-render      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_ban-vebox      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_close-pending-blt      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_close-pending-bsd      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_close-pending-ctx-render      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_close-pending-fork-blt      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_close-pending-fork-bsd      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_close-pending-fork-render      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_close-pending-fork-reverse-blt      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_close-pending-fork-reverse-bsd      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_close-pending-fork-reverse-render      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_close-pending-fork-reverse-vebox      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_close-pending-render      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_close-pending-vebox      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_reset-count-blt      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_reset-count-bsd      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_reset-count-ctx-render      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_reset-count-render      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_reset-count-vebox      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_reset-stats-blt      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_reset-stats-bsd      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_reset-stats-ctx-render      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_reset-stats-render      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
BDW  igt_drv_hangman_error-state-basic      TIMEOUT(18, M28M30)PASS(4, M28M30)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_drv_hangman_error-state-capture-blt      TIMEOUT(17, M28M30)PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_drv_hangman_error-state-capture-bsd      TIMEOUT(1, M28)PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_drv_hangman_error-state-capture-render      PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_drv_hangman_error-state-capture-vebox      PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_gem_reset_stats_ban-blt      PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_gem_reset_stats_ban-bsd      PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_gem_reset_stats_ban-ctx-render      PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_gem_reset_stats_ban-render      PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_gem_reset_stats_ban-vebox      PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_gem_reset_stats_close-pending-blt      PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_gem_reset_stats_close-pending-bsd      PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_gem_reset_stats_close-pending-ctx-render      PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_gem_reset_stats_close-pending-fork-blt      PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_gem_reset_stats_close-pending-fork-bsd      PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_gem_reset_stats_close-pending-fork-render      PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_gem_reset_stats_close-pending-fork-reverse-blt      PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_gem_reset_stats_close-pending-fork-reverse-bsd      PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_gem_reset_stats_close-pending-fork-reverse-render      PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_gem_reset_stats_close-pending-fork-reverse-vebox      PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_gem_reset_stats_close-pending-fork-vebox      PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
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Re: [PATCH] drm/i915: Remove intel_psr_is_enabled function.

[shuang.he]

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                 -2              369/369              367/369
ILK              +2-13              384/386              373/386
SNB                 -9              459/459              450/459
IVB                 -32              535/535              503/535
BYT                 -1              290/290              289/290
HSW                 -27              312/312              285/312
BDW                 -21              303/303              282/303
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
PNV  igt_drv_hangman_error-state-capture-render      TIMEOUT(27, M25M7M23)PASS(10, M23M25M7)      TIMEOUT(1, M7)PASS(3, M7)
PNV  igt_drv_missed_irq_hang      TIMEOUT(36, M23M25M7)PASS(1, M23)      TIMEOUT(1, M7)PASS(3, M7)
ILK  igt_drv_hangman_error-state-basic      TIMEOUT(18, M37M26)PASS(4, M26)      TIMEOUT(1, M37)PASS(3, M37)
ILK  igt_drv_hangman_error-state-capture-bsd      TIMEOUT(7, M26M37)PASS(1, M26)      TIMEOUT(1, M37)PASS(3, M37)
ILK  igt_drv_hangman_error-state-capture-render      PASS(1, M26)      TIMEOUT(1, M37)PASS(3, M37)
ILK  igt_drv_missed_irq_hang      PASS(1, M26)      TIMEOUT(1, M37)PASS(3, M37)
ILK  igt_gem_reset_stats_ban-render      PASS(4, M26)      TIMEOUT(1, M37)PASS(3, M37)
ILK  igt_gem_reset_stats_close-pending-fork-render      PASS(1, M26)      TIMEOUT(1, M37)PASS(3, M37)
ILK  igt_gem_reset_stats_close-pending-fork-reverse-render      PASS(1, M26)      TIMEOUT(1, M37)PASS(3, M37)
ILK  igt_gem_reset_stats_close-pending-render      PASS(1, M26)      TIMEOUT(1, M37)PASS(3, M37)
ILK  igt_gem_reset_stats_reset-count-render      PASS(1, M26)      TIMEOUT(1, M37)PASS(3, M37)
ILK  igt_gem_reset_stats_reset-stats-render      PASS(1, M26)      TIMEOUT(1, M37)PASS(3, M37)
ILK  igt_gem_workarounds_reset      PASS(1, M26)      TIMEOUT(1, M37)PASS(3, M37)
ILK  igt_kms_flip_nonexisting-fb      DMESG_WARN(1, M26)      PASS(4, M37)
ILK  igt_kms_flip_flip-vs-panning      NSPT(1, M26)      PASS(4, M37)
ILK  igt_kms_flip_vblank-vs-hang      PASS(1, M26)      TIMEOUT(1, M37)PASS(3, M37)
ILK  igt_kms_flip_vblank-vs-hang-interruptible      PASS(1, M26)      TIMEOUT(1, M37)PASS(3, M37)
SNB  igt_drv_hangman_error-state-basic      TIMEOUT(24, M35M22)PASS(1, M35)      TIMEOUT(1, M22)PASS(3, M22)
SNB  igt_drv_hangman_error-state-capture-bsd      TIMEOUT(24, M35M22)PASS(1, M35)      TIMEOUT(1, M22)PASS(3, M22)
SNB  igt_drv_hangman_error-state-capture-render      TIMEOUT(8, M35M22)PASS(1, M35)      TIMEOUT(1, M22)PASS(3, M22)
SNB  igt_drv_missed_irq_hang      PASS(1, M35)      TIMEOUT(1, M22)PASS(3, M22)
SNB  igt_gem_reset_stats_reset-count-render      PASS(1, M35)      TIMEOUT(1, M22)PASS(3, M22)
SNB  igt_gem_reset_stats_unrelated-ctx-render      PASS(1, M35)      TIMEOUT(1, M22)PASS(3, M22)
SNB  igt_kms_pipe_crc_basic_hang-read-crc-pipe-A      PASS(4, M35)      TIMEOUT(1, M22)PASS(3, M22)
SNB  igt_kms_pipe_crc_basic_hang-read-crc-pipe-B      PASS(1, M35)      TIMEOUT(1, M22)PASS(3, M22)
SNB  igt_pm_rps_min-max-config-idle      PASS(1, M35)      FAIL(1, M22)PASS(3, M22)
IVB  igt_drv_hangman_error-state-basic      TIMEOUT(21, M34M21M4)PASS(4, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_drv_hangman_error-state-capture-blt      TIMEOUT(20, M34M21M4)PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_drv_hangman_error-state-capture-bsd      TIMEOUT(1, M34)PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_drv_hangman_error-state-capture-render      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_drv_missed_irq_hang      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_bad_reloc_negative-reloc      PASS(1, M21)      NSPT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_ban-ctx-render      DMESG_WARN(2, M21)PASS(2, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_ban-render      DMESG_WARN(2, M21)PASS(2, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_close-pending-blt      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_close-pending-bsd      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_close-pending-ctx-render      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_close-pending-fork-blt      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_close-pending-fork-bsd      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_close-pending-fork-render      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_close-pending-fork-reverse-blt      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_close-pending-fork-reverse-bsd      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_close-pending-fork-reverse-render      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_close-pending-render      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_reset-count-blt      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_reset-count-bsd      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_reset-count-ctx-render      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_reset-count-render      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_reset-stats-blt      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_reset-stats-bsd      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_reset-stats-ctx-render      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_reset-stats-render      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_reset_stats_unrelated-ctx-render      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_gem_workarounds_reset      PASS(4, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_kms_pipe_crc_basic_hang-read-crc-pipe-A      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_kms_pipe_crc_basic_hang-read-crc-pipe-B      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_kms_pipe_crc_basic_hang-read-crc-pipe-C      PASS(1, M21)      TIMEOUT(1, M34)PASS(3, M34)
IVB  igt_pm_rps_min-max-config-idle      PASS(1, M21)      FAIL(1, M34)PASS(3, M34)
BYT  igt_drv_missed_irq_hang      TIMEOUT(38, M36M31)PASS(2, M36M31)      TIMEOUT(1, M36)PASS(3, M36)
HSW  igt_drv_hangman_error-state-capture-bsd      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_drv_hangman_error-state-capture-render      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_drv_hangman_error-state-capture-vebox      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_ban-ctx-render      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_ban-render      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_ban-vebox      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_close-pending-blt      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_close-pending-bsd      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_close-pending-ctx-render      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_close-pending-fork-blt      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_close-pending-fork-bsd      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_close-pending-fork-render      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_close-pending-fork-reverse-blt      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_close-pending-fork-reverse-bsd      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_close-pending-fork-reverse-render      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_close-pending-fork-reverse-vebox      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_close-pending-render      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_close-pending-vebox      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_reset-count-blt      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_reset-count-bsd      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_reset-count-ctx-render      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_reset-count-render      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_reset-count-vebox      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_reset-stats-blt      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_reset-stats-bsd      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_reset-stats-ctx-render      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
HSW  igt_gem_reset_stats_reset-stats-render      PASS(1, M19)      TIMEOUT(1, M40)PASS(1, M40)
BDW  igt_drv_hangman_error-state-basic      TIMEOUT(18, M28M30)PASS(4, M28M30)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_drv_hangman_error-state-capture-blt      TIMEOUT(17, M28M30)PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_drv_hangman_error-state-capture-bsd      TIMEOUT(1, M28)PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_drv_hangman_error-state-capture-render      PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_drv_hangman_error-state-capture-vebox      PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_gem_reset_stats_ban-blt      PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_gem_reset_stats_ban-bsd      PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_gem_reset_stats_ban-ctx-render      PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_gem_reset_stats_ban-render      PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_gem_reset_stats_ban-vebox      PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_gem_reset_stats_close-pending-blt      PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_gem_reset_stats_close-pending-bsd      PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_gem_reset_stats_close-pending-ctx-render      PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_gem_reset_stats_close-pending-fork-blt      PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_gem_reset_stats_close-pending-fork-bsd      PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_gem_reset_stats_close-pending-fork-render      PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_gem_reset_stats_close-pending-fork-reverse-blt      PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_gem_reset_stats_close-pending-fork-reverse-bsd      PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_gem_reset_stats_close-pending-fork-reverse-render      PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_gem_reset_stats_close-pending-fork-reverse-vebox      PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
BDW  igt_gem_reset_stats_close-pending-fork-vebox      PASS(1, M28)      TIMEOUT(1, M28)PASS(3, M28)
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[PATCH 10/15] drm/i915: Add PSR registers for PSR VLV/CHV.

[Rodrigo Vivi]

Baytrail (Valleyview) and Braswell (Cherryview) uses a complete different
implementation of PSR that we currently have supported for
Haswell and Broadwell. So let's start by adding registers definitions.

I usually don't like commit that adds just registers without using,
but after I put all in one commit I realized that no one would want
to take the AR to review it so I decided to split in order to make
reviewer's life easier. Only last commit in this series will actually
enable the PSR on intel enable panel path.

But as it happens currently with HSW/BDW the plan is to let it
disabled by default (protected by kernel parameter)
while we are able to fully validate it.

v2: Remove a unused bit definition that isn't used on vlv and
    reserved on chv as pointed out by Durgadoss.

Cc: Durgadoss R <durgadoss.r@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 36 ++++++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 35cfc16..667a923 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2511,6 +2511,42 @@ enum punit_power_well {
 #define PIPESRC(trans) _TRANSCODER2(trans, _PIPEASRC)
 #define PIPE_MULT(trans) _TRANSCODER2(trans, _PIPE_MULT_A)
 
+/* VLV eDP PSR registers */
+#define _PSRCTLA				(VLV_DISPLAY_BASE + 0x60090)
+#define _PSRCTLB				(VLV_DISPLAY_BASE + 0x61090)
+#define  VLV_EDP_PSR_ENABLE			(1<<0)
+#define  VLV_EDP_PSR_RESET			(1<<1)
+#define  VLV_EDP_PSR_MODE_MASK			(7<<2)
+#define  VLV_EDP_PSR_MODE_HW_TIMER		(1<<3)
+#define  VLV_EDP_PSR_MODE_SW_TIMER		(1<<2)
+#define  VLV_EDP_PSR_SINGLE_FRAME_UPDATE	(1<<7)
+#define  VLV_EDP_PSR_ACTIVE_ENTRY		(1<<8)
+#define  VLV_EDP_PSR_SRC_TRANSMITTER_STATE	(1<<9)
+#define  VLV_EDP_PSR_DBL_FRAME			(1<<10)
+#define  VLV_EDP_PSR_FRAME_COUNT_MASK		(0xff<<16)
+#define  VLV_EDP_PSR_IDLE_FRAME_SHIFT		16
+#define VLV_PSRCTL(pipe) _PIPE(pipe, _PSRCTLA, _PSRCTLB)
+
+#define _VSCSDPA			(VLV_DISPLAY_BASE + 0x600a0)
+#define _VSCSDPB			(VLV_DISPLAY_BASE + 0x610a0)
+#define  VLV_EDP_PSR_SDP_FREQ_MASK	(3<<30)
+#define  VLV_EDP_PSR_SDP_FREQ_ONCE	(1<<31)
+#define  VLV_EDP_PSR_SDP_FREQ_EVFRAME	(1<<30)
+#define VLV_VSCSDP(pipe)	_PIPE(pipe, _VSCSDPA, _VSCSDPB)
+
+#define _PSRSTATA			(VLV_DISPLAY_BASE + 0x60094)
+#define _PSRSTATB			(VLV_DISPLAY_BASE + 0x61094)
+#define  VLV_EDP_PSR_LAST_STATE_MASK	(7<<3)
+#define  VLV_EDP_PSR_CURR_STATE_MASK	7
+#define  VLV_EDP_PSR_DISABLED		(0<<0)
+#define  VLV_EDP_PSR_INACTIVE		(1<<0)
+#define  VLV_EDP_PSR_IN_TRANS_TO_ACTIVE	(2<<0)
+#define  VLV_EDP_PSR_ACTIVE_NORFB_UP	(3<<0)
+#define  VLV_EDP_PSR_ACTIVE_SF_UPDATE	(4<<0)
+#define  VLV_EDP_PSR_EXIT		(5<<0)
+#define  VLV_EDP_PSR_IN_TRANS		(1<<7)
+#define VLV_PSRSTAT(pipe) _PIPE(pipe, _PSRSTATA, _PSRSTATB)
+
 /* HSW+ eDP PSR registers */
 #define EDP_PSR_BASE(dev)                       (IS_HASWELL(dev) ? 0x64800 : 0x6f800)
 #define EDP_PSR_CTL(dev)			(EDP_PSR_BASE(dev) + 0)
-- 
1.9.3

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Re: [PATCH 10/15] drm/i915: Add PSR registers for PSR VLV/CHV.

[R, Durgadoss]

>-----Original Message-----
>From: Vivi, Rodrigo
>Sent: Friday, November 14, 2014 10:23 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Vivi, Rodrigo; R, Durgadoss
>Subject: [PATCH 10/15] drm/i915: Add PSR registers for PSR VLV/CHV.
>
>Baytrail (Valleyview) and Braswell (Cherryview) uses a complete different
>implementation of PSR that we currently have supported for
>Haswell and Broadwell. So let's start by adding registers definitions.
>
>I usually don't like commit that adds just registers without using,
>but after I put all in one commit I realized that no one would want
>to take the AR to review it so I decided to split in order to make
>reviewer's life easier. Only last commit in this series will actually
>enable the PSR on intel enable panel path.
>
>But as it happens currently with HSW/BDW the plan is to let it
>disabled by default (protected by kernel parameter)
>while we are able to fully validate it.
>
>v2: Remove a unused bit definition that isn't used on vlv and
>    reserved on chv as pointed out by Durgadoss.
>
>Cc: Durgadoss R <durgadoss.r@intel.com>
>Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Reviewed-by: Durgadoss R <durgadoss.r@intel.com>

Thanks,
Durga

>---
> drivers/gpu/drm/i915/i915_reg.h | 36 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 36 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index 35cfc16..667a923 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -2511,6 +2511,42 @@ enum punit_power_well {
> #define PIPESRC(trans) _TRANSCODER2(trans, _PIPEASRC)
> #define PIPE_MULT(trans) _TRANSCODER2(trans, _PIPE_MULT_A)
>
>+/* VLV eDP PSR registers */
>+#define _PSRCTLA				(VLV_DISPLAY_BASE + 0x60090)
>+#define _PSRCTLB				(VLV_DISPLAY_BASE + 0x61090)
>+#define  VLV_EDP_PSR_ENABLE			(1<<0)
>+#define  VLV_EDP_PSR_RESET			(1<<1)
>+#define  VLV_EDP_PSR_MODE_MASK			(7<<2)
>+#define  VLV_EDP_PSR_MODE_HW_TIMER		(1<<3)
>+#define  VLV_EDP_PSR_MODE_SW_TIMER		(1<<2)
>+#define  VLV_EDP_PSR_SINGLE_FRAME_UPDATE	(1<<7)
>+#define  VLV_EDP_PSR_ACTIVE_ENTRY		(1<<8)
>+#define  VLV_EDP_PSR_SRC_TRANSMITTER_STATE	(1<<9)
>+#define  VLV_EDP_PSR_DBL_FRAME			(1<<10)
>+#define  VLV_EDP_PSR_FRAME_COUNT_MASK		(0xff<<16)
>+#define  VLV_EDP_PSR_IDLE_FRAME_SHIFT		16
>+#define VLV_PSRCTL(pipe) _PIPE(pipe, _PSRCTLA, _PSRCTLB)
>+
>+#define _VSCSDPA			(VLV_DISPLAY_BASE + 0x600a0)
>+#define _VSCSDPB			(VLV_DISPLAY_BASE + 0x610a0)
>+#define  VLV_EDP_PSR_SDP_FREQ_MASK	(3<<30)
>+#define  VLV_EDP_PSR_SDP_FREQ_ONCE	(1<<31)
>+#define  VLV_EDP_PSR_SDP_FREQ_EVFRAME	(1<<30)
>+#define VLV_VSCSDP(pipe)	_PIPE(pipe, _VSCSDPA, _VSCSDPB)
>+
>+#define _PSRSTATA			(VLV_DISPLAY_BASE + 0x60094)
>+#define _PSRSTATB			(VLV_DISPLAY_BASE + 0x61094)
>+#define  VLV_EDP_PSR_LAST_STATE_MASK	(7<<3)
>+#define  VLV_EDP_PSR_CURR_STATE_MASK	7
>+#define  VLV_EDP_PSR_DISABLED		(0<<0)
>+#define  VLV_EDP_PSR_INACTIVE		(1<<0)
>+#define  VLV_EDP_PSR_IN_TRANS_TO_ACTIVE	(2<<0)
>+#define  VLV_EDP_PSR_ACTIVE_NORFB_UP	(3<<0)
>+#define  VLV_EDP_PSR_ACTIVE_SF_UPDATE	(4<<0)
>+#define  VLV_EDP_PSR_EXIT		(5<<0)
>+#define  VLV_EDP_PSR_IN_TRANS		(1<<7)
>+#define VLV_PSRSTAT(pipe) _PIPE(pipe, _PSRSTATA, _PSRSTATB)
>+
> /* HSW+ eDP PSR registers */
> #define EDP_PSR_BASE(dev)                       (IS_HASWELL(dev) ? 0x64800 : 0x6f800)
> #define EDP_PSR_CTL(dev)			(EDP_PSR_BASE(dev) + 0)
>--
>1.9.3

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[PATCH 11/15] drm/i915: PSR VLV/CHV: Introduce setup, enable and disable functions

[Rodrigo Vivi]

The biggest difference from HSW/BDW PSR here is that VLV enable_source
function enables PSR but let it in Inactive state. So it might be called
on early stage along with setup and enable_sink ones.

v2: Rebase over intel_psr.c;
    Remove docs from static functions;
    Merge vlv_psr_active_on_pipe;
    Timeout for psr transition is 250us;
    Remove SRC_TRASMITTER_STATE;

Cc: Durgadoss R <durgadoss.r@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_psr.c | 154 ++++++++++++++++++++++++++++++++-------
 1 file changed, 129 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index c296a89..bdb28f2 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -81,6 +81,17 @@ bool intel_psr_is_enabled(struct drm_device *dev)
 	return (bool)dev_priv->psr.enabled;
 }
 
+static bool vlv_is_psr_active_on_pipe(struct drm_device *dev, int pipe)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	uint32_t val;
+
+	val = I915_READ(VLV_PSRSTAT(pipe)) &
+	      VLV_EDP_PSR_CURR_STATE_MASK;
+	return (val == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
+	       (val == VLV_EDP_PSR_ACTIVE_SF_UPDATE);
+}
+
 static void intel_psr_write_vsc(struct intel_dp *intel_dp,
 				    struct edp_vsc_psr *vsc_psr)
 {
@@ -110,7 +121,23 @@ static void intel_psr_write_vsc(struct intel_dp *intel_dp,
 	POSTING_READ(ctl_reg);
 }
 
-static void intel_psr_setup_vsc(struct intel_dp *intel_dp)
+static void vlv_psr_setup_vsc(struct intel_dp *intel_dp)
+{
+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+	struct drm_device *dev = intel_dig_port->base.base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
+	enum pipe pipe = to_intel_crtc(crtc)->pipe;
+	uint32_t val;
+
+	/* VLV auto-generate VSC package as per EDP 1.3 spec, Table 3.10 */
+	val  = I915_READ(VLV_VSCSDP(pipe));
+	val &= ~VLV_EDP_PSR_SDP_FREQ_MASK;
+	val |= VLV_EDP_PSR_SDP_FREQ_EVFRAME;
+	I915_WRITE(VLV_VSCSDP(pipe), val);
+}
+
+static void hsw_psr_setup_vsc(struct intel_dp *intel_dp)
 {
 	struct edp_vsc_psr psr_vsc;
 
@@ -123,7 +150,13 @@ static void intel_psr_setup_vsc(struct intel_dp *intel_dp)
 	intel_psr_write_vsc(intel_dp, &psr_vsc);
 }
 
-static void intel_psr_enable_sink(struct intel_dp *intel_dp)
+static void vlv_psr_enable_sink(struct intel_dp *intel_dp)
+{
+	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
+			   DP_PSR_ENABLE);
+}
+
+static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
 {
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	struct drm_device *dev = dig_port->base.base.dev;
@@ -167,7 +200,21 @@ static void intel_psr_enable_sink(struct intel_dp *intel_dp)
 		   (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
 }
 
-static void intel_psr_enable_source(struct intel_dp *intel_dp)
+static void vlv_psr_enable_source(struct intel_dp *intel_dp)
+{
+	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+	struct drm_device *dev = dig_port->base.base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_crtc *crtc = dig_port->base.base.crtc;
+	enum pipe pipe = to_intel_crtc(crtc)->pipe;
+
+	/* Transition from PSR_state 0 to PSR_state 1, i.e. PSR Inactive */
+	I915_WRITE(VLV_PSRCTL(pipe),
+		   VLV_EDP_PSR_MODE_SW_TIMER |
+		   VLV_EDP_PSR_ENABLE);
+}
+
+static void hsw_psr_enable_source(struct intel_dp *intel_dp)
 {
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	struct drm_device *dev = dig_port->base.base.dev;
@@ -247,7 +294,7 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
 	return true;
 }
 
-static void intel_psr_do_enable(struct intel_dp *intel_dp)
+static void intel_psr_activate(struct intel_dp *intel_dp)
 {
 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 	struct drm_device *dev = intel_dig_port->base.base.dev;
@@ -257,9 +304,12 @@ static void intel_psr_do_enable(struct intel_dp *intel_dp)
 	WARN_ON(dev_priv->psr.active);
 	lockdep_assert_held(&dev_priv->psr.lock);
 
-	/* Enable/Re-enable PSR on the host */
-	intel_psr_enable_source(intel_dp);
-
+	/* Enable/Re-enable PSR on the host
+	 * On HSW+ after we enable PSR on source it will activate it
+	 * as soon as it match configure idle_frame count. So
+	 * we just actually enable it here on activation time.
+	 */
+	hsw_psr_enable_source(intel_dp);
 	dev_priv->psr.active = true;
 }
 
@@ -296,37 +346,67 @@ void intel_psr_enable(struct intel_dp *intel_dp)
 
 	dev_priv->psr.busy_frontbuffer_bits = 0;
 
-	intel_psr_setup_vsc(intel_dp);
+	if (HAS_DDI(dev)) {
+		hsw_psr_setup_vsc(intel_dp);
 
-	/* Avoid continuous PSR exit by masking memup and hpd */
-	I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
-		   EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
+		/* Avoid continuous PSR exit by masking memup and hpd */
+		I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
+			   EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
 
-	/* Enable PSR on the panel */
-	intel_psr_enable_sink(intel_dp);
+		/* Enable PSR on the panel */
+		hsw_psr_enable_sink(intel_dp);
+	} else {
+		vlv_psr_setup_vsc(intel_dp);
+
+		/* Enable PSR on the panel */
+		vlv_psr_enable_sink(intel_dp);
+
+		/* On HSW+ enable_source also means go to PSR entry/active
+		 * state as soon as idle_frame achieved and here would be
+		 * to soon. However on VLV enable_source just enable PSR
+		 * but let it on inactive state. So we might do this prior
+		 * to active transition, i.e. here.
+		 */
+		vlv_psr_enable_source(intel_dp);
+	}
 
 	dev_priv->psr.enabled = intel_dp;
 unlock:
 	mutex_unlock(&dev_priv->psr.lock);
 }
 
-/**
- * intel_psr_disable - Disable PSR
- * @intel_dp: Intel DP
- *
- * This function needs to be called before disabling pipe.
- */
-void intel_psr_disable(struct intel_dp *intel_dp)
+static void vlv_psr_disable(struct intel_dp *intel_dp)
 {
 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 	struct drm_device *dev = intel_dig_port->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_crtc *intel_crtc =
+		to_intel_crtc(intel_dig_port->base.base.crtc);
+	uint32_t val;
 
-	mutex_lock(&dev_priv->psr.lock);
-	if (!dev_priv->psr.enabled) {
-		mutex_unlock(&dev_priv->psr.lock);
-		return;
+	if (dev_priv->psr.active) {
+		/* Put VLV PSR back to PSR_state 0 that is PSR Disabled. */
+		if (wait_for((I915_READ(VLV_PSRSTAT(intel_crtc->pipe)) &
+			      VLV_EDP_PSR_IN_TRANS) == 0, 0.250))
+			WARN(1, "PSR transition took longer than expected\n");
+
+		val = I915_READ(VLV_PSRCTL(intel_crtc->pipe));
+		val &= ~VLV_EDP_PSR_ACTIVE_ENTRY;
+		val &= ~VLV_EDP_PSR_ENABLE;
+		val &= ~VLV_EDP_PSR_MODE_MASK;
+		I915_WRITE(VLV_PSRCTL(intel_crtc->pipe), val);
+
+		dev_priv->psr.active = false;
+	} else {
+		WARN_ON(vlv_is_psr_active_on_pipe(dev, intel_crtc->pipe));
 	}
+}
+
+static void hsw_psr_disable(struct intel_dp *intel_dp)
+{
+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+	struct drm_device *dev = intel_dig_port->base.base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
 
 	if (dev_priv->psr.active) {
 		I915_WRITE(EDP_PSR_CTL(dev),
@@ -341,6 +421,30 @@ void intel_psr_disable(struct intel_dp *intel_dp)
 	} else {
 		WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
 	}
+}
+
+/**
+ * intel_psr_disable - Disable PSR
+ * @intel_dp: Intel DP
+ *
+ * This function needs to be called before disabling pipe.
+ */
+void intel_psr_disable(struct intel_dp *intel_dp)
+{
+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+	struct drm_device *dev = intel_dig_port->base.base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	mutex_lock(&dev_priv->psr.lock);
+	if (!dev_priv->psr.enabled) {
+		mutex_unlock(&dev_priv->psr.lock);
+		return;
+	}
+
+	if (HAS_DDI(dev))
+		hsw_psr_disable(intel_dp);
+	else
+		vlv_psr_disable(intel_dp);
 
 	dev_priv->psr.enabled = NULL;
 	mutex_unlock(&dev_priv->psr.lock);
@@ -379,7 +483,7 @@ static void intel_psr_work(struct work_struct *work)
 	if (dev_priv->psr.busy_frontbuffer_bits)
 		goto unlock;
 
-	intel_psr_do_enable(intel_dp);
+	intel_psr_activate(intel_dp);
 unlock:
 	mutex_unlock(&dev_priv->psr.lock);
 }
-- 
1.9.3

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Re: [PATCH 11/15] drm/i915: PSR VLV/CHV: Introduce setup, enable and disable functions

[R, Durgadoss]

>-----Original Message-----
>From: Vivi, Rodrigo
>Sent: Friday, November 14, 2014 10:23 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Vivi, Rodrigo; R, Durgadoss
>Subject: [PATCH 11/15] drm/i915: PSR VLV/CHV: Introduce setup, enable and disable functions
>
>The biggest difference from HSW/BDW PSR here is that VLV enable_source
>function enables PSR but let it in Inactive state. So it might be called
>on early stage along with setup and enable_sink ones.
>
>v2: Rebase over intel_psr.c;
>    Remove docs from static functions;
>    Merge vlv_psr_active_on_pipe;
>    Timeout for psr transition is 250us;
>    Remove SRC_TRASMITTER_STATE;

With SRC_TRANSMITTER_STATE not set to 1
explicitly, if entry/exit works, I would like to know what DPCD
register 71h is reading in your panel ?

I would expect bit 0 of 71h to be 1.
Is it the case ? Can we check once ?

Thanks,
Durga

>
>Cc: Durgadoss R <durgadoss.r@intel.com>
>Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>---
> drivers/gpu/drm/i915/intel_psr.c | 154 ++++++++++++++++++++++++++++++++-------
> 1 file changed, 129 insertions(+), 25 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
>index c296a89..bdb28f2 100644
>--- a/drivers/gpu/drm/i915/intel_psr.c
>+++ b/drivers/gpu/drm/i915/intel_psr.c
>@@ -81,6 +81,17 @@ bool intel_psr_is_enabled(struct drm_device *dev)
> 	return (bool)dev_priv->psr.enabled;
> }
>
>+static bool vlv_is_psr_active_on_pipe(struct drm_device *dev, int pipe)
>+{
>+	struct drm_i915_private *dev_priv = dev->dev_private;
>+	uint32_t val;
>+
>+	val = I915_READ(VLV_PSRSTAT(pipe)) &
>+	      VLV_EDP_PSR_CURR_STATE_MASK;
>+	return (val == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
>+	       (val == VLV_EDP_PSR_ACTIVE_SF_UPDATE);
>+}
>+
> static void intel_psr_write_vsc(struct intel_dp *intel_dp,
> 				    struct edp_vsc_psr *vsc_psr)
> {
>@@ -110,7 +121,23 @@ static void intel_psr_write_vsc(struct intel_dp *intel_dp,
> 	POSTING_READ(ctl_reg);
> }
>
>-static void intel_psr_setup_vsc(struct intel_dp *intel_dp)
>+static void vlv_psr_setup_vsc(struct intel_dp *intel_dp)
>+{
>+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>+	struct drm_device *dev = intel_dig_port->base.base.dev;
>+	struct drm_i915_private *dev_priv = dev->dev_private;
>+	struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
>+	enum pipe pipe = to_intel_crtc(crtc)->pipe;
>+	uint32_t val;
>+
>+	/* VLV auto-generate VSC package as per EDP 1.3 spec, Table 3.10 */
>+	val  = I915_READ(VLV_VSCSDP(pipe));
>+	val &= ~VLV_EDP_PSR_SDP_FREQ_MASK;
>+	val |= VLV_EDP_PSR_SDP_FREQ_EVFRAME;
>+	I915_WRITE(VLV_VSCSDP(pipe), val);
>+}
>+
>+static void hsw_psr_setup_vsc(struct intel_dp *intel_dp)
> {
> 	struct edp_vsc_psr psr_vsc;
>
>@@ -123,7 +150,13 @@ static void intel_psr_setup_vsc(struct intel_dp *intel_dp)
> 	intel_psr_write_vsc(intel_dp, &psr_vsc);
> }
>
>-static void intel_psr_enable_sink(struct intel_dp *intel_dp)
>+static void vlv_psr_enable_sink(struct intel_dp *intel_dp)
>+{
>+	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
>+			   DP_PSR_ENABLE);
>+}
>+
>+static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
> {
> 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> 	struct drm_device *dev = dig_port->base.base.dev;
>@@ -167,7 +200,21 @@ static void intel_psr_enable_sink(struct intel_dp *intel_dp)
> 		   (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
> }
>
>-static void intel_psr_enable_source(struct intel_dp *intel_dp)
>+static void vlv_psr_enable_source(struct intel_dp *intel_dp)
>+{
>+	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>+	struct drm_device *dev = dig_port->base.base.dev;
>+	struct drm_i915_private *dev_priv = dev->dev_private;
>+	struct drm_crtc *crtc = dig_port->base.base.crtc;
>+	enum pipe pipe = to_intel_crtc(crtc)->pipe;
>+
>+	/* Transition from PSR_state 0 to PSR_state 1, i.e. PSR Inactive */
>+	I915_WRITE(VLV_PSRCTL(pipe),
>+		   VLV_EDP_PSR_MODE_SW_TIMER |
>+		   VLV_EDP_PSR_ENABLE);
>+}
>+
>+static void hsw_psr_enable_source(struct intel_dp *intel_dp)
> {
> 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> 	struct drm_device *dev = dig_port->base.base.dev;
>@@ -247,7 +294,7 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
> 	return true;
> }
>
>-static void intel_psr_do_enable(struct intel_dp *intel_dp)
>+static void intel_psr_activate(struct intel_dp *intel_dp)
> {
> 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> 	struct drm_device *dev = intel_dig_port->base.base.dev;
>@@ -257,9 +304,12 @@ static void intel_psr_do_enable(struct intel_dp *intel_dp)
> 	WARN_ON(dev_priv->psr.active);
> 	lockdep_assert_held(&dev_priv->psr.lock);
>
>-	/* Enable/Re-enable PSR on the host */
>-	intel_psr_enable_source(intel_dp);
>-
>+	/* Enable/Re-enable PSR on the host
>+	 * On HSW+ after we enable PSR on source it will activate it
>+	 * as soon as it match configure idle_frame count. So
>+	 * we just actually enable it here on activation time.
>+	 */
>+	hsw_psr_enable_source(intel_dp);
> 	dev_priv->psr.active = true;
> }
>
>@@ -296,37 +346,67 @@ void intel_psr_enable(struct intel_dp *intel_dp)
>
> 	dev_priv->psr.busy_frontbuffer_bits = 0;
>
>-	intel_psr_setup_vsc(intel_dp);
>+	if (HAS_DDI(dev)) {
>+		hsw_psr_setup_vsc(intel_dp);
>
>-	/* Avoid continuous PSR exit by masking memup and hpd */
>-	I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
>-		   EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
>+		/* Avoid continuous PSR exit by masking memup and hpd */
>+		I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
>+			   EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
>
>-	/* Enable PSR on the panel */
>-	intel_psr_enable_sink(intel_dp);
>+		/* Enable PSR on the panel */
>+		hsw_psr_enable_sink(intel_dp);
>+	} else {
>+		vlv_psr_setup_vsc(intel_dp);
>+
>+		/* Enable PSR on the panel */
>+		vlv_psr_enable_sink(intel_dp);
>+
>+		/* On HSW+ enable_source also means go to PSR entry/active
>+		 * state as soon as idle_frame achieved and here would be
>+		 * to soon. However on VLV enable_source just enable PSR
>+		 * but let it on inactive state. So we might do this prior
>+		 * to active transition, i.e. here.
>+		 */
>+		vlv_psr_enable_source(intel_dp);
>+	}
>
> 	dev_priv->psr.enabled = intel_dp;
> unlock:
> 	mutex_unlock(&dev_priv->psr.lock);
> }
>
>-/**
>- * intel_psr_disable - Disable PSR
>- * @intel_dp: Intel DP
>- *
>- * This function needs to be called before disabling pipe.
>- */
>-void intel_psr_disable(struct intel_dp *intel_dp)
>+static void vlv_psr_disable(struct intel_dp *intel_dp)
> {
> 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> 	struct drm_device *dev = intel_dig_port->base.base.dev;
> 	struct drm_i915_private *dev_priv = dev->dev_private;
>+	struct intel_crtc *intel_crtc =
>+		to_intel_crtc(intel_dig_port->base.base.crtc);
>+	uint32_t val;
>
>-	mutex_lock(&dev_priv->psr.lock);
>-	if (!dev_priv->psr.enabled) {
>-		mutex_unlock(&dev_priv->psr.lock);
>-		return;
>+	if (dev_priv->psr.active) {
>+		/* Put VLV PSR back to PSR_state 0 that is PSR Disabled. */
>+		if (wait_for((I915_READ(VLV_PSRSTAT(intel_crtc->pipe)) &
>+			      VLV_EDP_PSR_IN_TRANS) == 0, 0.250))
>+			WARN(1, "PSR transition took longer than expected\n");
>+
>+		val = I915_READ(VLV_PSRCTL(intel_crtc->pipe));
>+		val &= ~VLV_EDP_PSR_ACTIVE_ENTRY;
>+		val &= ~VLV_EDP_PSR_ENABLE;
>+		val &= ~VLV_EDP_PSR_MODE_MASK;
>+		I915_WRITE(VLV_PSRCTL(intel_crtc->pipe), val);
>+
>+		dev_priv->psr.active = false;
>+	} else {
>+		WARN_ON(vlv_is_psr_active_on_pipe(dev, intel_crtc->pipe));
> 	}
>+}
>+
>+static void hsw_psr_disable(struct intel_dp *intel_dp)
>+{
>+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>+	struct drm_device *dev = intel_dig_port->base.base.dev;
>+	struct drm_i915_private *dev_priv = dev->dev_private;
>
> 	if (dev_priv->psr.active) {
> 		I915_WRITE(EDP_PSR_CTL(dev),
>@@ -341,6 +421,30 @@ void intel_psr_disable(struct intel_dp *intel_dp)
> 	} else {
> 		WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
> 	}
>+}
>+
>+/**
>+ * intel_psr_disable - Disable PSR
>+ * @intel_dp: Intel DP
>+ *
>+ * This function needs to be called before disabling pipe.
>+ */
>+void intel_psr_disable(struct intel_dp *intel_dp)
>+{
>+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>+	struct drm_device *dev = intel_dig_port->base.base.dev;
>+	struct drm_i915_private *dev_priv = dev->dev_private;
>+
>+	mutex_lock(&dev_priv->psr.lock);
>+	if (!dev_priv->psr.enabled) {
>+		mutex_unlock(&dev_priv->psr.lock);
>+		return;
>+	}
>+
>+	if (HAS_DDI(dev))
>+		hsw_psr_disable(intel_dp);
>+	else
>+		vlv_psr_disable(intel_dp);
>
> 	dev_priv->psr.enabled = NULL;
> 	mutex_unlock(&dev_priv->psr.lock);
>@@ -379,7 +483,7 @@ static void intel_psr_work(struct work_struct *work)
> 	if (dev_priv->psr.busy_frontbuffer_bits)
> 		goto unlock;
>
>-	intel_psr_do_enable(intel_dp);
>+	intel_psr_activate(intel_dp);
> unlock:
> 	mutex_unlock(&dev_priv->psr.lock);
> }
>--
>1.9.3

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Re: [PATCH 11/15] drm/i915: PSR VLV/CHV: Introduce setup, enable and disable functions

[Rodrigo Vivi]

On Tue, Nov 18, 2014 at 10:32 AM, R, Durgadoss <durgadoss.r@intel.com> wrote:
>>-----Original Message-----
>>From: Vivi, Rodrigo
>>Sent: Friday, November 14, 2014 10:23 PM
>>To: intel-gfx@lists.freedesktop.org
>>Cc: Vivi, Rodrigo; R, Durgadoss
>>Subject: [PATCH 11/15] drm/i915: PSR VLV/CHV: Introduce setup, enable and disable functions
>>
>>The biggest difference from HSW/BDW PSR here is that VLV enable_source
>>function enables PSR but let it in Inactive state. So it might be called
>>on early stage along with setup and enable_sink ones.
>>
>>v2: Rebase over intel_psr.c;
>>    Remove docs from static functions;
>>    Merge vlv_psr_active_on_pipe;
>>    Timeout for psr transition is 250us;
>>    Remove SRC_TRASMITTER_STATE;
>
> With SRC_TRANSMITTER_STATE not set to 1
> explicitly, if entry/exit works, I would like to know what DPCD
> register 71h is reading in your panel ?
>
> I would expect bit 0 of 71h to be 1.
> Is it the case ?

no. It is always 0.

DP_PSR_CAPS = 0xA

> Can we check once ?
>
> Thanks,
> Durga

What do you suggest? get SRC_TRANSMITTER_STATE back?

>
>>
>>Cc: Durgadoss R <durgadoss.r@intel.com>
>>Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>---
>> drivers/gpu/drm/i915/intel_psr.c | 154 ++++++++++++++++++++++++++++++++-------
>> 1 file changed, 129 insertions(+), 25 deletions(-)
>>
>>diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
>>index c296a89..bdb28f2 100644
>>--- a/drivers/gpu/drm/i915/intel_psr.c
>>+++ b/drivers/gpu/drm/i915/intel_psr.c
>>@@ -81,6 +81,17 @@ bool intel_psr_is_enabled(struct drm_device *dev)
>>       return (bool)dev_priv->psr.enabled;
>> }
>>
>>+static bool vlv_is_psr_active_on_pipe(struct drm_device *dev, int pipe)
>>+{
>>+      struct drm_i915_private *dev_priv = dev->dev_private;
>>+      uint32_t val;
>>+
>>+      val = I915_READ(VLV_PSRSTAT(pipe)) &
>>+            VLV_EDP_PSR_CURR_STATE_MASK;
>>+      return (val == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
>>+             (val == VLV_EDP_PSR_ACTIVE_SF_UPDATE);
>>+}
>>+
>> static void intel_psr_write_vsc(struct intel_dp *intel_dp,
>>                                   struct edp_vsc_psr *vsc_psr)
>> {
>>@@ -110,7 +121,23 @@ static void intel_psr_write_vsc(struct intel_dp *intel_dp,
>>       POSTING_READ(ctl_reg);
>> }
>>
>>-static void intel_psr_setup_vsc(struct intel_dp *intel_dp)
>>+static void vlv_psr_setup_vsc(struct intel_dp *intel_dp)
>>+{
>>+      struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>>+      struct drm_device *dev = intel_dig_port->base.base.dev;
>>+      struct drm_i915_private *dev_priv = dev->dev_private;
>>+      struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
>>+      enum pipe pipe = to_intel_crtc(crtc)->pipe;
>>+      uint32_t val;
>>+
>>+      /* VLV auto-generate VSC package as per EDP 1.3 spec, Table 3.10 */
>>+      val  = I915_READ(VLV_VSCSDP(pipe));
>>+      val &= ~VLV_EDP_PSR_SDP_FREQ_MASK;
>>+      val |= VLV_EDP_PSR_SDP_FREQ_EVFRAME;
>>+      I915_WRITE(VLV_VSCSDP(pipe), val);
>>+}
>>+
>>+static void hsw_psr_setup_vsc(struct intel_dp *intel_dp)
>> {
>>       struct edp_vsc_psr psr_vsc;
>>
>>@@ -123,7 +150,13 @@ static void intel_psr_setup_vsc(struct intel_dp *intel_dp)
>>       intel_psr_write_vsc(intel_dp, &psr_vsc);
>> }
>>
>>-static void intel_psr_enable_sink(struct intel_dp *intel_dp)
>>+static void vlv_psr_enable_sink(struct intel_dp *intel_dp)
>>+{
>>+      drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
>>+                         DP_PSR_ENABLE);
>>+}
>>+
>>+static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
>> {
>>       struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>>       struct drm_device *dev = dig_port->base.base.dev;
>>@@ -167,7 +200,21 @@ static void intel_psr_enable_sink(struct intel_dp *intel_dp)
>>                  (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
>> }
>>
>>-static void intel_psr_enable_source(struct intel_dp *intel_dp)
>>+static void vlv_psr_enable_source(struct intel_dp *intel_dp)
>>+{
>>+      struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>>+      struct drm_device *dev = dig_port->base.base.dev;
>>+      struct drm_i915_private *dev_priv = dev->dev_private;
>>+      struct drm_crtc *crtc = dig_port->base.base.crtc;
>>+      enum pipe pipe = to_intel_crtc(crtc)->pipe;
>>+
>>+      /* Transition from PSR_state 0 to PSR_state 1, i.e. PSR Inactive */
>>+      I915_WRITE(VLV_PSRCTL(pipe),
>>+                 VLV_EDP_PSR_MODE_SW_TIMER |
>>+                 VLV_EDP_PSR_ENABLE);
>>+}
>>+
>>+static void hsw_psr_enable_source(struct intel_dp *intel_dp)
>> {
>>       struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>>       struct drm_device *dev = dig_port->base.base.dev;
>>@@ -247,7 +294,7 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
>>       return true;
>> }
>>
>>-static void intel_psr_do_enable(struct intel_dp *intel_dp)
>>+static void intel_psr_activate(struct intel_dp *intel_dp)
>> {
>>       struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>>       struct drm_device *dev = intel_dig_port->base.base.dev;
>>@@ -257,9 +304,12 @@ static void intel_psr_do_enable(struct intel_dp *intel_dp)
>>       WARN_ON(dev_priv->psr.active);
>>       lockdep_assert_held(&dev_priv->psr.lock);
>>
>>-      /* Enable/Re-enable PSR on the host */
>>-      intel_psr_enable_source(intel_dp);
>>-
>>+      /* Enable/Re-enable PSR on the host
>>+       * On HSW+ after we enable PSR on source it will activate it
>>+       * as soon as it match configure idle_frame count. So
>>+       * we just actually enable it here on activation time.
>>+       */
>>+      hsw_psr_enable_source(intel_dp);
>>       dev_priv->psr.active = true;
>> }
>>
>>@@ -296,37 +346,67 @@ void intel_psr_enable(struct intel_dp *intel_dp)
>>
>>       dev_priv->psr.busy_frontbuffer_bits = 0;
>>
>>-      intel_psr_setup_vsc(intel_dp);
>>+      if (HAS_DDI(dev)) {
>>+              hsw_psr_setup_vsc(intel_dp);
>>
>>-      /* Avoid continuous PSR exit by masking memup and hpd */
>>-      I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
>>-                 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
>>+              /* Avoid continuous PSR exit by masking memup and hpd */
>>+              I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
>>+                         EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
>>
>>-      /* Enable PSR on the panel */
>>-      intel_psr_enable_sink(intel_dp);
>>+              /* Enable PSR on the panel */
>>+              hsw_psr_enable_sink(intel_dp);
>>+      } else {
>>+              vlv_psr_setup_vsc(intel_dp);
>>+
>>+              /* Enable PSR on the panel */
>>+              vlv_psr_enable_sink(intel_dp);
>>+
>>+              /* On HSW+ enable_source also means go to PSR entry/active
>>+               * state as soon as idle_frame achieved and here would be
>>+               * to soon. However on VLV enable_source just enable PSR
>>+               * but let it on inactive state. So we might do this prior
>>+               * to active transition, i.e. here.
>>+               */
>>+              vlv_psr_enable_source(intel_dp);
>>+      }
>>
>>       dev_priv->psr.enabled = intel_dp;
>> unlock:
>>       mutex_unlock(&dev_priv->psr.lock);
>> }
>>
>>-/**
>>- * intel_psr_disable - Disable PSR
>>- * @intel_dp: Intel DP
>>- *
>>- * This function needs to be called before disabling pipe.
>>- */
>>-void intel_psr_disable(struct intel_dp *intel_dp)
>>+static void vlv_psr_disable(struct intel_dp *intel_dp)
>> {
>>       struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>>       struct drm_device *dev = intel_dig_port->base.base.dev;
>>       struct drm_i915_private *dev_priv = dev->dev_private;
>>+      struct intel_crtc *intel_crtc =
>>+              to_intel_crtc(intel_dig_port->base.base.crtc);
>>+      uint32_t val;
>>
>>-      mutex_lock(&dev_priv->psr.lock);
>>-      if (!dev_priv->psr.enabled) {
>>-              mutex_unlock(&dev_priv->psr.lock);
>>-              return;
>>+      if (dev_priv->psr.active) {
>>+              /* Put VLV PSR back to PSR_state 0 that is PSR Disabled. */
>>+              if (wait_for((I915_READ(VLV_PSRSTAT(intel_crtc->pipe)) &
>>+                            VLV_EDP_PSR_IN_TRANS) == 0, 0.250))
>>+                      WARN(1, "PSR transition took longer than expected\n");
>>+
>>+              val = I915_READ(VLV_PSRCTL(intel_crtc->pipe));
>>+              val &= ~VLV_EDP_PSR_ACTIVE_ENTRY;
>>+              val &= ~VLV_EDP_PSR_ENABLE;
>>+              val &= ~VLV_EDP_PSR_MODE_MASK;
>>+              I915_WRITE(VLV_PSRCTL(intel_crtc->pipe), val);
>>+
>>+              dev_priv->psr.active = false;
>>+      } else {
>>+              WARN_ON(vlv_is_psr_active_on_pipe(dev, intel_crtc->pipe));
>>       }
>>+}
>>+
>>+static void hsw_psr_disable(struct intel_dp *intel_dp)
>>+{
>>+      struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>>+      struct drm_device *dev = intel_dig_port->base.base.dev;
>>+      struct drm_i915_private *dev_priv = dev->dev_private;
>>
>>       if (dev_priv->psr.active) {
>>               I915_WRITE(EDP_PSR_CTL(dev),
>>@@ -341,6 +421,30 @@ void intel_psr_disable(struct intel_dp *intel_dp)
>>       } else {
>>               WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
>>       }
>>+}
>>+
>>+/**
>>+ * intel_psr_disable - Disable PSR
>>+ * @intel_dp: Intel DP
>>+ *
>>+ * This function needs to be called before disabling pipe.
>>+ */
>>+void intel_psr_disable(struct intel_dp *intel_dp)
>>+{
>>+      struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>>+      struct drm_device *dev = intel_dig_port->base.base.dev;
>>+      struct drm_i915_private *dev_priv = dev->dev_private;
>>+
>>+      mutex_lock(&dev_priv->psr.lock);
>>+      if (!dev_priv->psr.enabled) {
>>+              mutex_unlock(&dev_priv->psr.lock);
>>+              return;
>>+      }
>>+
>>+      if (HAS_DDI(dev))
>>+              hsw_psr_disable(intel_dp);
>>+      else
>>+              vlv_psr_disable(intel_dp);
>>
>>       dev_priv->psr.enabled = NULL;
>>       mutex_unlock(&dev_priv->psr.lock);
>>@@ -379,7 +483,7 @@ static void intel_psr_work(struct work_struct *work)
>>       if (dev_priv->psr.busy_frontbuffer_bits)
>>               goto unlock;
>>
>>-      intel_psr_do_enable(intel_dp);
>>+      intel_psr_activate(intel_dp);
>> unlock:
>>       mutex_unlock(&dev_priv->psr.lock);
>> }
>>--
>>1.9.3
>
> _______________________________________________
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> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
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Re: [PATCH 11/15] drm/i915: PSR VLV/CHV: Introduce setup, enable and disable functions

[R, Durgadoss]

>-----Original Message-----
>From: Rodrigo Vivi [mailto:rodrigo.vivi@gmail.com]
>Sent: Wednesday, November 19, 2014 11:51 PM
>To: R, Durgadoss
>Cc: Vivi, Rodrigo; intel-gfx@lists.freedesktop.org
>Subject: Re: [Intel-gfx] [PATCH 11/15] drm/i915: PSR VLV/CHV: Introduce setup, enable and disable
>functions
>
>On Tue, Nov 18, 2014 at 10:32 AM, R, Durgadoss <durgadoss.r@intel.com> wrote:
>>>-----Original Message-----
>>>From: Vivi, Rodrigo
>>>Sent: Friday, November 14, 2014 10:23 PM
>>>To: intel-gfx@lists.freedesktop.org
>>>Cc: Vivi, Rodrigo; R, Durgadoss
>>>Subject: [PATCH 11/15] drm/i915: PSR VLV/CHV: Introduce setup, enable and disable functions
>>>
>>>The biggest difference from HSW/BDW PSR here is that VLV enable_source
>>>function enables PSR but let it in Inactive state. So it might be called
>>>on early stage along with setup and enable_sink ones.
>>>
>>>v2: Rebase over intel_psr.c;
>>>    Remove docs from static functions;
>>>    Merge vlv_psr_active_on_pipe;
>>>    Timeout for psr transition is 250us;
>>>    Remove SRC_TRASMITTER_STATE;
>>
>> With SRC_TRANSMITTER_STATE not set to 1
>> explicitly, if entry/exit works, I would like to know what DPCD
>> register 71h is reading in your panel ?
>>
>> I would expect bit 0 of 71h to be 1.
>> Is it the case ?
>
>no. It is always 0.
>
>DP_PSR_CAPS = 0xA

0xA ? could be.. but surprising how exit works
Without doing link training..
May be we are looking at 01h..?, but your
Description seems fine .. it is DP_PSR_CAPS.
Can we double check once ?

eDP spec v1.3 claims default setup time is 330 us.
So, I would expect bits[1:3] to be 0 (usually)

This is the DPCD hex dump from 00h to 0xf in the
Panels that I use: {from dmesg}
DPCD: 11 0a 84 41 00 00 01 c0 02 03 00 00 00 0b 00

>
>> Can we check once ?
>>
>> Thanks,
>> Durga
>
>What do you suggest? get SRC_TRANSMITTER_STATE back?

Yes. The reason I say is because not all panels come with
a 1 in that bit and ideally panels with a 0 in that bit 71h[0]
are supposed to require link training after PSR exit
when the main link is off. The main link will be off if we do
not set the SRC_TRANSMITTER_STATE bit to 1.

So, removing it is not safe in my opinion. I would suggest
Keeping it there. And also, the same bit in the DPCD as well.

Thanks,
Durga

>
>>
>>>
>>>Cc: Durgadoss R <durgadoss.r@intel.com>
>>>Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>>---
>>> drivers/gpu/drm/i915/intel_psr.c | 154 ++++++++++++++++++++++++++++++++-------
>>> 1 file changed, 129 insertions(+), 25 deletions(-)
>>>
>>>diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
>>>index c296a89..bdb28f2 100644
>>>--- a/drivers/gpu/drm/i915/intel_psr.c
>>>+++ b/drivers/gpu/drm/i915/intel_psr.c
>>>@@ -81,6 +81,17 @@ bool intel_psr_is_enabled(struct drm_device *dev)
>>>       return (bool)dev_priv->psr.enabled;
>>> }
>>>
>>>+static bool vlv_is_psr_active_on_pipe(struct drm_device *dev, int pipe)
>>>+{
>>>+      struct drm_i915_private *dev_priv = dev->dev_private;
>>>+      uint32_t val;
>>>+
>>>+      val = I915_READ(VLV_PSRSTAT(pipe)) &
>>>+            VLV_EDP_PSR_CURR_STATE_MASK;
>>>+      return (val == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
>>>+             (val == VLV_EDP_PSR_ACTIVE_SF_UPDATE);
>>>+}
>>>+
>>> static void intel_psr_write_vsc(struct intel_dp *intel_dp,
>>>                                   struct edp_vsc_psr *vsc_psr)
>>> {
>>>@@ -110,7 +121,23 @@ static void intel_psr_write_vsc(struct intel_dp *intel_dp,
>>>       POSTING_READ(ctl_reg);
>>> }
>>>
>>>-static void intel_psr_setup_vsc(struct intel_dp *intel_dp)
>>>+static void vlv_psr_setup_vsc(struct intel_dp *intel_dp)
>>>+{
>>>+      struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>>>+      struct drm_device *dev = intel_dig_port->base.base.dev;
>>>+      struct drm_i915_private *dev_priv = dev->dev_private;
>>>+      struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
>>>+      enum pipe pipe = to_intel_crtc(crtc)->pipe;
>>>+      uint32_t val;
>>>+
>>>+      /* VLV auto-generate VSC package as per EDP 1.3 spec, Table 3.10 */
>>>+      val  = I915_READ(VLV_VSCSDP(pipe));
>>>+      val &= ~VLV_EDP_PSR_SDP_FREQ_MASK;
>>>+      val |= VLV_EDP_PSR_SDP_FREQ_EVFRAME;
>>>+      I915_WRITE(VLV_VSCSDP(pipe), val);
>>>+}
>>>+
>>>+static void hsw_psr_setup_vsc(struct intel_dp *intel_dp)
>>> {
>>>       struct edp_vsc_psr psr_vsc;
>>>
>>>@@ -123,7 +150,13 @@ static void intel_psr_setup_vsc(struct intel_dp *intel_dp)
>>>       intel_psr_write_vsc(intel_dp, &psr_vsc);
>>> }
>>>
>>>-static void intel_psr_enable_sink(struct intel_dp *intel_dp)
>>>+static void vlv_psr_enable_sink(struct intel_dp *intel_dp)
>>>+{
>>>+      drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
>>>+                         DP_PSR_ENABLE);
>>>+}
>>>+
>>>+static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
>>> {
>>>       struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>>>       struct drm_device *dev = dig_port->base.base.dev;
>>>@@ -167,7 +200,21 @@ static void intel_psr_enable_sink(struct intel_dp *intel_dp)
>>>                  (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
>>> }
>>>
>>>-static void intel_psr_enable_source(struct intel_dp *intel_dp)
>>>+static void vlv_psr_enable_source(struct intel_dp *intel_dp)
>>>+{
>>>+      struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>>>+      struct drm_device *dev = dig_port->base.base.dev;
>>>+      struct drm_i915_private *dev_priv = dev->dev_private;
>>>+      struct drm_crtc *crtc = dig_port->base.base.crtc;
>>>+      enum pipe pipe = to_intel_crtc(crtc)->pipe;
>>>+
>>>+      /* Transition from PSR_state 0 to PSR_state 1, i.e. PSR Inactive */
>>>+      I915_WRITE(VLV_PSRCTL(pipe),
>>>+                 VLV_EDP_PSR_MODE_SW_TIMER |
>>>+                 VLV_EDP_PSR_ENABLE);
>>>+}
>>>+
>>>+static void hsw_psr_enable_source(struct intel_dp *intel_dp)
>>> {
>>>       struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>>>       struct drm_device *dev = dig_port->base.base.dev;
>>>@@ -247,7 +294,7 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
>>>       return true;
>>> }
>>>
>>>-static void intel_psr_do_enable(struct intel_dp *intel_dp)
>>>+static void intel_psr_activate(struct intel_dp *intel_dp)
>>> {
>>>       struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>>>       struct drm_device *dev = intel_dig_port->base.base.dev;
>>>@@ -257,9 +304,12 @@ static void intel_psr_do_enable(struct intel_dp *intel_dp)
>>>       WARN_ON(dev_priv->psr.active);
>>>       lockdep_assert_held(&dev_priv->psr.lock);
>>>
>>>-      /* Enable/Re-enable PSR on the host */
>>>-      intel_psr_enable_source(intel_dp);
>>>-
>>>+      /* Enable/Re-enable PSR on the host
>>>+       * On HSW+ after we enable PSR on source it will activate it
>>>+       * as soon as it match configure idle_frame count. So
>>>+       * we just actually enable it here on activation time.
>>>+       */
>>>+      hsw_psr_enable_source(intel_dp);
>>>       dev_priv->psr.active = true;
>>> }
>>>
>>>@@ -296,37 +346,67 @@ void intel_psr_enable(struct intel_dp *intel_dp)
>>>
>>>       dev_priv->psr.busy_frontbuffer_bits = 0;
>>>
>>>-      intel_psr_setup_vsc(intel_dp);
>>>+      if (HAS_DDI(dev)) {
>>>+              hsw_psr_setup_vsc(intel_dp);
>>>
>>>-      /* Avoid continuous PSR exit by masking memup and hpd */
>>>-      I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
>>>-                 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
>>>+              /* Avoid continuous PSR exit by masking memup and hpd */
>>>+              I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
>>>+                         EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
>>>
>>>-      /* Enable PSR on the panel */
>>>-      intel_psr_enable_sink(intel_dp);
>>>+              /* Enable PSR on the panel */
>>>+              hsw_psr_enable_sink(intel_dp);
>>>+      } else {
>>>+              vlv_psr_setup_vsc(intel_dp);
>>>+
>>>+              /* Enable PSR on the panel */
>>>+              vlv_psr_enable_sink(intel_dp);
>>>+
>>>+              /* On HSW+ enable_source also means go to PSR entry/active
>>>+               * state as soon as idle_frame achieved and here would be
>>>+               * to soon. However on VLV enable_source just enable PSR
>>>+               * but let it on inactive state. So we might do this prior
>>>+               * to active transition, i.e. here.
>>>+               */
>>>+              vlv_psr_enable_source(intel_dp);
>>>+      }
>>>
>>>       dev_priv->psr.enabled = intel_dp;
>>> unlock:
>>>       mutex_unlock(&dev_priv->psr.lock);
>>> }
>>>
>>>-/**
>>>- * intel_psr_disable - Disable PSR
>>>- * @intel_dp: Intel DP
>>>- *
>>>- * This function needs to be called before disabling pipe.
>>>- */
>>>-void intel_psr_disable(struct intel_dp *intel_dp)
>>>+static void vlv_psr_disable(struct intel_dp *intel_dp)
>>> {
>>>       struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>>>       struct drm_device *dev = intel_dig_port->base.base.dev;
>>>       struct drm_i915_private *dev_priv = dev->dev_private;
>>>+      struct intel_crtc *intel_crtc =
>>>+              to_intel_crtc(intel_dig_port->base.base.crtc);
>>>+      uint32_t val;
>>>
>>>-      mutex_lock(&dev_priv->psr.lock);
>>>-      if (!dev_priv->psr.enabled) {
>>>-              mutex_unlock(&dev_priv->psr.lock);
>>>-              return;
>>>+      if (dev_priv->psr.active) {
>>>+              /* Put VLV PSR back to PSR_state 0 that is PSR Disabled. */
>>>+              if (wait_for((I915_READ(VLV_PSRSTAT(intel_crtc->pipe)) &
>>>+                            VLV_EDP_PSR_IN_TRANS) == 0, 0.250))
>>>+                      WARN(1, "PSR transition took longer than expected\n");
>>>+
>>>+              val = I915_READ(VLV_PSRCTL(intel_crtc->pipe));
>>>+              val &= ~VLV_EDP_PSR_ACTIVE_ENTRY;
>>>+              val &= ~VLV_EDP_PSR_ENABLE;
>>>+              val &= ~VLV_EDP_PSR_MODE_MASK;
>>>+              I915_WRITE(VLV_PSRCTL(intel_crtc->pipe), val);
>>>+
>>>+              dev_priv->psr.active = false;
>>>+      } else {
>>>+              WARN_ON(vlv_is_psr_active_on_pipe(dev, intel_crtc->pipe));
>>>       }
>>>+}
>>>+
>>>+static void hsw_psr_disable(struct intel_dp *intel_dp)
>>>+{
>>>+      struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>>>+      struct drm_device *dev = intel_dig_port->base.base.dev;
>>>+      struct drm_i915_private *dev_priv = dev->dev_private;
>>>
>>>       if (dev_priv->psr.active) {
>>>               I915_WRITE(EDP_PSR_CTL(dev),
>>>@@ -341,6 +421,30 @@ void intel_psr_disable(struct intel_dp *intel_dp)
>>>       } else {
>>>               WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
>>>       }
>>>+}
>>>+
>>>+/**
>>>+ * intel_psr_disable - Disable PSR
>>>+ * @intel_dp: Intel DP
>>>+ *
>>>+ * This function needs to be called before disabling pipe.
>>>+ */
>>>+void intel_psr_disable(struct intel_dp *intel_dp)
>>>+{
>>>+      struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>>>+      struct drm_device *dev = intel_dig_port->base.base.dev;
>>>+      struct drm_i915_private *dev_priv = dev->dev_private;
>>>+
>>>+      mutex_lock(&dev_priv->psr.lock);
>>>+      if (!dev_priv->psr.enabled) {
>>>+              mutex_unlock(&dev_priv->psr.lock);
>>>+              return;
>>>+      }
>>>+
>>>+      if (HAS_DDI(dev))
>>>+              hsw_psr_disable(intel_dp);
>>>+      else
>>>+              vlv_psr_disable(intel_dp);
>>>
>>>       dev_priv->psr.enabled = NULL;
>>>       mutex_unlock(&dev_priv->psr.lock);
>>>@@ -379,7 +483,7 @@ static void intel_psr_work(struct work_struct *work)
>>>       if (dev_priv->psr.busy_frontbuffer_bits)
>>>               goto unlock;
>>>
>>>-      intel_psr_do_enable(intel_dp);
>>>+      intel_psr_activate(intel_dp);
>>> unlock:
>>>       mutex_unlock(&dev_priv->psr.lock);
>>> }
>>>--
>>>1.9.3
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>
>
>--
>Rodrigo Vivi
>Blog: http://blog.vivi.eng.br
_______________________________________________
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH] drm/i915: PSR VLV/CHV: Introduce setup, enable and disable functions

[Rodrigo Vivi]

The biggest difference from HSW/BDW PSR here is that VLV enable_source
function enables PSR but let it in Inactive state. So it might be called
on early stage along with setup and enable_sink ones.

v2: Rebase over intel_psr.c;
    Remove docs from static functions;
    Merge vlv_psr_active_on_pipe;
    Timeout for psr transition is 250us;
    Remove SRC_TRASMITTER_STATE;

v3: Rebase after is_psr_enabled function got removed;
    Get SRC_TRANSMITTER_STATE back to be on the safe side since
    default for panels is to require link training on exit when
    main link off;
    As pointed out by Durgadoss msecs_to_jiffies used on wait_for only uses int,
    so let's use 1 instead. Althought the 1/4 of this is needed for the
    transition let's use 1 for simplicity;

Cc: Durgadoss R <durgadoss.r@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_psr.c | 155 ++++++++++++++++++++++++++++++++-------
 1 file changed, 130 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 576ad02..30f341a 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -61,6 +61,17 @@ static bool is_edp_psr(struct intel_dp *intel_dp)
 	return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
 }
 
+static bool vlv_is_psr_active_on_pipe(struct drm_device *dev, int pipe)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	uint32_t val;
+
+	val = I915_READ(VLV_PSRSTAT(pipe)) &
+	      VLV_EDP_PSR_CURR_STATE_MASK;
+	return (val == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
+	       (val == VLV_EDP_PSR_ACTIVE_SF_UPDATE);
+}
+
 static void intel_psr_write_vsc(struct intel_dp *intel_dp,
 				    struct edp_vsc_psr *vsc_psr)
 {
@@ -90,7 +101,23 @@ static void intel_psr_write_vsc(struct intel_dp *intel_dp,
 	POSTING_READ(ctl_reg);
 }
 
-static void intel_psr_setup_vsc(struct intel_dp *intel_dp)
+static void vlv_psr_setup_vsc(struct intel_dp *intel_dp)
+{
+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+	struct drm_device *dev = intel_dig_port->base.base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
+	enum pipe pipe = to_intel_crtc(crtc)->pipe;
+	uint32_t val;
+
+	/* VLV auto-generate VSC package as per EDP 1.3 spec, Table 3.10 */
+	val  = I915_READ(VLV_VSCSDP(pipe));
+	val &= ~VLV_EDP_PSR_SDP_FREQ_MASK;
+	val |= VLV_EDP_PSR_SDP_FREQ_EVFRAME;
+	I915_WRITE(VLV_VSCSDP(pipe), val);
+}
+
+static void hsw_psr_setup_vsc(struct intel_dp *intel_dp)
 {
 	struct edp_vsc_psr psr_vsc;
 
@@ -103,7 +130,13 @@ static void intel_psr_setup_vsc(struct intel_dp *intel_dp)
 	intel_psr_write_vsc(intel_dp, &psr_vsc);
 }
 
-static void intel_psr_enable_sink(struct intel_dp *intel_dp)
+static void vlv_psr_enable_sink(struct intel_dp *intel_dp)
+{
+	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
+			   DP_PSR_ENABLE);
+}
+
+static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
 {
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	struct drm_device *dev = dig_port->base.base.dev;
@@ -147,7 +180,22 @@ static void intel_psr_enable_sink(struct intel_dp *intel_dp)
 		   (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
 }
 
-static void intel_psr_enable_source(struct intel_dp *intel_dp)
+static void vlv_psr_enable_source(struct intel_dp *intel_dp)
+{
+	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+	struct drm_device *dev = dig_port->base.base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_crtc *crtc = dig_port->base.base.crtc;
+	enum pipe pipe = to_intel_crtc(crtc)->pipe;
+
+	/* Transition from PSR_state 0 to PSR_state 1, i.e. PSR Inactive */
+	I915_WRITE(VLV_PSRCTL(pipe),
+		   VLV_EDP_PSR_MODE_SW_TIMER |
+		   VLV_EDP_PSR_SRC_TRANSMITTER_STATE |
+		   VLV_EDP_PSR_ENABLE);
+}
+
+static void hsw_psr_enable_source(struct intel_dp *intel_dp)
 {
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	struct drm_device *dev = dig_port->base.base.dev;
@@ -225,7 +273,7 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
 	return true;
 }
 
-static void intel_psr_do_enable(struct intel_dp *intel_dp)
+static void intel_psr_activate(struct intel_dp *intel_dp)
 {
 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 	struct drm_device *dev = intel_dig_port->base.base.dev;
@@ -235,9 +283,12 @@ static void intel_psr_do_enable(struct intel_dp *intel_dp)
 	WARN_ON(dev_priv->psr.active);
 	lockdep_assert_held(&dev_priv->psr.lock);
 
-	/* Enable/Re-enable PSR on the host */
-	intel_psr_enable_source(intel_dp);
-
+	/* Enable/Re-enable PSR on the host
+	 * On HSW+ after we enable PSR on source it will activate it
+	 * as soon as it match configure idle_frame count. So
+	 * we just actually enable it here on activation time.
+	 */
+	hsw_psr_enable_source(intel_dp);
 	dev_priv->psr.active = true;
 }
 
@@ -274,37 +325,67 @@ void intel_psr_enable(struct intel_dp *intel_dp)
 
 	dev_priv->psr.busy_frontbuffer_bits = 0;
 
-	intel_psr_setup_vsc(intel_dp);
+	if (HAS_DDI(dev)) {
+		hsw_psr_setup_vsc(intel_dp);
 
-	/* Avoid continuous PSR exit by masking memup and hpd */
-	I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
-		   EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
+		/* Avoid continuous PSR exit by masking memup and hpd */
+		I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
+			   EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
 
-	/* Enable PSR on the panel */
-	intel_psr_enable_sink(intel_dp);
+		/* Enable PSR on the panel */
+		hsw_psr_enable_sink(intel_dp);
+	} else {
+		vlv_psr_setup_vsc(intel_dp);
+
+		/* Enable PSR on the panel */
+		vlv_psr_enable_sink(intel_dp);
+
+		/* On HSW+ enable_source also means go to PSR entry/active
+		 * state as soon as idle_frame achieved and here would be
+		 * to soon. However on VLV enable_source just enable PSR
+		 * but let it on inactive state. So we might do this prior
+		 * to active transition, i.e. here.
+		 */
+		vlv_psr_enable_source(intel_dp);
+	}
 
 	dev_priv->psr.enabled = intel_dp;
 unlock:
 	mutex_unlock(&dev_priv->psr.lock);
 }
 
-/**
- * intel_psr_disable - Disable PSR
- * @intel_dp: Intel DP
- *
- * This function needs to be called before disabling pipe.
- */
-void intel_psr_disable(struct intel_dp *intel_dp)
+static void vlv_psr_disable(struct intel_dp *intel_dp)
 {
 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 	struct drm_device *dev = intel_dig_port->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_crtc *intel_crtc =
+		to_intel_crtc(intel_dig_port->base.base.crtc);
+	uint32_t val;
 
-	mutex_lock(&dev_priv->psr.lock);
-	if (!dev_priv->psr.enabled) {
-		mutex_unlock(&dev_priv->psr.lock);
-		return;
+	if (dev_priv->psr.active) {
+		/* Put VLV PSR back to PSR_state 0 that is PSR Disabled. */
+		if (wait_for((I915_READ(VLV_PSRSTAT(intel_crtc->pipe)) &
+			      VLV_EDP_PSR_IN_TRANS) == 0, 1))
+			WARN(1, "PSR transition took longer than expected\n");
+
+		val = I915_READ(VLV_PSRCTL(intel_crtc->pipe));
+		val &= ~VLV_EDP_PSR_ACTIVE_ENTRY;
+		val &= ~VLV_EDP_PSR_ENABLE;
+		val &= ~VLV_EDP_PSR_MODE_MASK;
+		I915_WRITE(VLV_PSRCTL(intel_crtc->pipe), val);
+
+		dev_priv->psr.active = false;
+	} else {
+		WARN_ON(vlv_is_psr_active_on_pipe(dev, intel_crtc->pipe));
 	}
+}
+
+static void hsw_psr_disable(struct intel_dp *intel_dp)
+{
+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+	struct drm_device *dev = intel_dig_port->base.base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
 
 	if (dev_priv->psr.active) {
 		I915_WRITE(EDP_PSR_CTL(dev),
@@ -319,6 +400,30 @@ void intel_psr_disable(struct intel_dp *intel_dp)
 	} else {
 		WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
 	}
+}
+
+/**
+ * intel_psr_disable - Disable PSR
+ * @intel_dp: Intel DP
+ *
+ * This function needs to be called before disabling pipe.
+ */
+void intel_psr_disable(struct intel_dp *intel_dp)
+{
+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+	struct drm_device *dev = intel_dig_port->base.base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	mutex_lock(&dev_priv->psr.lock);
+	if (!dev_priv->psr.enabled) {
+		mutex_unlock(&dev_priv->psr.lock);
+		return;
+	}
+
+	if (HAS_DDI(dev))
+		hsw_psr_disable(intel_dp);
+	else
+		vlv_psr_disable(intel_dp);
 
 	dev_priv->psr.enabled = NULL;
 	mutex_unlock(&dev_priv->psr.lock);
@@ -357,7 +462,7 @@ static void intel_psr_work(struct work_struct *work)
 	if (dev_priv->psr.busy_frontbuffer_bits)
 		goto unlock;
 
-	intel_psr_do_enable(intel_dp);
+	intel_psr_activate(intel_dp);
 unlock:
 	mutex_unlock(&dev_priv->psr.lock);
 }
-- 
1.9.3

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Re: [PATCH] drm/i915: PSR VLV/CHV: Introduce setup, enable and disable functions

[R, Durgadoss]

>-----Original Message-----
>From: Vivi, Rodrigo
>Sent: Wednesday, November 19, 2014 9:07 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Vivi, Rodrigo; R, Durgadoss
>Subject: [PATCH] drm/i915: PSR VLV/CHV: Introduce setup, enable and disable functions
>
>The biggest difference from HSW/BDW PSR here is that VLV enable_source
>function enables PSR but let it in Inactive state. So it might be called
>on early stage along with setup and enable_sink ones.
>
>v2: Rebase over intel_psr.c;
>    Remove docs from static functions;
>    Merge vlv_psr_active_on_pipe;
>    Timeout for psr transition is 250us;
>    Remove SRC_TRASMITTER_STATE;
>
>v3: Rebase after is_psr_enabled function got removed;
>    Get SRC_TRANSMITTER_STATE back to be on the safe side since
>    default for panels is to require link training on exit when
>    main link off;
>    As pointed out by Durgadoss msecs_to_jiffies used on wait_for only uses int,
>    so let's use 1 instead. Althought the 1/4 of this is needed for the
>    transition let's use 1 for simplicity;
>
>Cc: Durgadoss R <durgadoss.r@intel.com>
>Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>---
> drivers/gpu/drm/i915/intel_psr.c | 155 ++++++++++++++++++++++++++++++++-------
> 1 file changed, 130 insertions(+), 25 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
>index 576ad02..30f341a 100644
>--- a/drivers/gpu/drm/i915/intel_psr.c
>+++ b/drivers/gpu/drm/i915/intel_psr.c
>@@ -61,6 +61,17 @@ static bool is_edp_psr(struct intel_dp *intel_dp)
> 	return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
> }
>
>+static bool vlv_is_psr_active_on_pipe(struct drm_device *dev, int pipe)
>+{
>+	struct drm_i915_private *dev_priv = dev->dev_private;
>+	uint32_t val;
>+
>+	val = I915_READ(VLV_PSRSTAT(pipe)) &
>+	      VLV_EDP_PSR_CURR_STATE_MASK;
>+	return (val == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
>+	       (val == VLV_EDP_PSR_ACTIVE_SF_UPDATE);
>+}
>+
> static void intel_psr_write_vsc(struct intel_dp *intel_dp,
> 				    struct edp_vsc_psr *vsc_psr)
> {
>@@ -90,7 +101,23 @@ static void intel_psr_write_vsc(struct intel_dp *intel_dp,
> 	POSTING_READ(ctl_reg);
> }
>
>-static void intel_psr_setup_vsc(struct intel_dp *intel_dp)
>+static void vlv_psr_setup_vsc(struct intel_dp *intel_dp)
>+{
>+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>+	struct drm_device *dev = intel_dig_port->base.base.dev;
>+	struct drm_i915_private *dev_priv = dev->dev_private;
>+	struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
>+	enum pipe pipe = to_intel_crtc(crtc)->pipe;
>+	uint32_t val;
>+
>+	/* VLV auto-generate VSC package as per EDP 1.3 spec, Table 3.10 */
>+	val  = I915_READ(VLV_VSCSDP(pipe));
>+	val &= ~VLV_EDP_PSR_SDP_FREQ_MASK;
>+	val |= VLV_EDP_PSR_SDP_FREQ_EVFRAME;
>+	I915_WRITE(VLV_VSCSDP(pipe), val);
>+}
>+
>+static void hsw_psr_setup_vsc(struct intel_dp *intel_dp)
> {
> 	struct edp_vsc_psr psr_vsc;
>
>@@ -103,7 +130,13 @@ static void intel_psr_setup_vsc(struct intel_dp *intel_dp)
> 	intel_psr_write_vsc(intel_dp, &psr_vsc);
> }
>
>-static void intel_psr_enable_sink(struct intel_dp *intel_dp)
>+static void vlv_psr_enable_sink(struct intel_dp *intel_dp)
>+{
>+	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
>+			   DP_PSR_ENABLE);
>+}
>+
>+static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
> {
> 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> 	struct drm_device *dev = dig_port->base.base.dev;
>@@ -147,7 +180,22 @@ static void intel_psr_enable_sink(struct intel_dp *intel_dp)
> 		   (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
> }
>
>-static void intel_psr_enable_source(struct intel_dp *intel_dp)
>+static void vlv_psr_enable_source(struct intel_dp *intel_dp)
>+{
>+	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>+	struct drm_device *dev = dig_port->base.base.dev;
>+	struct drm_i915_private *dev_priv = dev->dev_private;
>+	struct drm_crtc *crtc = dig_port->base.base.crtc;
>+	enum pipe pipe = to_intel_crtc(crtc)->pipe;
>+
>+	/* Transition from PSR_state 0 to PSR_state 1, i.e. PSR Inactive */
>+	I915_WRITE(VLV_PSRCTL(pipe),
>+		   VLV_EDP_PSR_MODE_SW_TIMER |
>+		   VLV_EDP_PSR_SRC_TRANSMITTER_STATE |

This looks safe for now.

Reviewed-by: Durgadoss R <durgadoss.r@intel.com>

Thanks,
Durga

>+		   VLV_EDP_PSR_ENABLE);
>+}
>+
>+static void hsw_psr_enable_source(struct intel_dp *intel_dp)
> {
> 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> 	struct drm_device *dev = dig_port->base.base.dev;
>@@ -225,7 +273,7 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
> 	return true;
> }
>
>-static void intel_psr_do_enable(struct intel_dp *intel_dp)
>+static void intel_psr_activate(struct intel_dp *intel_dp)
> {
> 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> 	struct drm_device *dev = intel_dig_port->base.base.dev;
>@@ -235,9 +283,12 @@ static void intel_psr_do_enable(struct intel_dp *intel_dp)
> 	WARN_ON(dev_priv->psr.active);
> 	lockdep_assert_held(&dev_priv->psr.lock);
>
>-	/* Enable/Re-enable PSR on the host */
>-	intel_psr_enable_source(intel_dp);
>-
>+	/* Enable/Re-enable PSR on the host
>+	 * On HSW+ after we enable PSR on source it will activate it
>+	 * as soon as it match configure idle_frame count. So
>+	 * we just actually enable it here on activation time.
>+	 */
>+	hsw_psr_enable_source(intel_dp);
> 	dev_priv->psr.active = true;
> }
>
>@@ -274,37 +325,67 @@ void intel_psr_enable(struct intel_dp *intel_dp)
>
> 	dev_priv->psr.busy_frontbuffer_bits = 0;
>
>-	intel_psr_setup_vsc(intel_dp);
>+	if (HAS_DDI(dev)) {
>+		hsw_psr_setup_vsc(intel_dp);
>
>-	/* Avoid continuous PSR exit by masking memup and hpd */
>-	I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
>-		   EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
>+		/* Avoid continuous PSR exit by masking memup and hpd */
>+		I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
>+			   EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
>
>-	/* Enable PSR on the panel */
>-	intel_psr_enable_sink(intel_dp);
>+		/* Enable PSR on the panel */
>+		hsw_psr_enable_sink(intel_dp);
>+	} else {
>+		vlv_psr_setup_vsc(intel_dp);
>+
>+		/* Enable PSR on the panel */
>+		vlv_psr_enable_sink(intel_dp);
>+
>+		/* On HSW+ enable_source also means go to PSR entry/active
>+		 * state as soon as idle_frame achieved and here would be
>+		 * to soon. However on VLV enable_source just enable PSR
>+		 * but let it on inactive state. So we might do this prior
>+		 * to active transition, i.e. here.
>+		 */
>+		vlv_psr_enable_source(intel_dp);
>+	}
>
> 	dev_priv->psr.enabled = intel_dp;
> unlock:
> 	mutex_unlock(&dev_priv->psr.lock);
> }
>
>-/**
>- * intel_psr_disable - Disable PSR
>- * @intel_dp: Intel DP
>- *
>- * This function needs to be called before disabling pipe.
>- */
>-void intel_psr_disable(struct intel_dp *intel_dp)
>+static void vlv_psr_disable(struct intel_dp *intel_dp)
> {
> 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> 	struct drm_device *dev = intel_dig_port->base.base.dev;
> 	struct drm_i915_private *dev_priv = dev->dev_private;
>+	struct intel_crtc *intel_crtc =
>+		to_intel_crtc(intel_dig_port->base.base.crtc);
>+	uint32_t val;
>
>-	mutex_lock(&dev_priv->psr.lock);
>-	if (!dev_priv->psr.enabled) {
>-		mutex_unlock(&dev_priv->psr.lock);
>-		return;
>+	if (dev_priv->psr.active) {
>+		/* Put VLV PSR back to PSR_state 0 that is PSR Disabled. */
>+		if (wait_for((I915_READ(VLV_PSRSTAT(intel_crtc->pipe)) &
>+			      VLV_EDP_PSR_IN_TRANS) == 0, 1))
>+			WARN(1, "PSR transition took longer than expected\n");
>+
>+		val = I915_READ(VLV_PSRCTL(intel_crtc->pipe));
>+		val &= ~VLV_EDP_PSR_ACTIVE_ENTRY;
>+		val &= ~VLV_EDP_PSR_ENABLE;
>+		val &= ~VLV_EDP_PSR_MODE_MASK;
>+		I915_WRITE(VLV_PSRCTL(intel_crtc->pipe), val);
>+
>+		dev_priv->psr.active = false;
>+	} else {
>+		WARN_ON(vlv_is_psr_active_on_pipe(dev, intel_crtc->pipe));
> 	}
>+}
>+
>+static void hsw_psr_disable(struct intel_dp *intel_dp)
>+{
>+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>+	struct drm_device *dev = intel_dig_port->base.base.dev;
>+	struct drm_i915_private *dev_priv = dev->dev_private;
>
> 	if (dev_priv->psr.active) {
> 		I915_WRITE(EDP_PSR_CTL(dev),
>@@ -319,6 +400,30 @@ void intel_psr_disable(struct intel_dp *intel_dp)
> 	} else {
> 		WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
> 	}
>+}
>+
>+/**
>+ * intel_psr_disable - Disable PSR
>+ * @intel_dp: Intel DP
>+ *
>+ * This function needs to be called before disabling pipe.
>+ */
>+void intel_psr_disable(struct intel_dp *intel_dp)
>+{
>+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>+	struct drm_device *dev = intel_dig_port->base.base.dev;
>+	struct drm_i915_private *dev_priv = dev->dev_private;
>+
>+	mutex_lock(&dev_priv->psr.lock);
>+	if (!dev_priv->psr.enabled) {
>+		mutex_unlock(&dev_priv->psr.lock);
>+		return;
>+	}
>+
>+	if (HAS_DDI(dev))
>+		hsw_psr_disable(intel_dp);
>+	else
>+		vlv_psr_disable(intel_dp);
>
> 	dev_priv->psr.enabled = NULL;
> 	mutex_unlock(&dev_priv->psr.lock);
>@@ -357,7 +462,7 @@ static void intel_psr_work(struct work_struct *work)
> 	if (dev_priv->psr.busy_frontbuffer_bits)
> 		goto unlock;
>
>-	intel_psr_do_enable(intel_dp);
>+	intel_psr_activate(intel_dp);
> unlock:
> 	mutex_unlock(&dev_priv->psr.lock);
> }
>--
>1.9.3

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Re: [PATCH 11/15] drm/i915: PSR VLV/CHV: Introduce setup, enable and disable functions

[Rodrigo Vivi]

On Wed, Nov 19, 2014 at 11:22 AM, R, Durgadoss <durgadoss.r@intel.com> wrote:
>>-----Original Message-----
>>From: Rodrigo Vivi [mailto:rodrigo.vivi@gmail.com]
>>Sent: Wednesday, November 19, 2014 11:51 PM
>>To: R, Durgadoss
>>Cc: Vivi, Rodrigo; intel-gfx@lists.freedesktop.org
>>Subject: Re: [Intel-gfx] [PATCH 11/15] drm/i915: PSR VLV/CHV: Introduce setup, enable and disable
>>functions
>>
>>On Tue, Nov 18, 2014 at 10:32 AM, R, Durgadoss <durgadoss.r@intel.com> wrote:
>>>>-----Original Message-----
>>>>From: Vivi, Rodrigo
>>>>Sent: Friday, November 14, 2014 10:23 PM
>>>>To: intel-gfx@lists.freedesktop.org
>>>>Cc: Vivi, Rodrigo; R, Durgadoss
>>>>Subject: [PATCH 11/15] drm/i915: PSR VLV/CHV: Introduce setup, enable and disable functions
>>>>
>>>>The biggest difference from HSW/BDW PSR here is that VLV enable_source
>>>>function enables PSR but let it in Inactive state. So it might be called
>>>>on early stage along with setup and enable_sink ones.
>>>>
>>>>v2: Rebase over intel_psr.c;
>>>>    Remove docs from static functions;
>>>>    Merge vlv_psr_active_on_pipe;
>>>>    Timeout for psr transition is 250us;
>>>>    Remove SRC_TRASMITTER_STATE;
>>>
>>> With SRC_TRANSMITTER_STATE not set to 1
>>> explicitly, if entry/exit works, I would like to know what DPCD
>>> register 71h is reading in your panel ?
>>>
>>> I would expect bit 0 of 71h to be 1.
>>> Is it the case ?
>>
>>no. It is always 0.
>>
>>DP_PSR_CAPS = 0xA
>
> 0xA ? could be.. but surprising how exit works
> Without doing link training..
> May be we are looking at 01h..?, but your
> Description seems fine .. it is DP_PSR_CAPS.
> Can we double check once ?


+       u8 caps;
        drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
                           DP_PSR_ENABLE);
+
+       drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_CAPS,
+                          &caps);
+       DRM_ERROR("PSR Caps %x\n", caps);


The works part is that if I

+ drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_CAPS,
                          DP_PSR_NO_TRAIN_ON_EXIT);

and read again it is still 0xA

>
> eDP spec v1.3 claims default setup time is 330 us.
> So, I would expect bits[1:3] to be 0 (usually)
>
> This is the DPCD hex dump from 00h to 0xf in the
> Panels that I use: {from dmesg}
> DPCD: 11 0a 84 41 00 00 01 c0 02 03 00 00 00 0b 00

My one is

DPCD: 12 0a 82 41 00 00 01 80 02 00 00 00 0f 0b 00

and it is funny but even with different platforms and apparently
different panel I get the same... but maybe just a coincidence with
similar panels...

>
>>
>>> Can we check once ?
>>>
>>> Thanks,
>>> Durga
>>
>>What do you suggest? get SRC_TRANSMITTER_STATE back?
>
> Yes. The reason I say is because not all panels come with
> a 1 in that bit and ideally panels with a 0 in that bit 71h[0]
> are supposed to require link training after PSR exit
> when the main link is off. The main link will be off if we do
> not set the SRC_TRANSMITTER_STATE bit to 1.

Ok, I'm resending with SRC_TRANSMITTER_STATE back to 1.

>
> So, removing it is not safe in my opinion. I would suggest
> Keeping it there. And also, the same bit in the DPCD as well.

However I'm not sure about setting PSR_CAPS to 1 since my attempt here
still shows 0xA when reading it right after writing it.

>
> Thanks,
> Durga
>
>>
>>>
>>>>
>>>>Cc: Durgadoss R <durgadoss.r@intel.com>
>>>>Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>>>---
>>>> drivers/gpu/drm/i915/intel_psr.c | 154 ++++++++++++++++++++++++++++++++-------
>>>> 1 file changed, 129 insertions(+), 25 deletions(-)
>>>>
>>>>diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
>>>>index c296a89..bdb28f2 100644
>>>>--- a/drivers/gpu/drm/i915/intel_psr.c
>>>>+++ b/drivers/gpu/drm/i915/intel_psr.c
>>>>@@ -81,6 +81,17 @@ bool intel_psr_is_enabled(struct drm_device *dev)
>>>>       return (bool)dev_priv->psr.enabled;
>>>> }
>>>>
>>>>+static bool vlv_is_psr_active_on_pipe(struct drm_device *dev, int pipe)
>>>>+{
>>>>+      struct drm_i915_private *dev_priv = dev->dev_private;
>>>>+      uint32_t val;
>>>>+
>>>>+      val = I915_READ(VLV_PSRSTAT(pipe)) &
>>>>+            VLV_EDP_PSR_CURR_STATE_MASK;
>>>>+      return (val == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
>>>>+             (val == VLV_EDP_PSR_ACTIVE_SF_UPDATE);
>>>>+}
>>>>+
>>>> static void intel_psr_write_vsc(struct intel_dp *intel_dp,
>>>>                                   struct edp_vsc_psr *vsc_psr)
>>>> {
>>>>@@ -110,7 +121,23 @@ static void intel_psr_write_vsc(struct intel_dp *intel_dp,
>>>>       POSTING_READ(ctl_reg);
>>>> }
>>>>
>>>>-static void intel_psr_setup_vsc(struct intel_dp *intel_dp)
>>>>+static void vlv_psr_setup_vsc(struct intel_dp *intel_dp)
>>>>+{
>>>>+      struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>>>>+      struct drm_device *dev = intel_dig_port->base.base.dev;
>>>>+      struct drm_i915_private *dev_priv = dev->dev_private;
>>>>+      struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
>>>>+      enum pipe pipe = to_intel_crtc(crtc)->pipe;
>>>>+      uint32_t val;
>>>>+
>>>>+      /* VLV auto-generate VSC package as per EDP 1.3 spec, Table 3.10 */
>>>>+      val  = I915_READ(VLV_VSCSDP(pipe));
>>>>+      val &= ~VLV_EDP_PSR_SDP_FREQ_MASK;
>>>>+      val |= VLV_EDP_PSR_SDP_FREQ_EVFRAME;
>>>>+      I915_WRITE(VLV_VSCSDP(pipe), val);
>>>>+}
>>>>+
>>>>+static void hsw_psr_setup_vsc(struct intel_dp *intel_dp)
>>>> {
>>>>       struct edp_vsc_psr psr_vsc;
>>>>
>>>>@@ -123,7 +150,13 @@ static void intel_psr_setup_vsc(struct intel_dp *intel_dp)
>>>>       intel_psr_write_vsc(intel_dp, &psr_vsc);
>>>> }
>>>>
>>>>-static void intel_psr_enable_sink(struct intel_dp *intel_dp)
>>>>+static void vlv_psr_enable_sink(struct intel_dp *intel_dp)
>>>>+{
>>>>+      drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
>>>>+                         DP_PSR_ENABLE);
>>>>+}
>>>>+
>>>>+static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
>>>> {
>>>>       struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>>>>       struct drm_device *dev = dig_port->base.base.dev;
>>>>@@ -167,7 +200,21 @@ static void intel_psr_enable_sink(struct intel_dp *intel_dp)
>>>>                  (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
>>>> }
>>>>
>>>>-static void intel_psr_enable_source(struct intel_dp *intel_dp)
>>>>+static void vlv_psr_enable_source(struct intel_dp *intel_dp)
>>>>+{
>>>>+      struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>>>>+      struct drm_device *dev = dig_port->base.base.dev;
>>>>+      struct drm_i915_private *dev_priv = dev->dev_private;
>>>>+      struct drm_crtc *crtc = dig_port->base.base.crtc;
>>>>+      enum pipe pipe = to_intel_crtc(crtc)->pipe;
>>>>+
>>>>+      /* Transition from PSR_state 0 to PSR_state 1, i.e. PSR Inactive */
>>>>+      I915_WRITE(VLV_PSRCTL(pipe),
>>>>+                 VLV_EDP_PSR_MODE_SW_TIMER |
>>>>+                 VLV_EDP_PSR_ENABLE);
>>>>+}
>>>>+
>>>>+static void hsw_psr_enable_source(struct intel_dp *intel_dp)
>>>> {
>>>>       struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>>>>       struct drm_device *dev = dig_port->base.base.dev;
>>>>@@ -247,7 +294,7 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
>>>>       return true;
>>>> }
>>>>
>>>>-static void intel_psr_do_enable(struct intel_dp *intel_dp)
>>>>+static void intel_psr_activate(struct intel_dp *intel_dp)
>>>> {
>>>>       struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>>>>       struct drm_device *dev = intel_dig_port->base.base.dev;
>>>>@@ -257,9 +304,12 @@ static void intel_psr_do_enable(struct intel_dp *intel_dp)
>>>>       WARN_ON(dev_priv->psr.active);
>>>>       lockdep_assert_held(&dev_priv->psr.lock);
>>>>
>>>>-      /* Enable/Re-enable PSR on the host */
>>>>-      intel_psr_enable_source(intel_dp);
>>>>-
>>>>+      /* Enable/Re-enable PSR on the host
>>>>+       * On HSW+ after we enable PSR on source it will activate it
>>>>+       * as soon as it match configure idle_frame count. So
>>>>+       * we just actually enable it here on activation time.
>>>>+       */
>>>>+      hsw_psr_enable_source(intel_dp);
>>>>       dev_priv->psr.active = true;
>>>> }
>>>>
>>>>@@ -296,37 +346,67 @@ void intel_psr_enable(struct intel_dp *intel_dp)
>>>>
>>>>       dev_priv->psr.busy_frontbuffer_bits = 0;
>>>>
>>>>-      intel_psr_setup_vsc(intel_dp);
>>>>+      if (HAS_DDI(dev)) {
>>>>+              hsw_psr_setup_vsc(intel_dp);
>>>>
>>>>-      /* Avoid continuous PSR exit by masking memup and hpd */
>>>>-      I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
>>>>-                 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
>>>>+              /* Avoid continuous PSR exit by masking memup and hpd */
>>>>+              I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
>>>>+                         EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
>>>>
>>>>-      /* Enable PSR on the panel */
>>>>-      intel_psr_enable_sink(intel_dp);
>>>>+              /* Enable PSR on the panel */
>>>>+              hsw_psr_enable_sink(intel_dp);
>>>>+      } else {
>>>>+              vlv_psr_setup_vsc(intel_dp);
>>>>+
>>>>+              /* Enable PSR on the panel */
>>>>+              vlv_psr_enable_sink(intel_dp);
>>>>+
>>>>+              /* On HSW+ enable_source also means go to PSR entry/active
>>>>+               * state as soon as idle_frame achieved and here would be
>>>>+               * to soon. However on VLV enable_source just enable PSR
>>>>+               * but let it on inactive state. So we might do this prior
>>>>+               * to active transition, i.e. here.
>>>>+               */
>>>>+              vlv_psr_enable_source(intel_dp);
>>>>+      }
>>>>
>>>>       dev_priv->psr.enabled = intel_dp;
>>>> unlock:
>>>>       mutex_unlock(&dev_priv->psr.lock);
>>>> }
>>>>
>>>>-/**
>>>>- * intel_psr_disable - Disable PSR
>>>>- * @intel_dp: Intel DP
>>>>- *
>>>>- * This function needs to be called before disabling pipe.
>>>>- */
>>>>-void intel_psr_disable(struct intel_dp *intel_dp)
>>>>+static void vlv_psr_disable(struct intel_dp *intel_dp)
>>>> {
>>>>       struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>>>>       struct drm_device *dev = intel_dig_port->base.base.dev;
>>>>       struct drm_i915_private *dev_priv = dev->dev_private;
>>>>+      struct intel_crtc *intel_crtc =
>>>>+              to_intel_crtc(intel_dig_port->base.base.crtc);
>>>>+      uint32_t val;
>>>>
>>>>-      mutex_lock(&dev_priv->psr.lock);
>>>>-      if (!dev_priv->psr.enabled) {
>>>>-              mutex_unlock(&dev_priv->psr.lock);
>>>>-              return;
>>>>+      if (dev_priv->psr.active) {
>>>>+              /* Put VLV PSR back to PSR_state 0 that is PSR Disabled. */
>>>>+              if (wait_for((I915_READ(VLV_PSRSTAT(intel_crtc->pipe)) &
>>>>+                            VLV_EDP_PSR_IN_TRANS) == 0, 0.250))
>>>>+                      WARN(1, "PSR transition took longer than expected\n");
>>>>+
>>>>+              val = I915_READ(VLV_PSRCTL(intel_crtc->pipe));
>>>>+              val &= ~VLV_EDP_PSR_ACTIVE_ENTRY;
>>>>+              val &= ~VLV_EDP_PSR_ENABLE;
>>>>+              val &= ~VLV_EDP_PSR_MODE_MASK;
>>>>+              I915_WRITE(VLV_PSRCTL(intel_crtc->pipe), val);
>>>>+
>>>>+              dev_priv->psr.active = false;
>>>>+      } else {
>>>>+              WARN_ON(vlv_is_psr_active_on_pipe(dev, intel_crtc->pipe));
>>>>       }
>>>>+}
>>>>+
>>>>+static void hsw_psr_disable(struct intel_dp *intel_dp)
>>>>+{
>>>>+      struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>>>>+      struct drm_device *dev = intel_dig_port->base.base.dev;
>>>>+      struct drm_i915_private *dev_priv = dev->dev_private;
>>>>
>>>>       if (dev_priv->psr.active) {
>>>>               I915_WRITE(EDP_PSR_CTL(dev),
>>>>@@ -341,6 +421,30 @@ void intel_psr_disable(struct intel_dp *intel_dp)
>>>>       } else {
>>>>               WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
>>>>       }
>>>>+}
>>>>+
>>>>+/**
>>>>+ * intel_psr_disable - Disable PSR
>>>>+ * @intel_dp: Intel DP
>>>>+ *
>>>>+ * This function needs to be called before disabling pipe.
>>>>+ */
>>>>+void intel_psr_disable(struct intel_dp *intel_dp)
>>>>+{
>>>>+      struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>>>>+      struct drm_device *dev = intel_dig_port->base.base.dev;
>>>>+      struct drm_i915_private *dev_priv = dev->dev_private;
>>>>+
>>>>+      mutex_lock(&dev_priv->psr.lock);
>>>>+      if (!dev_priv->psr.enabled) {
>>>>+              mutex_unlock(&dev_priv->psr.lock);
>>>>+              return;
>>>>+      }
>>>>+
>>>>+      if (HAS_DDI(dev))
>>>>+              hsw_psr_disable(intel_dp);
>>>>+      else
>>>>+              vlv_psr_disable(intel_dp);
>>>>
>>>>       dev_priv->psr.enabled = NULL;
>>>>       mutex_unlock(&dev_priv->psr.lock);
>>>>@@ -379,7 +483,7 @@ static void intel_psr_work(struct work_struct *work)
>>>>       if (dev_priv->psr.busy_frontbuffer_bits)
>>>>               goto unlock;
>>>>
>>>>-      intel_psr_do_enable(intel_dp);
>>>>+      intel_psr_activate(intel_dp);
>>>> unlock:
>>>>       mutex_unlock(&dev_priv->psr.lock);
>>>> }
>>>>--
>>>>1.9.3
>>>
>>> _______________________________________________
>>> Intel-gfx mailing list
>>> Intel-gfx@lists.freedesktop.org
>>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>
>>
>>
>>--
>>Rodrigo Vivi
>>Blog: http://blog.vivi.eng.br



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
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[PATCH 12/15] drm/i915: VLV/CHV PSR Software timer mode

[Rodrigo Vivi]

This patch introduces exit/activate functions for PSR
on VLV+. Since on VLV+ HW cannot track frame updates and force PSR
exit let's use fully SW tracking available.

v2: Rebase over intel_psr.c;
    Remove Single Frame update transitioning from state 3 to 5 directly;
    Fake a software invalidation for sprites and cursor so we don't miss
    any screen update;

Cc: Durgadoss R <durgadoss.r@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_psr.c | 96 ++++++++++++++++++++++++++++++++++------
 1 file changed, 83 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index bdb28f2..b2a4ee7 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -214,6 +214,23 @@ static void vlv_psr_enable_source(struct intel_dp *intel_dp)
 		   VLV_EDP_PSR_ENABLE);
 }
 
+static void vlv_psr_activate(struct intel_dp *intel_dp)
+{
+	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+	struct drm_device *dev = dig_port->base.base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_crtc *crtc = dig_port->base.base.crtc;
+	enum pipe pipe = to_intel_crtc(crtc)->pipe;
+
+	/* Let's do the transition from PSR_state 1 to PSR_state 2
+	 * that is PSR transition to active - static frame transmission.
+	 * Then Hardware is responsible for the transition to PSR_state 3
+	 * that is PSR active - no Remote Frame Buffer (RFB) update.
+	 */
+	I915_WRITE(VLV_PSRCTL(pipe), I915_READ(VLV_PSRCTL(pipe)) |
+		   VLV_EDP_PSR_ACTIVE_ENTRY);
+}
+
 static void hsw_psr_enable_source(struct intel_dp *intel_dp)
 {
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
@@ -304,12 +321,16 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
 	WARN_ON(dev_priv->psr.active);
 	lockdep_assert_held(&dev_priv->psr.lock);
 
-	/* Enable/Re-enable PSR on the host
-	 * On HSW+ after we enable PSR on source it will activate it
-	 * as soon as it match configure idle_frame count. So
-	 * we just actually enable it here on activation time.
-	 */
-	hsw_psr_enable_source(intel_dp);
+	/* Enable/Re-enable PSR on the host */
+	if (HAS_DDI(dev))
+		/* On HSW+ after we enable PSR on source it will activate it
+		 * as soon as it match configure idle_frame count. So
+		 * we just actually enable it here on activation time.
+		 */
+		hsw_psr_enable_source(intel_dp);
+	else
+		vlv_psr_activate(intel_dp);
+
 	dev_priv->psr.active = true;
 }
 
@@ -457,18 +478,27 @@ static void intel_psr_work(struct work_struct *work)
 	struct drm_i915_private *dev_priv =
 		container_of(work, typeof(*dev_priv), psr.work.work);
 	struct intel_dp *intel_dp = dev_priv->psr.enabled;
+	struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
+	enum pipe pipe = to_intel_crtc(crtc)->pipe;
 
 	/* We have to make sure PSR is ready for re-enable
 	 * otherwise it keeps disabled until next full enable/disable cycle.
 	 * PSR might take some time to get fully disabled
 	 * and be ready for re-enable.
 	 */
-	if (wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev_priv->dev)) &
-		      EDP_PSR_STATUS_STATE_MASK) == 0, 50)) {
-		DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
-		return;
+	if (HAS_DDI(dev_priv->dev)) {
+		if (wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev_priv->dev)) &
+			      EDP_PSR_STATUS_STATE_MASK) == 0, 50)) {
+			DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
+			return;
+		}
+	} else {
+		if (wait_for((I915_READ(VLV_PSRSTAT(pipe)) &
+			      VLV_EDP_PSR_IN_TRANS) == 0, 0.250)) {
+			DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
+			return;
+		}
 	}
-
 	mutex_lock(&dev_priv->psr.lock);
 	intel_dp = dev_priv->psr.enabled;
 
@@ -491,17 +521,47 @@ unlock:
 static void intel_psr_exit(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_dp *intel_dp = dev_priv->psr.enabled;
+	struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
+	enum pipe pipe = to_intel_crtc(crtc)->pipe;
+	u32 val;
 
-	if (dev_priv->psr.active) {
-		u32 val = I915_READ(EDP_PSR_CTL(dev));
+	if (!dev_priv->psr.active)
+		return;
+
+	if (HAS_DDI(dev)) {
+		val = I915_READ(EDP_PSR_CTL(dev));
 
 		WARN_ON(!(val & EDP_PSR_ENABLE));
 
 		I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
 
 		dev_priv->psr.active = false;
+	} else {
+		val = I915_READ(VLV_PSRCTL(pipe));
+
+		/* Here we do the transition from PSR_state 3 to PSR_state 5
+		 * directly once PSR State 4 that is active with single frame
+		 * update can be skipped. PSR_state 5 that is PSR exit then
+		 * Hardware is responsible to transition back to PSR_state 1
+		 * that is PSR inactive. Same state after
+		 * vlv_edp_psr_enable_source.
+		 */
+		val &= ~VLV_EDP_PSR_ACTIVE_ENTRY;
+		I915_WRITE(VLV_PSRCTL(pipe), val);
+
+		/* Send AUX wake up - Spec says after transitioning to PSR
+		 * active we have to send AUX wake up by writing 01h in DPCD
+		 * 600h of sink device.
+		 * XXX: This might slow down the transition, but without this
+		 * HW doesn't complete the transition to PSR_state 1 and we
+		 * never get the screen updated.
+		 */
+		drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
+				   DP_SET_POWER_D0);
 	}
 
+	dev_priv->psr.active = false;
 }
 
 /**
@@ -579,6 +639,16 @@ void intel_psr_flush(struct drm_device *dev,
 	    (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
 		intel_psr_exit(dev);
 
+	/* On Valleyview and Cherryview we don't use hardware tracking so
+	 * sprite plane updates or cursor moves don't result in a psr
+	 * invalidating. Which means we need to manually fake this in
+	 * software for all flushes, not just when we've seen a preceding
+	 * invalidation through frontbuffer rendering. */
+	if (!HAS_DDI(dev) &&
+	    ((frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)) ||
+	     (frontbuffer_bits & INTEL_FRONTBUFFER_CURSOR(pipe))))
+		intel_psr_exit(dev);
+
 	if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
 		schedule_delayed_work(&dev_priv->psr.work,
 				      msecs_to_jiffies(100));
-- 
1.9.3

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Re: [PATCH 12/15] drm/i915: VLV/CHV PSR Software timer mode

[R, Durgadoss]

>-----Original Message-----
>From: Vivi, Rodrigo
>Sent: Friday, November 14, 2014 10:23 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Vivi, Rodrigo; R, Durgadoss
>Subject: [PATCH 12/15] drm/i915: VLV/CHV PSR Software timer mode
>
>This patch introduces exit/activate functions for PSR
>on VLV+. Since on VLV+ HW cannot track frame updates and force PSR
>exit let's use fully SW tracking available.
>
>v2: Rebase over intel_psr.c;
>    Remove Single Frame update transitioning from state 3 to 5 directly;
>    Fake a software invalidation for sprites and cursor so we don't miss
>    any screen update;
>
>Cc: Durgadoss R <durgadoss.r@intel.com>
>Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>---
> drivers/gpu/drm/i915/intel_psr.c | 96 ++++++++++++++++++++++++++++++++++------
> 1 file changed, 83 insertions(+), 13 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
>index bdb28f2..b2a4ee7 100644
>--- a/drivers/gpu/drm/i915/intel_psr.c
>+++ b/drivers/gpu/drm/i915/intel_psr.c
>@@ -214,6 +214,23 @@ static void vlv_psr_enable_source(struct intel_dp *intel_dp)
> 		   VLV_EDP_PSR_ENABLE);
> }
>
>+static void vlv_psr_activate(struct intel_dp *intel_dp)
>+{
>+	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>+	struct drm_device *dev = dig_port->base.base.dev;
>+	struct drm_i915_private *dev_priv = dev->dev_private;
>+	struct drm_crtc *crtc = dig_port->base.base.crtc;
>+	enum pipe pipe = to_intel_crtc(crtc)->pipe;
>+
>+	/* Let's do the transition from PSR_state 1 to PSR_state 2
>+	 * that is PSR transition to active - static frame transmission.
>+	 * Then Hardware is responsible for the transition to PSR_state 3
>+	 * that is PSR active - no Remote Frame Buffer (RFB) update.
>+	 */
>+	I915_WRITE(VLV_PSRCTL(pipe), I915_READ(VLV_PSRCTL(pipe)) |
>+		   VLV_EDP_PSR_ACTIVE_ENTRY);
>+}
>+
> static void hsw_psr_enable_source(struct intel_dp *intel_dp)
> {
> 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>@@ -304,12 +321,16 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
> 	WARN_ON(dev_priv->psr.active);
> 	lockdep_assert_held(&dev_priv->psr.lock);
>
>-	/* Enable/Re-enable PSR on the host
>-	 * On HSW+ after we enable PSR on source it will activate it
>-	 * as soon as it match configure idle_frame count. So
>-	 * we just actually enable it here on activation time.
>-	 */
>-	hsw_psr_enable_source(intel_dp);
>+	/* Enable/Re-enable PSR on the host */
>+	if (HAS_DDI(dev))
>+		/* On HSW+ after we enable PSR on source it will activate it
>+		 * as soon as it match configure idle_frame count. So
>+		 * we just actually enable it here on activation time.
>+		 */
>+		hsw_psr_enable_source(intel_dp);
>+	else
>+		vlv_psr_activate(intel_dp);
>+
> 	dev_priv->psr.active = true;
> }
>
>@@ -457,18 +478,27 @@ static void intel_psr_work(struct work_struct *work)
> 	struct drm_i915_private *dev_priv =
> 		container_of(work, typeof(*dev_priv), psr.work.work);
> 	struct intel_dp *intel_dp = dev_priv->psr.enabled;
>+	struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
>+	enum pipe pipe = to_intel_crtc(crtc)->pipe;
>
> 	/* We have to make sure PSR is ready for re-enable
> 	 * otherwise it keeps disabled until next full enable/disable cycle.
> 	 * PSR might take some time to get fully disabled
> 	 * and be ready for re-enable.
> 	 */
>-	if (wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev_priv->dev)) &
>-		      EDP_PSR_STATUS_STATE_MASK) == 0, 50)) {
>-		DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
>-		return;
>+	if (HAS_DDI(dev_priv->dev)) {
>+		if (wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev_priv->dev)) &
>+			      EDP_PSR_STATUS_STATE_MASK) == 0, 50)) {
>+			DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
>+			return;
>+		}
>+	} else {
>+		if (wait_for((I915_READ(VLV_PSRSTAT(pipe)) &
>+			      VLV_EDP_PSR_IN_TRANS) == 0, 0.250)) {

I didn't know wait_for takes floats ;)

>+			DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
>+			return;
>+		}
> 	}
>-
> 	mutex_lock(&dev_priv->psr.lock);
> 	intel_dp = dev_priv->psr.enabled;
>
>@@ -491,17 +521,47 @@ unlock:
> static void intel_psr_exit(struct drm_device *dev)
> {
> 	struct drm_i915_private *dev_priv = dev->dev_private;
>+	struct intel_dp *intel_dp = dev_priv->psr.enabled;
>+	struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
>+	enum pipe pipe = to_intel_crtc(crtc)->pipe;
>+	u32 val;
>
>-	if (dev_priv->psr.active) {
>-		u32 val = I915_READ(EDP_PSR_CTL(dev));
>+	if (!dev_priv->psr.active)
>+		return;
>+
>+	if (HAS_DDI(dev)) {
>+		val = I915_READ(EDP_PSR_CTL(dev));
>
> 		WARN_ON(!(val & EDP_PSR_ENABLE));
>
> 		I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
>
> 		dev_priv->psr.active = false;
>+	} else {
>+		val = I915_READ(VLV_PSRCTL(pipe));
>+
>+		/* Here we do the transition from PSR_state 3 to PSR_state 5
>+		 * directly once PSR State 4 that is active with single frame
>+		 * update can be skipped. PSR_state 5 that is PSR exit then
>+		 * Hardware is responsible to transition back to PSR_state 1
>+		 * that is PSR inactive. Same state after
>+		 * vlv_edp_psr_enable_source.
>+		 */
>+		val &= ~VLV_EDP_PSR_ACTIVE_ENTRY;
>+		I915_WRITE(VLV_PSRCTL(pipe), val);
>+
>+		/* Send AUX wake up - Spec says after transitioning to PSR
>+		 * active we have to send AUX wake up by writing 01h in DPCD
>+		 * 600h of sink device.
>+		 * XXX: This might slow down the transition, but without this
>+		 * HW doesn't complete the transition to PSR_state 1 and we
>+		 * never get the screen updated.
>+		 */
>+		drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
>+				   DP_SET_POWER_D0);
> 	}
>
>+	dev_priv->psr.active = false;
> }
>
> /**
>@@ -579,6 +639,16 @@ void intel_psr_flush(struct drm_device *dev,
> 	    (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
> 		intel_psr_exit(dev);
>
>+	/* On Valleyview and Cherryview we don't use hardware tracking so
>+	 * sprite plane updates or cursor moves don't result in a psr

s/psr/PSR for consistency

>+	 * invalidating. Which means we need to manually fake this in
>+	 * software for all flushes, not just when we've seen a preceding
>+	 * invalidation through frontbuffer rendering. */

Nitpick..can we follow the earlier style of commenting..
*/ to come in the next line.

With that feel free to add my:
Reviewed-by: Durgadoss R <durgadoss.r@intel.com>

Thanks,
Durga

>+	if (!HAS_DDI(dev) &&
>+	    ((frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)) ||
>+	     (frontbuffer_bits & INTEL_FRONTBUFFER_CURSOR(pipe))))
>+		intel_psr_exit(dev);
>+
> 	if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
> 		schedule_delayed_work(&dev_priv->psr.work,
> 				      msecs_to_jiffies(100));
>--
>1.9.3

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[PATCH] drm/i915: VLV/CHV PSR Software timer mode

[Rodrigo Vivi]

This patch introduces exit/activate functions for PSR
on VLV+. Since on VLV+ HW cannot track frame updates and force PSR
exit let's use fully SW tracking available.

v2: Rebase over intel_psr.c;
    Remove Single Frame update transitioning from state 3 to 5 directly;
    Fake a software invalidation for sprites and cursor so we don't miss
    any screen update;

v3: As pointed out by Durgadoss msecs_to_jiffies used on wait_for only uses int,
    so let's use 1 instead. Althought the 1/4 of this is needed for the
    transition let's use 1 for simplicity;
    Also fix comments as suggested by Durgadoss

Cc: Durgadoss R <durgadoss.r@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_psr.c | 97 ++++++++++++++++++++++++++++++++++------
 1 file changed, 84 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 30f341a..dd0e6e0 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -195,6 +195,23 @@ static void vlv_psr_enable_source(struct intel_dp *intel_dp)
 		   VLV_EDP_PSR_ENABLE);
 }
 
+static void vlv_psr_activate(struct intel_dp *intel_dp)
+{
+	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+	struct drm_device *dev = dig_port->base.base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_crtc *crtc = dig_port->base.base.crtc;
+	enum pipe pipe = to_intel_crtc(crtc)->pipe;
+
+	/* Let's do the transition from PSR_state 1 to PSR_state 2
+	 * that is PSR transition to active - static frame transmission.
+	 * Then Hardware is responsible for the transition to PSR_state 3
+	 * that is PSR active - no Remote Frame Buffer (RFB) update.
+	 */
+	I915_WRITE(VLV_PSRCTL(pipe), I915_READ(VLV_PSRCTL(pipe)) |
+		   VLV_EDP_PSR_ACTIVE_ENTRY);
+}
+
 static void hsw_psr_enable_source(struct intel_dp *intel_dp)
 {
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
@@ -283,12 +300,16 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
 	WARN_ON(dev_priv->psr.active);
 	lockdep_assert_held(&dev_priv->psr.lock);
 
-	/* Enable/Re-enable PSR on the host
-	 * On HSW+ after we enable PSR on source it will activate it
-	 * as soon as it match configure idle_frame count. So
-	 * we just actually enable it here on activation time.
-	 */
-	hsw_psr_enable_source(intel_dp);
+	/* Enable/Re-enable PSR on the host */
+	if (HAS_DDI(dev))
+		/* On HSW+ after we enable PSR on source it will activate it
+		 * as soon as it match configure idle_frame count. So
+		 * we just actually enable it here on activation time.
+		 */
+		hsw_psr_enable_source(intel_dp);
+	else
+		vlv_psr_activate(intel_dp);
+
 	dev_priv->psr.active = true;
 }
 
@@ -436,18 +457,27 @@ static void intel_psr_work(struct work_struct *work)
 	struct drm_i915_private *dev_priv =
 		container_of(work, typeof(*dev_priv), psr.work.work);
 	struct intel_dp *intel_dp = dev_priv->psr.enabled;
+	struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
+	enum pipe pipe = to_intel_crtc(crtc)->pipe;
 
 	/* We have to make sure PSR is ready for re-enable
 	 * otherwise it keeps disabled until next full enable/disable cycle.
 	 * PSR might take some time to get fully disabled
 	 * and be ready for re-enable.
 	 */
-	if (wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev_priv->dev)) &
-		      EDP_PSR_STATUS_STATE_MASK) == 0, 50)) {
-		DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
-		return;
+	if (HAS_DDI(dev_priv->dev)) {
+		if (wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev_priv->dev)) &
+			      EDP_PSR_STATUS_STATE_MASK) == 0, 50)) {
+			DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
+			return;
+		}
+	} else {
+		if (wait_for((I915_READ(VLV_PSRSTAT(pipe)) &
+			      VLV_EDP_PSR_IN_TRANS) == 0, 1)) {
+			DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
+			return;
+		}
 	}
-
 	mutex_lock(&dev_priv->psr.lock);
 	intel_dp = dev_priv->psr.enabled;
 
@@ -470,17 +500,47 @@ unlock:
 static void intel_psr_exit(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_dp *intel_dp = dev_priv->psr.enabled;
+	struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
+	enum pipe pipe = to_intel_crtc(crtc)->pipe;
+	u32 val;
 
-	if (dev_priv->psr.active) {
-		u32 val = I915_READ(EDP_PSR_CTL(dev));
+	if (!dev_priv->psr.active)
+		return;
+
+	if (HAS_DDI(dev)) {
+		val = I915_READ(EDP_PSR_CTL(dev));
 
 		WARN_ON(!(val & EDP_PSR_ENABLE));
 
 		I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
 
 		dev_priv->psr.active = false;
+	} else {
+		val = I915_READ(VLV_PSRCTL(pipe));
+
+		/* Here we do the transition from PSR_state 3 to PSR_state 5
+		 * directly once PSR State 4 that is active with single frame
+		 * update can be skipped. PSR_state 5 that is PSR exit then
+		 * Hardware is responsible to transition back to PSR_state 1
+		 * that is PSR inactive. Same state after
+		 * vlv_edp_psr_enable_source.
+		 */
+		val &= ~VLV_EDP_PSR_ACTIVE_ENTRY;
+		I915_WRITE(VLV_PSRCTL(pipe), val);
+
+		/* Send AUX wake up - Spec says after transitioning to PSR
+		 * active we have to send AUX wake up by writing 01h in DPCD
+		 * 600h of sink device.
+		 * XXX: This might slow down the transition, but without this
+		 * HW doesn't complete the transition to PSR_state 1 and we
+		 * never get the screen updated.
+		 */
+		drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
+				   DP_SET_POWER_D0);
 	}
 
+	dev_priv->psr.active = false;
 }
 
 /**
@@ -558,6 +618,17 @@ void intel_psr_flush(struct drm_device *dev,
 	    (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
 		intel_psr_exit(dev);
 
+	/*
+	 * On Valleyview and Cherryview we don't use hardware tracking so
+	 * sprite plane updates or cursor moves don't result in a PSR
+	 * invalidating. Which means we need to manually fake this in
+	 * software for all flushes, not just when we've seen a preceding
+	 * invalidation through frontbuffer rendering. */
+	if (!HAS_DDI(dev) &&
+	    ((frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)) ||
+	     (frontbuffer_bits & INTEL_FRONTBUFFER_CURSOR(pipe))))
+		intel_psr_exit(dev);
+
 	if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
 		schedule_delayed_work(&dev_priv->psr.work,
 				      msecs_to_jiffies(100));
-- 
1.9.3

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Re: [PATCH] drm/i915: VLV/CHV PSR Software timer mode

[R, Durgadoss]

>-----Original Message-----
>From: Vivi, Rodrigo
>Sent: Wednesday, November 19, 2014 9:08 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Vivi, Rodrigo; R, Durgadoss
>Subject: [PATCH] drm/i915: VLV/CHV PSR Software timer mode
>
>This patch introduces exit/activate functions for PSR
>on VLV+. Since on VLV+ HW cannot track frame updates and force PSR
>exit let's use fully SW tracking available.
>
>v2: Rebase over intel_psr.c;
>    Remove Single Frame update transitioning from state 3 to 5 directly;
>    Fake a software invalidation for sprites and cursor so we don't miss
>    any screen update;
>
>v3: As pointed out by Durgadoss msecs_to_jiffies used on wait_for only uses int,
>    so let's use 1 instead. Althought the 1/4 of this is needed for the
>    transition let's use 1 for simplicity;
>    Also fix comments as suggested by Durgadoss
>
>Cc: Durgadoss R <durgadoss.r@intel.com>
>Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

1 ms for transition looks fine..

Reviewed-by: Durgadoss R <durgadoss.r@intel.com>

Thanks,
Durga

>---
> drivers/gpu/drm/i915/intel_psr.c | 97 ++++++++++++++++++++++++++++++++++------
> 1 file changed, 84 insertions(+), 13 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
>index 30f341a..dd0e6e0 100644
>--- a/drivers/gpu/drm/i915/intel_psr.c
>+++ b/drivers/gpu/drm/i915/intel_psr.c
>@@ -195,6 +195,23 @@ static void vlv_psr_enable_source(struct intel_dp *intel_dp)
> 		   VLV_EDP_PSR_ENABLE);
> }
>
>+static void vlv_psr_activate(struct intel_dp *intel_dp)
>+{
>+	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>+	struct drm_device *dev = dig_port->base.base.dev;
>+	struct drm_i915_private *dev_priv = dev->dev_private;
>+	struct drm_crtc *crtc = dig_port->base.base.crtc;
>+	enum pipe pipe = to_intel_crtc(crtc)->pipe;
>+
>+	/* Let's do the transition from PSR_state 1 to PSR_state 2
>+	 * that is PSR transition to active - static frame transmission.
>+	 * Then Hardware is responsible for the transition to PSR_state 3
>+	 * that is PSR active - no Remote Frame Buffer (RFB) update.
>+	 */
>+	I915_WRITE(VLV_PSRCTL(pipe), I915_READ(VLV_PSRCTL(pipe)) |
>+		   VLV_EDP_PSR_ACTIVE_ENTRY);
>+}
>+
> static void hsw_psr_enable_source(struct intel_dp *intel_dp)
> {
> 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>@@ -283,12 +300,16 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
> 	WARN_ON(dev_priv->psr.active);
> 	lockdep_assert_held(&dev_priv->psr.lock);
>
>-	/* Enable/Re-enable PSR on the host
>-	 * On HSW+ after we enable PSR on source it will activate it
>-	 * as soon as it match configure idle_frame count. So
>-	 * we just actually enable it here on activation time.
>-	 */
>-	hsw_psr_enable_source(intel_dp);
>+	/* Enable/Re-enable PSR on the host */
>+	if (HAS_DDI(dev))
>+		/* On HSW+ after we enable PSR on source it will activate it
>+		 * as soon as it match configure idle_frame count. So
>+		 * we just actually enable it here on activation time.
>+		 */
>+		hsw_psr_enable_source(intel_dp);
>+	else
>+		vlv_psr_activate(intel_dp);
>+
> 	dev_priv->psr.active = true;
> }
>
>@@ -436,18 +457,27 @@ static void intel_psr_work(struct work_struct *work)
> 	struct drm_i915_private *dev_priv =
> 		container_of(work, typeof(*dev_priv), psr.work.work);
> 	struct intel_dp *intel_dp = dev_priv->psr.enabled;
>+	struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
>+	enum pipe pipe = to_intel_crtc(crtc)->pipe;
>
> 	/* We have to make sure PSR is ready for re-enable
> 	 * otherwise it keeps disabled until next full enable/disable cycle.
> 	 * PSR might take some time to get fully disabled
> 	 * and be ready for re-enable.
> 	 */
>-	if (wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev_priv->dev)) &
>-		      EDP_PSR_STATUS_STATE_MASK) == 0, 50)) {
>-		DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
>-		return;
>+	if (HAS_DDI(dev_priv->dev)) {
>+		if (wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev_priv->dev)) &
>+			      EDP_PSR_STATUS_STATE_MASK) == 0, 50)) {
>+			DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
>+			return;
>+		}
>+	} else {
>+		if (wait_for((I915_READ(VLV_PSRSTAT(pipe)) &
>+			      VLV_EDP_PSR_IN_TRANS) == 0, 1)) {
>+			DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
>+			return;
>+		}
> 	}
>-
> 	mutex_lock(&dev_priv->psr.lock);
> 	intel_dp = dev_priv->psr.enabled;
>
>@@ -470,17 +500,47 @@ unlock:
> static void intel_psr_exit(struct drm_device *dev)
> {
> 	struct drm_i915_private *dev_priv = dev->dev_private;
>+	struct intel_dp *intel_dp = dev_priv->psr.enabled;
>+	struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
>+	enum pipe pipe = to_intel_crtc(crtc)->pipe;
>+	u32 val;
>
>-	if (dev_priv->psr.active) {
>-		u32 val = I915_READ(EDP_PSR_CTL(dev));
>+	if (!dev_priv->psr.active)
>+		return;
>+
>+	if (HAS_DDI(dev)) {
>+		val = I915_READ(EDP_PSR_CTL(dev));
>
> 		WARN_ON(!(val & EDP_PSR_ENABLE));
>
> 		I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
>
> 		dev_priv->psr.active = false;
>+	} else {
>+		val = I915_READ(VLV_PSRCTL(pipe));
>+
>+		/* Here we do the transition from PSR_state 3 to PSR_state 5
>+		 * directly once PSR State 4 that is active with single frame
>+		 * update can be skipped. PSR_state 5 that is PSR exit then
>+		 * Hardware is responsible to transition back to PSR_state 1
>+		 * that is PSR inactive. Same state after
>+		 * vlv_edp_psr_enable_source.
>+		 */
>+		val &= ~VLV_EDP_PSR_ACTIVE_ENTRY;
>+		I915_WRITE(VLV_PSRCTL(pipe), val);
>+
>+		/* Send AUX wake up - Spec says after transitioning to PSR
>+		 * active we have to send AUX wake up by writing 01h in DPCD
>+		 * 600h of sink device.
>+		 * XXX: This might slow down the transition, but without this
>+		 * HW doesn't complete the transition to PSR_state 1 and we
>+		 * never get the screen updated.
>+		 */
>+		drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
>+				   DP_SET_POWER_D0);
> 	}
>
>+	dev_priv->psr.active = false;
> }
>
> /**
>@@ -558,6 +618,17 @@ void intel_psr_flush(struct drm_device *dev,
> 	    (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
> 		intel_psr_exit(dev);
>
>+	/*
>+	 * On Valleyview and Cherryview we don't use hardware tracking so
>+	 * sprite plane updates or cursor moves don't result in a PSR
>+	 * invalidating. Which means we need to manually fake this in
>+	 * software for all flushes, not just when we've seen a preceding
>+	 * invalidation through frontbuffer rendering. */
>+	if (!HAS_DDI(dev) &&
>+	    ((frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)) ||
>+	     (frontbuffer_bits & INTEL_FRONTBUFFER_CURSOR(pipe))))
>+		intel_psr_exit(dev);
>+
> 	if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
> 		schedule_delayed_work(&dev_priv->psr.work,
> 				      msecs_to_jiffies(100));
>--
>1.9.3

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[PATCH 13/15] drm/i915: VLV/CHV PSR: Increase wait delay time before active PSR.

[Rodrigo Vivi]

Since active function on VLV immediately activate PSR let's give more
time for idleness.

v2: Rebase over intel_psr.c and fix typo.

Cc: Durgadoss R <durgadoss.r@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_psr.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index b2a4ee7..fe7b0f6 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -618,6 +618,11 @@ void intel_psr_flush(struct drm_device *dev,
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_crtc *crtc;
 	enum pipe pipe;
+	/* On HSW/BDW Hardware controls idle_frames to go to PSR entry state
+	 * However on VLV we go to PSR active state with psr work. So let's
+	 * wait more time and let the user experience smooth enough.
+	 */
+	int delay = msecs_to_jiffies(HAS_DDI(dev) ? 100 : 5000);
 
 	mutex_lock(&dev_priv->psr.lock);
 	if (!dev_priv->psr.enabled) {
@@ -651,7 +656,7 @@ void intel_psr_flush(struct drm_device *dev,
 
 	if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
 		schedule_delayed_work(&dev_priv->psr.work,
-				      msecs_to_jiffies(100));
+				      msecs_to_jiffies(delay));
 	mutex_unlock(&dev_priv->psr.lock);
 }
 
-- 
1.9.3

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Re: [PATCH 13/15] drm/i915: VLV/CHV PSR: Increase wait delay time before active PSR.

[R, Durgadoss]

>-----Original Message-----
>From: Vivi, Rodrigo
>Sent: Friday, November 14, 2014 10:23 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Vivi, Rodrigo; R, Durgadoss
>Subject: [PATCH 13/15] drm/i915: VLV/CHV PSR: Increase wait delay time before active PSR.
>
>Since active function on VLV immediately activate PSR let's give more
>time for idleness.
>
>v2: Rebase over intel_psr.c and fix typo.
>
>Cc: Durgadoss R <durgadoss.r@intel.com>
>Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>---
> drivers/gpu/drm/i915/intel_psr.c | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
>index b2a4ee7..fe7b0f6 100644
>--- a/drivers/gpu/drm/i915/intel_psr.c
>+++ b/drivers/gpu/drm/i915/intel_psr.c
>@@ -618,6 +618,11 @@ void intel_psr_flush(struct drm_device *dev,
> 	struct drm_i915_private *dev_priv = dev->dev_private;
> 	struct drm_crtc *crtc;
> 	enum pipe pipe;
>+	/* On HSW/BDW Hardware controls idle_frames to go to PSR entry state
>+	 * However on VLV we go to PSR active state with psr work. So let's

s/psr/PSR

Reviewed-by: Durgadoss R <durgadoss.r@intel.com>

Thanks,
Durga

>+	 * wait more time and let the user experience smooth enough.
>+	 */
>+	int delay = msecs_to_jiffies(HAS_DDI(dev) ? 100 : 5000);
>
> 	mutex_lock(&dev_priv->psr.lock);
> 	if (!dev_priv->psr.enabled) {
>@@ -651,7 +656,7 @@ void intel_psr_flush(struct drm_device *dev,
>
> 	if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
> 		schedule_delayed_work(&dev_priv->psr.work,
>-				      msecs_to_jiffies(100));
>+				      msecs_to_jiffies(delay));
> 	mutex_unlock(&dev_priv->psr.lock);
> }
>
>--
>1.9.3

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[PATCH] drm/i915: VLV/CHV PSR: Increase wait delay time before active PSR.

[Rodrigo Vivi]

Since active function on VLV immediately activate PSR let's give more
time for idleness.

v2: Rebase over intel_psr.c and fix typo.
v3: s/psr/PSR on comment (by Durgadoss)

Reviewed-by: Durgadoss R <durgadoss.r@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_psr.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index dd0e6e0..57bf6d4 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -597,6 +597,11 @@ void intel_psr_flush(struct drm_device *dev,
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_crtc *crtc;
 	enum pipe pipe;
+	/* On HSW/BDW Hardware controls idle_frames to go to PSR entry state
+	 * However on VLV we go to PSR active state with PSR work. So let's
+	 * wait more time and let the user experience smooth enough.
+	 */
+	int delay = msecs_to_jiffies(HAS_DDI(dev) ? 100 : 5000);
 
 	mutex_lock(&dev_priv->psr.lock);
 	if (!dev_priv->psr.enabled) {
@@ -631,7 +636,7 @@ void intel_psr_flush(struct drm_device *dev,
 
 	if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
 		schedule_delayed_work(&dev_priv->psr.work,
-				      msecs_to_jiffies(100));
+				      msecs_to_jiffies(delay));
 	mutex_unlock(&dev_priv->psr.lock);
 }
 
-- 
1.9.3

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Re: [PATCH] drm/i915: VLV/CHV PSR: Increase wait delay time before active PSR.

[Daniel Vetter]

On Wed, Nov 19, 2014 at 07:38:51AM -0800, Rodrigo Vivi wrote:
> Since active function on VLV immediately activate PSR let's give more
> time for idleness.
> 
> v2: Rebase over intel_psr.c and fix typo.
> v3: s/psr/PSR on comment (by Durgadoss)
> 
> Reviewed-by: Durgadoss R <durgadoss.r@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_psr.c | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index dd0e6e0..57bf6d4 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -597,6 +597,11 @@ void intel_psr_flush(struct drm_device *dev,
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct drm_crtc *crtc;
>  	enum pipe pipe;
> +	/* On HSW/BDW Hardware controls idle_frames to go to PSR entry state
> +	 * However on VLV we go to PSR active state with PSR work. So let's
> +	 * wait more time and let the user experience smooth enough.
> +	 */
> +	int delay = msecs_to_jiffies(HAS_DDI(dev) ? 100 : 5000);

I'd like to know how we arrived at this number? And the justification imo
doesn't make a lot of sense, whether it's hw or sw entering psr state
doesn't take a lot of cpu cycles. Two things:

- Should we compute this delay according to the minimal psr exit frames we
  already get from vbt and use for hsw/bdw?
- Do we need to adjust igt testcases to wait longer with this 5s delay?

I'll punt on this patch for now until this is resolved.
-Daniel

>  
>  	mutex_lock(&dev_priv->psr.lock);
>  	if (!dev_priv->psr.enabled) {
> @@ -631,7 +636,7 @@ void intel_psr_flush(struct drm_device *dev,
>  
>  	if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
>  		schedule_delayed_work(&dev_priv->psr.work,
> -				      msecs_to_jiffies(100));
> +				      msecs_to_jiffies(delay));
>  	mutex_unlock(&dev_priv->psr.lock);
>  }
>  
> -- 
> 1.9.3
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [PATCH] drm/i915: VLV/CHV PSR: Increase wait delay time before active PSR.

[Vivi, Rodrigo]

Yeah, I'm glad you skipped this one. It was something old I was just carrying for too long... 

Just tested on -nightly and everything is working fine. Even after suspend-resume! :)

Still said that I cannot use sink_crc when psr is enabled...

Thank you very much.

-----Original Message-----
From: Daniel Vetter [mailto:daniel.vetter@ffwll.ch] On Behalf Of Daniel Vetter
Sent: Friday, November 21, 2014 10:46 AM
To: Vivi, Rodrigo
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH] drm/i915: VLV/CHV PSR: Increase wait delay time before active PSR.

On Wed, Nov 19, 2014 at 07:38:51AM -0800, Rodrigo Vivi wrote:
> Since active function on VLV immediately activate PSR let's give more 
> time for idleness.
> 
> v2: Rebase over intel_psr.c and fix typo.
> v3: s/psr/PSR on comment (by Durgadoss)
> 
> Reviewed-by: Durgadoss R <durgadoss.r@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_psr.c | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_psr.c 
> b/drivers/gpu/drm/i915/intel_psr.c
> index dd0e6e0..57bf6d4 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -597,6 +597,11 @@ void intel_psr_flush(struct drm_device *dev,
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct drm_crtc *crtc;
>  	enum pipe pipe;
> +	/* On HSW/BDW Hardware controls idle_frames to go to PSR entry state
> +	 * However on VLV we go to PSR active state with PSR work. So let's
> +	 * wait more time and let the user experience smooth enough.
> +	 */
> +	int delay = msecs_to_jiffies(HAS_DDI(dev) ? 100 : 5000);

I'd like to know how we arrived at this number? And the justification imo doesn't make a lot of sense, whether it's hw or sw entering psr state doesn't take a lot of cpu cycles. Two things:

- Should we compute this delay according to the minimal psr exit frames we
  already get from vbt and use for hsw/bdw?
- Do we need to adjust igt testcases to wait longer with this 5s delay?

I'll punt on this patch for now until this is resolved.
-Daniel

>  
>  	mutex_lock(&dev_priv->psr.lock);
>  	if (!dev_priv->psr.enabled) {
> @@ -631,7 +636,7 @@ void intel_psr_flush(struct drm_device *dev,
>  
>  	if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
>  		schedule_delayed_work(&dev_priv->psr.work,
> -				      msecs_to_jiffies(100));
> +				      msecs_to_jiffies(delay));
>  	mutex_unlock(&dev_priv->psr.lock);
>  }
>  
> --
> 1.9.3
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

--
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+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [PATCH] drm/i915: VLV/CHV PSR: Increase wait delay time before active PSR.

[Daniel Vetter]

On Fri, Nov 21, 2014 at 10:00:53PM +0000, Vivi, Rodrigo wrote:
> Yeah, I'm glad you skipped this one. It was something old I was just carrying for too long... 
> 
> Just tested on -nightly and everything is working fine. Even after suspend-resume! :)
> 
> Still said that I cannot use sink_crc when psr is enabled...

Don't we still need a patch to obey the minimal psr/non-psr times as
specified in the vbt like on hsw/bdw? Or is this a case where the vbt
doesn't quite mean the same thing on vlv/chv than on big core platforms?

Please chase the vbt/vbios/bangalore folks a bit to make sure we don't
have a gap here.

Thanks, Daniel
> 
> Thank you very much.
> 
> -----Original Message-----
> From: Daniel Vetter [mailto:daniel.vetter@ffwll.ch] On Behalf Of Daniel Vetter
> Sent: Friday, November 21, 2014 10:46 AM
> To: Vivi, Rodrigo
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915: VLV/CHV PSR: Increase wait delay time before active PSR.
> 
> On Wed, Nov 19, 2014 at 07:38:51AM -0800, Rodrigo Vivi wrote:
> > Since active function on VLV immediately activate PSR let's give more 
> > time for idleness.
> > 
> > v2: Rebase over intel_psr.c and fix typo.
> > v3: s/psr/PSR on comment (by Durgadoss)
> > 
> > Reviewed-by: Durgadoss R <durgadoss.r@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_psr.c | 7 ++++++-
> >  1 file changed, 6 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_psr.c 
> > b/drivers/gpu/drm/i915/intel_psr.c
> > index dd0e6e0..57bf6d4 100644
> > --- a/drivers/gpu/drm/i915/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > @@ -597,6 +597,11 @@ void intel_psr_flush(struct drm_device *dev,
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> >  	struct drm_crtc *crtc;
> >  	enum pipe pipe;
> > +	/* On HSW/BDW Hardware controls idle_frames to go to PSR entry state
> > +	 * However on VLV we go to PSR active state with PSR work. So let's
> > +	 * wait more time and let the user experience smooth enough.
> > +	 */
> > +	int delay = msecs_to_jiffies(HAS_DDI(dev) ? 100 : 5000);
> 
> I'd like to know how we arrived at this number? And the justification imo doesn't make a lot of sense, whether it's hw or sw entering psr state doesn't take a lot of cpu cycles. Two things:
> 
> - Should we compute this delay according to the minimal psr exit frames we
>   already get from vbt and use for hsw/bdw?
> - Do we need to adjust igt testcases to wait longer with this 5s delay?
> 
> I'll punt on this patch for now until this is resolved.
> -Daniel
> 
> >  
> >  	mutex_lock(&dev_priv->psr.lock);
> >  	if (!dev_priv->psr.enabled) {
> > @@ -631,7 +636,7 @@ void intel_psr_flush(struct drm_device *dev,
> >  
> >  	if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
> >  		schedule_delayed_work(&dev_priv->psr.work,
> > -				      msecs_to_jiffies(100));
> > +				      msecs_to_jiffies(delay));
> >  	mutex_unlock(&dev_priv->psr.lock);
> >  }
> >  
> > --
> > 1.9.3
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch

-- 
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Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [PATCH] drm/i915: VLV/CHV PSR: Increase wait delay time

[shuang.he]

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                                  367/367              367/367
ILK              +2-3              373/375              372/375
SNB                                  450/450              450/450
IVB                 -3              503/503              500/503
BYT                                  289/289              289/289
HSW                 -3              568/568              565/568
BDW                                  417/417              417/417
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
ILK  igt_kms_flip_flip-vs-panning      NSPT(1, M26)      PASS(2, M26)
ILK  igt_kms_flip_nonexisting-fb      DMESG_WARN(1, M26)      PASS(2, M26)
ILK  igt_kms_flip_wf_vblank-ts-check      PASS(1, M26)      DMESG_WARN(1, M26)PASS(1, M26)
ILK  igt_kms_flip_wf_vblank-ts-check-interruptible      PASS(1, M26)      DMESG_WARN(1, M26)PASS(1, M26)
ILK  igt_kms_pipe_crc_basic_bad-source      PASS(1, M26)      DMESG_WARN(1, M26)PASS(1, M26)
IVB  igt_gem_bad_reloc_negative-reloc      PASS(1, M21)      NSPT(2, M21)
IVB  igt_gem_bad_reloc_negative-reloc-lut      PASS(1, M21)      NSPT(1, M21)PASS(1, M21)
IVB  igt_kms_cursor_crc_cursor-128x128-sliding      PASS(1, M21)      DMESG_WARN(1, M21)PASS(1, M21)
HSW  igt_gem_bad_reloc_negative-reloc-lut      PASS(1, M19)      NSPT(2, M20)
HSW  igt_kms_rotation_crc_primary-rotation      PASS(1, M19)      DMESG_WARN(1, M20)PASS(1, M20)
HSW  igt_pm_rc6_residency_rc6-accuracy      PASS(1, M19)      FAIL(1, M20)PASS(1, M20)
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[PATCH 14/15] drm/i915: VLV/CHV PSR debugfs.

[Rodrigo Vivi]

Add debugfs support for Valleyview and Cherryview considering that
we have PSR per pipe and  we don't have any kind of
performance counter as we have on other platforms that support PSR.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 34 +++++++++++++++++++++++++++++-----
 1 file changed, 29 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 319da61..d9b27f8 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2126,6 +2126,8 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
 	struct drm_device *dev = node->minor->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 psrperf = 0;
+	u32 stat[3];
+	enum pipe pipe;
 	bool enabled = false;
 
 	intel_runtime_pm_get(dev_priv);
@@ -2140,14 +2142,36 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
 	seq_printf(m, "Re-enable work scheduled: %s\n",
 		   yesno(work_busy(&dev_priv->psr.work.work)));
 
-	enabled = HAS_PSR(dev) &&
-		I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
-	seq_printf(m, "HW Enabled & Active bit: %s\n", yesno(enabled));
+	if (HAS_PSR(dev)) {
+		if (HAS_DDI(dev))
+			enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
+		else {
+			for_each_pipe(dev_priv, pipe) {
+				stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
+					VLV_EDP_PSR_CURR_STATE_MASK;
+				if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
+				    (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
+					enabled = true;
+			}
+		}
+	}
+	seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
 
-	if (HAS_PSR(dev))
+	if (!HAS_DDI(dev))
+		for_each_pipe(dev_priv, pipe) {
+			if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
+			    (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
+				seq_printf(m, " pipe %c", pipe_name(pipe));
+		}
+	seq_puts(m, "\n");
+
+	/* CHV PSR has no kind of performance counter */
+	if (HAS_PSR(dev) && HAS_DDI(dev)) {
 		psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
 			EDP_PSR_PERF_CNT_MASK;
-	seq_printf(m, "Performance_Counter: %u\n", psrperf);
+
+		seq_printf(m, "Performance_Counter: %u\n", psrperf);
+	}
 	mutex_unlock(&dev_priv->psr.lock);
 
 	intel_runtime_pm_put(dev_priv);
-- 
1.9.3

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Re: [PATCH 14/15] drm/i915: VLV/CHV PSR debugfs.

[R, Durgadoss]

>-----Original Message-----
>From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of Rodrigo Vivi
>Sent: Friday, November 14, 2014 10:23 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Vivi, Rodrigo
>Subject: [Intel-gfx] [PATCH 14/15] drm/i915: VLV/CHV PSR debugfs.
>
>Add debugfs support for Valleyview and Cherryview considering that
>we have PSR per pipe and  we don't have any kind of
>performance counter as we have on other platforms that support PSR.
>
>Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>---
> drivers/gpu/drm/i915/i915_debugfs.c | 34 +++++++++++++++++++++++++++++-----
> 1 file changed, 29 insertions(+), 5 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
>index 319da61..d9b27f8 100644
>--- a/drivers/gpu/drm/i915/i915_debugfs.c
>+++ b/drivers/gpu/drm/i915/i915_debugfs.c
>@@ -2126,6 +2126,8 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
> 	struct drm_device *dev = node->minor->dev;
> 	struct drm_i915_private *dev_priv = dev->dev_private;
> 	u32 psrperf = 0;
>+	u32 stat[3];
>+	enum pipe pipe;
> 	bool enabled = false;
>
> 	intel_runtime_pm_get(dev_priv);
>@@ -2140,14 +2142,36 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
> 	seq_printf(m, "Re-enable work scheduled: %s\n",
> 		   yesno(work_busy(&dev_priv->psr.work.work)));
>
>-	enabled = HAS_PSR(dev) &&
>-		I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
>-	seq_printf(m, "HW Enabled & Active bit: %s\n", yesno(enabled));
>+	if (HAS_PSR(dev)) {
>+		if (HAS_DDI(dev))
>+			enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
>+		else {
>+			for_each_pipe(dev_priv, pipe) {
>+				stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
>+					VLV_EDP_PSR_CURR_STATE_MASK;
>+				if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
>+				    (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
>+					enabled = true;
>+			}
>+		}
>+	}

Reviewed-by: Durgadoss R <durgadoss.r@intel.com>

Thanks,
Durga

>+	seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
>
>-	if (HAS_PSR(dev))
>+	if (!HAS_DDI(dev))
>+		for_each_pipe(dev_priv, pipe) {
>+			if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
>+			    (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
>+				seq_printf(m, " pipe %c", pipe_name(pipe));
>+		}
>+	seq_puts(m, "\n");
>+
>+	/* CHV PSR has no kind of performance counter */
>+	if (HAS_PSR(dev) && HAS_DDI(dev)) {
> 		psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
> 			EDP_PSR_PERF_CNT_MASK;
>-	seq_printf(m, "Performance_Counter: %u\n", psrperf);
>+
>+		seq_printf(m, "Performance_Counter: %u\n", psrperf);
>+	}
> 	mutex_unlock(&dev_priv->psr.lock);
>
> 	intel_runtime_pm_put(dev_priv);
>--
>1.9.3
>
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[PATCH 15/15] drm/i915: Enable PSR for Baytrail and Braswell.

[Rodrigo Vivi]

This patch is the last in series of VLV/CHV PSR,
that finnaly enable psr by adding it to HAS_PSR
and calling the proper enable and disable
functions on the right places.

Although it is still disabled by default.

v2: Rebase over intel_psr and merge Durgadoss's fixes.

Cc: Durgadoss R <durgadoss.r@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 3 ++-
 drivers/gpu/drm/i915/intel_dp.c | 4 ++++
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 573f084..4020653 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2267,7 +2267,8 @@ struct drm_i915_cmd_table {
 
 #define HAS_DDI(dev)		(INTEL_INFO(dev)->has_ddi)
 #define HAS_FPGA_DBG_UNCLAIMED(dev)	(INTEL_INFO(dev)->has_fpga_dbg)
-#define HAS_PSR(dev)		(IS_HASWELL(dev) || IS_BROADWELL(dev))
+#define HAS_PSR(dev)		(IS_HASWELL(dev) || IS_BROADWELL(dev) || \
+				 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 #define HAS_RUNTIME_PM(dev)	(IS_GEN6(dev) || IS_HASWELL(dev) || \
 				 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev))
 #define HAS_RC6(dev)		(INTEL_INFO(dev)->gen >= 6)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 98f7ecd..d53a0c9 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2075,6 +2075,9 @@ static void intel_disable_dp(struct intel_encoder *encoder)
 	if (crtc->config.has_audio)
 		intel_audio_codec_disable(encoder);
 
+	if (HAS_PSR(dev) && !HAS_DDI(dev))
+		intel_psr_disable(intel_dp);
+
 	/* Make sure the panel is off before trying to change the mode. But also
 	 * ensure that we have vdd while we switch off the panel. */
 	intel_edp_panel_vdd_on(intel_dp);
@@ -2299,6 +2302,7 @@ static void vlv_enable_dp(struct intel_encoder *encoder)
 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 
 	intel_edp_backlight_on(intel_dp);
+	intel_psr_enable(intel_dp);
 }
 
 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
-- 
1.9.3

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Re: [PATCH 15/15] drm/i915: Enable PSR for Baytrail and

[shuang.he]

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
-------------------------------------Summary-------------------------------------
Platform: baseline_drm_intel_nightly_pass_rate->patch_applied_pass_rate
BYT: pass/total=290/291->290/291
PNV: pass/total=352/356->356/356
ILK: pass/total=371/372->364/372
IVB: pass/total=545/546->544/546
SNB: pass/total=424/425->424/425
HSW: pass/total=579/579->579/579
BDW: pass/total=434/435->434/435
-------------------------------------Detailed-------------------------------------
test_platform: test_suite, test_case, result_with_drm_intel_nightly(count, machine_id...)...->result_with_patch_applied(count, machine_id)...
PNV: Intel_gpu_tools, igt_gen3_mixed_blits, DMESG_WARN(1, M23) -> PASS(4, M25)
PNV: Intel_gpu_tools, igt_gen3_render_mixed_blits, CRASH(1, M23) -> PASS(1, M25)
PNV: Intel_gpu_tools, igt_gen3_render_tiledx_blits, CRASH(1, M23) -> PASS(1, M25)
PNV: Intel_gpu_tools, igt_gen3_render_tiledy_blits, CRASH(1, M23) -> PASS(1, M25)
ILK: Intel_gpu_tools, igt_kms_flip_blocking-wf_vblank, PASS(4, M37M26) -> DMESG_WARN(2, M26)PASS(2, M26)
ILK: Intel_gpu_tools, igt_kms_flip_flip-vs-modeset-vs-hang-interruptible, PASS(7, M37M26) -> NSPT(1, M26)PASS(3, M26)
ILK: Intel_gpu_tools, igt_kms_flip_flip-vs-rmfb-interruptible, PASS(4, M37M26) -> DMESG_WARN(2, M26)PASS(2, M26)
ILK: Intel_gpu_tools, igt_kms_flip_flip-vs-wf_vblank-interruptible, DMESG_WARN(1, M26)PASS(6, M37M26) -> DMESG_WARN(1, M26)PASS(3, M26)
ILK: Intel_gpu_tools, igt_kms_flip_plain-flip, PASS(7, M37M26) -> DMESG_WARN(1, M26)PASS(3, M26)
ILK: Intel_gpu_tools, igt_kms_flip_plain-flip-fb-recreate-interruptible, PASS(4, M37M26) -> DMESG_WARN(2, M26)PASS(2, M26)
ILK: Intel_gpu_tools, igt_kms_render_direct-render, PASS(4, M37M26) -> DMESG_WARN(1, M26)PASS(3, M26)
ILK: Intel_gpu_tools, igt_kms_setmode_invalid-clone-single-crtc, DMESG_FAIL(2, M26)TIMEOUT(2, M37M26) -> FAIL(4, M26)
IVB: Intel_gpu_tools, igt_kms_pipe_crc_basic_hang-read-crc-pipe-C, PASS(4, M4M34) -> TIMEOUT(1, M34)PASS(3, M34)
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Re: [PATCH 15/15] drm/i915: Enable PSR for Baytrail and Braswell.

[Daniel Vetter]

On Fri, Nov 14, 2014 at 08:52:41AM -0800, Rodrigo Vivi wrote:
> This patch is the last in series of VLV/CHV PSR,
> that finnaly enable psr by adding it to HAS_PSR
> and calling the proper enable and disable
> functions on the right places.
> 
> Although it is still disabled by default.
> 
> v2: Rebase over intel_psr and merge Durgadoss's fixes.
> 
> Cc: Durgadoss R <durgadoss.r@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

where's the patch to enable PSR by default again? Also I've heard noises
that the sink crc stuff is busted :( And we still have the tasklist to fix
up the functional igt testcases.

I don't want to block merging this, but we need a clear task list of
what's left to do and full commitment of the necessary engineer-time to
actually make it happen. PSR with the frontbuffer tracking code is
invasive and will simply keep on bitrotting if we don't enable it (atomic
modeset already almost broke it completely by accident), which would
really be sad given all the time we've invested. Please chat with
Paul/Gavin to make sure this is tracked.

I don't want to carry essentially dead code around - the illusion that it
will get magically rebased and keep working is really just that.

Cheers, Daniel
-- 
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Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [PATCH 15/15] drm/i915: Enable PSR for Baytrail and Braswell.

[Rodrigo Vivi]

On Mon, Nov 17, 2014 at 10:18 AM, Daniel Vetter <daniel@ffwll.ch> wrote:
> On Fri, Nov 14, 2014 at 08:52:41AM -0800, Rodrigo Vivi wrote:
>> This patch is the last in series of VLV/CHV PSR,
>> that finnaly enable psr by adding it to HAS_PSR
>> and calling the proper enable and disable
>> functions on the right places.
>>
>> Although it is still disabled by default.
>>
>> v2: Rebase over intel_psr and merge Durgadoss's fixes.
>>
>> Cc: Durgadoss R <durgadoss.r@intel.com>
>> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> where's the patch to enable PSR by default again?

I'm trying to be extremely careful with this. I'm not enabling it by
default while I'm not 100% sure
I'm not breaking things hard for end users again.

> Also I've heard noises
> that the sink crc stuff is busted :( And we still have the tasklist to fix
> up the functional igt testcases.

Yes. In VLV/CHV the sink CRC is not working at all. This is one of the
reasons I'm not trying to
enable it by default again.

>
> I don't want to block merging this, but we need a clear task list of
> what's left to do and full commitment of the necessary engineer-time to
> actually make it happen. PSR with the frontbuffer tracking code is
> invasive and will simply keep on bitrotting if we don't enable it (atomic
> modeset already almost broke it completely by accident), which would
> really be sad given all the time we've invested. Please chat with
> Paul/Gavin to make sure this is tracked.

Sure. I'm not just trowing and abandoning it. I'll continue investing
time to get it properly to get enabled by default.
I have some Jira tasks for that and we can chat more later.

> I don't want to carry essentially dead code around - the illusion that it
> will get magically rebased and keep working is really just that.

I don't believe this is deadcode at all. Every progress is better than
none. This is why parameters exist.
We are just protecting all kind of end users but still giving the
choice to try some power savings.

>
> Cheers, Daniel
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
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Re: [PATCH 15/15] drm/i915: Enable PSR for Baytrail and Braswell.

[Daniel Vetter]

On Mon, Nov 17, 2014 at 10:30:58AM -0800, Rodrigo Vivi wrote:
> On Mon, Nov 17, 2014 at 10:18 AM, Daniel Vetter <daniel@ffwll.ch> wrote:
> > On Fri, Nov 14, 2014 at 08:52:41AM -0800, Rodrigo Vivi wrote:
> >> This patch is the last in series of VLV/CHV PSR,
> >> that finnaly enable psr by adding it to HAS_PSR
> >> and calling the proper enable and disable
> >> functions on the right places.
> >>
> >> Although it is still disabled by default.
> >>
> >> v2: Rebase over intel_psr and merge Durgadoss's fixes.
> >>
> >> Cc: Durgadoss R <durgadoss.r@intel.com>
> >> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> >
> > where's the patch to enable PSR by default again?
> 
> I'm trying to be extremely careful with this. I'm not enabling it by
> default while I'm not 100% sure
> I'm not breaking things hard for end users again.

The 3.19 window is pretty much gone by now, so we can be lenient with
enabling.

> > Also I've heard noises
> > that the sink crc stuff is busted :( And we still have the tasklist to fix
> > up the functional igt testcases.
> 
> Yes. In VLV/CHV the sink CRC is not working at all. This is one of the
> reasons I'm not trying to
> enable it by default again.

Bummer :( Have you tried switching panels (if you have an sdv with the
panel separate ofc and not a form-factor). Also do things still work on
hsw/bdw? If so that's really strange since this shouldn't depend in any
way on the source platform, it's "just" dp aux.

And if vlv/chv somehow block dp aux when psr is active then:
- We need a testcase for this (reading edid while psr is active should do
  that).
- We need to throw a synchronous psr exit into the dp aux transfer
  function on vlv/chv.

If it's something else we should track this down, too.

> > I don't want to block merging this, but we need a clear task list of
> > what's left to do and full commitment of the necessary engineer-time to
> > actually make it happen. PSR with the frontbuffer tracking code is
> > invasive and will simply keep on bitrotting if we don't enable it (atomic
> > modeset already almost broke it completely by accident), which would
> > really be sad given all the time we've invested. Please chat with
> > Paul/Gavin to make sure this is tracked.
> 
> Sure. I'm not just trowing and abandoning it. I'll continue investing
> time to get it properly to get enabled by default.
> I have some Jira tasks for that and we can chat more later.
> 
> > I don't want to carry essentially dead code around - the illusion that it
> > will get magically rebased and keep working is really just that.
> 
> I don't believe this is deadcode at all. Every progress is better than
> none. This is why parameters exist.
> We are just protecting all kind of end users but still giving the
> choice to try some power savings.

The problem is that if we don't enable this by default it bitrots really
quickly, and we'll end up spending more time keeping it alive than the
final push to make it work would cost. I've thought that for hsw/bdw we've
had patches to make it work well? But somehow they never landed, or we've
forgotten to throw the switch to "enabled by default" again ...

Cheers, Daniel
-- 
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Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [PATCH 15/15] drm/i915: Enable PSR for Baytrail and Braswell.

[Rodrigo Vivi]

On Mon, Nov 17, 2014 at 10:51 AM, Daniel Vetter <daniel@ffwll.ch> wrote:
> On Mon, Nov 17, 2014 at 10:30:58AM -0800, Rodrigo Vivi wrote:
>> On Mon, Nov 17, 2014 at 10:18 AM, Daniel Vetter <daniel@ffwll.ch> wrote:
>> > On Fri, Nov 14, 2014 at 08:52:41AM -0800, Rodrigo Vivi wrote:
>> >> This patch is the last in series of VLV/CHV PSR,
>> >> that finnaly enable psr by adding it to HAS_PSR
>> >> and calling the proper enable and disable
>> >> functions on the right places.
>> >>
>> >> Although it is still disabled by default.
>> >>
>> >> v2: Rebase over intel_psr and merge Durgadoss's fixes.
>> >>
>> >> Cc: Durgadoss R <durgadoss.r@intel.com>
>> >> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> >
>> > where's the patch to enable PSR by default again?
>>
>> I'm trying to be extremely careful with this. I'm not enabling it by
>> default while I'm not 100% sure
>> I'm not breaking things hard for end users again.
>
> The 3.19 window is pretty much gone by now, so we can be lenient with
> enabling.
>
>> > Also I've heard noises
>> > that the sink crc stuff is busted :( And we still have the tasklist to fix
>> > up the functional igt testcases.
>>
>> Yes. In VLV/CHV the sink CRC is not working at all. This is one of the
>> reasons I'm not trying to
>> enable it by default again.
>
> Bummer :( Have you tried switching panels (if you have an sdv with the
> panel separate ofc and not a form-factor).

yes

> Also do things still work on
> hsw/bdw?

Yes, on hsw sdp ultrabook passing 100% of time.
On BDW acrilic sdp passing after I removed that VBT.skip aux on exit.


> If so that's really strange since this shouldn't depend in any
> way on the source platform, it's "just" dp aux.

indeed.

>
> And if vlv/chv somehow block dp aux when psr is active then:
> - We need a testcase for this (reading edid while psr is active should do
>   that).
> - We need to throw a synchronous psr exit into the dp aux transfer
>   function on vlv/chv.

good ideas, I;ll check that
Thanks.

>
> If it's something else we should track this down, too.

I'll continue the investigation.

>
>> > I don't want to block merging this, but we need a clear task list of
>> > what's left to do and full commitment of the necessary engineer-time to
>> > actually make it happen. PSR with the frontbuffer tracking code is
>> > invasive and will simply keep on bitrotting if we don't enable it (atomic
>> > modeset already almost broke it completely by accident), which would
>> > really be sad given all the time we've invested. Please chat with
>> > Paul/Gavin to make sure this is tracked.
>>
>> Sure. I'm not just trowing and abandoning it. I'll continue investing
>> time to get it properly to get enabled by default.
>> I have some Jira tasks for that and we can chat more later.
>>
>> > I don't want to carry essentially dead code around - the illusion that it
>> > will get magically rebased and keep working is really just that.
>>
>> I don't believe this is deadcode at all. Every progress is better than
>> none. This is why parameters exist.
>> We are just protecting all kind of end users but still giving the
>> choice to try some power savings.
>
> The problem is that if we don't enable this by default it bitrots really
> quickly, and we'll end up spending more time keeping it alive than the
> final push to make it work would cost. I've thought that for hsw/bdw we've
> had patches to make it work well? But somehow they never landed, or we've
> forgotten to throw the switch to "enabled by default" again ...

I'll do my best to speed up this work and get this safelly enabled by
default soon.

But with your point in mind I got worried about FBC. One of my tasks
that should be easily here was to put FBC on SKL on the same stage
that we have currently on previous platforms. Should I just skip that
while we don't really have FBC enabled by default?

>
> Cheers, Daniel
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
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Re: [PATCH 15/15] drm/i915: Enable PSR for Baytrail and Braswell.

[Daniel Vetter]

On Mon, Nov 17, 2014 at 11:12:30AM -0800, Rodrigo Vivi wrote:
> But with your point in mind I got worried about FBC. One of my tasks
> that should be easily here was to put FBC on SKL on the same stage
> that we have currently on previous platforms. Should I just skip that
> while we don't really have FBC enabled by default?

Yeah I think we should try to make a plan to get fbc into shape for
enabling-by-default first. Ville has done the patches a while ago to
mostly get there, but that work needs to be rebased on top of the
frontbuffer tracking (just duplicates infrastructure otherwise). I think
Paulo wanted to look into that, but I'm not sure whether he has time.
-Daniel
-- 
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Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [PATCH 15/15] drm/i915: Enable PSR for Baytrail and Braswell.

[Rodrigo Vivi]

Daniel, I think this is the only one of this series with pending
reviewed-by right?

Durga or Paulo, could you please help me on this?

Thank you,
Rodrigo.

On Fri, Nov 14, 2014 at 8:52 AM, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> This patch is the last in series of VLV/CHV PSR,
> that finnaly enable psr by adding it to HAS_PSR
> and calling the proper enable and disable
> functions on the right places.
>
> Although it is still disabled by default.
>
> v2: Rebase over intel_psr and merge Durgadoss's fixes.
>
> Cc: Durgadoss R <durgadoss.r@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h | 3 ++-
>  drivers/gpu/drm/i915/intel_dp.c | 4 ++++
>  2 files changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 573f084..4020653 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2267,7 +2267,8 @@ struct drm_i915_cmd_table {
>
>  #define HAS_DDI(dev)           (INTEL_INFO(dev)->has_ddi)
>  #define HAS_FPGA_DBG_UNCLAIMED(dev)    (INTEL_INFO(dev)->has_fpga_dbg)
> -#define HAS_PSR(dev)           (IS_HASWELL(dev) || IS_BROADWELL(dev))
> +#define HAS_PSR(dev)           (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
> +                                IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>  #define HAS_RUNTIME_PM(dev)    (IS_GEN6(dev) || IS_HASWELL(dev) || \
>                                  IS_BROADWELL(dev) || IS_VALLEYVIEW(dev))
>  #define HAS_RC6(dev)           (INTEL_INFO(dev)->gen >= 6)
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 98f7ecd..d53a0c9 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2075,6 +2075,9 @@ static void intel_disable_dp(struct intel_encoder *encoder)
>         if (crtc->config.has_audio)
>                 intel_audio_codec_disable(encoder);
>
> +       if (HAS_PSR(dev) && !HAS_DDI(dev))
> +               intel_psr_disable(intel_dp);
> +
>         /* Make sure the panel is off before trying to change the mode. But also
>          * ensure that we have vdd while we switch off the panel. */
>         intel_edp_panel_vdd_on(intel_dp);
> @@ -2299,6 +2302,7 @@ static void vlv_enable_dp(struct intel_encoder *encoder)
>         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
>
>         intel_edp_backlight_on(intel_dp);
> +       intel_psr_enable(intel_dp);
>  }
>
>  static void g4x_pre_enable_dp(struct intel_encoder *encoder)
> --
> 1.9.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
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Blog: http://blog.vivi.eng.br
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Re: [PATCH 15/15] drm/i915: Enable PSR for Baytrail and Braswell.

[R, Durgadoss]

>-----Original Message-----
>From: Rodrigo Vivi [mailto:rodrigo.vivi@gmail.com]
>Sent: Thursday, November 20, 2014 10:55 PM
>To: Vivi, Rodrigo; R, Durgadoss; Zanoni, Paulo R; Daniel Vetter
>Cc: intel-gfx
>Subject: Re: [Intel-gfx] [PATCH 15/15] drm/i915: Enable PSR for Baytrail and Braswell.
>
>Daniel, I think this is the only one of this series with pending
>reviewed-by right?
>
>Durga or Paulo, could you please help me on this?
>
>Thank you,
>Rodrigo.
>
>On Fri, Nov 14, 2014 at 8:52 AM, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
>> This patch is the last in series of VLV/CHV PSR,
>> that finnaly enable psr by adding it to HAS_PSR

Finally,

>> and calling the proper enable and disable
>> functions on the right places.
>>
>> Although it is still disabled by default.
>>
>> v2: Rebase over intel_psr and merge Durgadoss's fixes.
>>
>> Cc: Durgadoss R <durgadoss.r@intel.com>
>> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

With that,

Reviewed-by: Durgadoss R <durgadoss.r@intel.com>

Thanks,
Durga

>> ---
>>  drivers/gpu/drm/i915/i915_drv.h | 3 ++-
>>  drivers/gpu/drm/i915/intel_dp.c | 4 ++++
>>  2 files changed, 6 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index 573f084..4020653 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -2267,7 +2267,8 @@ struct drm_i915_cmd_table {
>>
>>  #define HAS_DDI(dev)           (INTEL_INFO(dev)->has_ddi)
>>  #define HAS_FPGA_DBG_UNCLAIMED(dev)    (INTEL_INFO(dev)->has_fpga_dbg)
>> -#define HAS_PSR(dev)           (IS_HASWELL(dev) || IS_BROADWELL(dev))
>> +#define HAS_PSR(dev)           (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
>> +                                IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>>  #define HAS_RUNTIME_PM(dev)    (IS_GEN6(dev) || IS_HASWELL(dev) || \
>>                                  IS_BROADWELL(dev) || IS_VALLEYVIEW(dev))
>>  #define HAS_RC6(dev)           (INTEL_INFO(dev)->gen >= 6)
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>> index 98f7ecd..d53a0c9 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -2075,6 +2075,9 @@ static void intel_disable_dp(struct intel_encoder *encoder)
>>         if (crtc->config.has_audio)
>>                 intel_audio_codec_disable(encoder);
>>
>> +       if (HAS_PSR(dev) && !HAS_DDI(dev))
>> +               intel_psr_disable(intel_dp);
>> +
>>         /* Make sure the panel is off before trying to change the mode. But also
>>          * ensure that we have vdd while we switch off the panel. */
>>         intel_edp_panel_vdd_on(intel_dp);
>> @@ -2299,6 +2302,7 @@ static void vlv_enable_dp(struct intel_encoder *encoder)
>>         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
>>
>>         intel_edp_backlight_on(intel_dp);
>> +       intel_psr_enable(intel_dp);
>>  }
>>
>>  static void g4x_pre_enable_dp(struct intel_encoder *encoder)
>> --
>> 1.9.3
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>
>
>--
>Rodrigo Vivi
>Blog: http://blog.vivi.eng.br
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[PATCH] drm/i915: Enable PSR for Baytrail and Braswell.

[Rodrigo Vivi]

This patch is the last in series of VLV/CHV PSR,
that finally enable PSR by adding it to HAS_PSR
and calling the proper enable and disable
functions on the right places.

Although it is still disabled by default.

v2: Rebase over intel_psr and merge Durgadoss's fixes.
v3: Fix typo.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Durgadoss R <durgadoss.r@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 3 ++-
 drivers/gpu/drm/i915/intel_dp.c | 4 ++++
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3ce820b..730abad 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2288,7 +2288,8 @@ struct drm_i915_cmd_table {
 
 #define HAS_DDI(dev)		(INTEL_INFO(dev)->has_ddi)
 #define HAS_FPGA_DBG_UNCLAIMED(dev)	(INTEL_INFO(dev)->has_fpga_dbg)
-#define HAS_PSR(dev)		(IS_HASWELL(dev) || IS_BROADWELL(dev))
+#define HAS_PSR(dev)		(IS_HASWELL(dev) || IS_BROADWELL(dev) || \
+				 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 #define HAS_RUNTIME_PM(dev)	(IS_GEN6(dev) || IS_HASWELL(dev) || \
 				 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev))
 #define HAS_RC6(dev)		(INTEL_INFO(dev)->gen >= 6)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 5be6f5e..70bb8d0 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2104,6 +2104,9 @@ static void intel_disable_dp(struct intel_encoder *encoder)
 	if (crtc->config.has_audio)
 		intel_audio_codec_disable(encoder);
 
+	if (HAS_PSR(dev) && !HAS_DDI(dev))
+		intel_psr_disable(intel_dp);
+
 	/* Make sure the panel is off before trying to change the mode. But also
 	 * ensure that we have vdd while we switch off the panel. */
 	intel_edp_panel_vdd_on(intel_dp);
@@ -2328,6 +2331,7 @@ static void vlv_enable_dp(struct intel_encoder *encoder)
 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 
 	intel_edp_backlight_on(intel_dp);
+	intel_psr_enable(intel_dp);
 }
 
 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
-- 
1.9.3

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Re: [PATCH] drm/i915: Enable PSR for Baytrail and Braswell.

[shuang.he]

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                 -1              367/367              366/367
ILK                                  373/375              373/375
SNB                 -1              450/450              449/450
IVB                 -1              502/503              501/503
BYT                                  289/289              289/289
HSW                 -3              567/567              564/567
BDW                                  417/417              417/417
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
PNV  igt_gen3_mixed_blits      PASS(2, M23)      CRASH(1, M23)
SNB  igt_kms_cursor_crc_cursor-size-change      PASS(1, M22)      DMESG_WARN(1, M22)PASS(1, M22)
IVB  igt_gem_bad_reloc_negative-reloc-lut      NSPT(3, M21M34M4)PASS(1, M21)      NSPT(2, M34)
HSW  igt_gem_bad_reloc_negative-reloc-lut      NSPT(3, M40M20)PASS(1, M20)      NSPT(1, M40)
HSW  igt_kms_rotation_crc_primary-rotation      PASS(4, M20M40)      DMESG_WARN(1, M40)
HSW  igt_pm_rc6_residency_rc6-accuracy      PASS(4, M20M40)      FAIL(1, M40)
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Re: [PATCH 01/15] drm/i915: Make dp aux pack/unpack public outside intel_dp.c

[Daniel Vetter]

On Fri, Nov 14, 2014 at 08:52:27AM -0800, Rodrigo Vivi wrote:
> No functional change. Just making it public for use outside intel_dp.c
> Allowing split psr functions.
> 
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Hm, some docbook for the library functions in intel_dp.c used by
intel_ddi.c and other parts of the driver might eventually come handy.
Volunteers welcome ;-)

Anyway thanks a lot for the docbook, I've merged the first three patches
from this series directly to avoid too much rebase pain.
-Daniel

> ---
>  drivers/gpu/drm/i915/intel_dp.c | 15 +++++++--------
>  1 file changed, 7 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 45b53ff..01834cd 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -227,8 +227,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
>  	return MODE_OK;
>  }
>  
> -static uint32_t
> -pack_aux(const uint8_t *src, int src_bytes)
> +uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
>  {
>  	int	i;
>  	uint32_t v = 0;
> @@ -240,8 +239,7 @@ pack_aux(const uint8_t *src, int src_bytes)
>  	return v;
>  }
>  
> -static void
> -unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
> +void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
>  {
>  	int i;
>  	if (dst_bytes > 4)
> @@ -863,7 +861,8 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
>  			/* Load the send data into the aux channel data registers */
>  			for (i = 0; i < send_bytes; i += 4)
>  				I915_WRITE(ch_data + i,
> -					   pack_aux(send + i, send_bytes - i));
> +					   intel_dp_pack_aux(send + i,
> +							     send_bytes - i));
>  
>  			/* Send the command and wait for it to complete */
>  			I915_WRITE(ch_ctl, send_ctl);
> @@ -917,8 +916,8 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
>  		recv_bytes = recv_size;
>  
>  	for (i = 0; i < recv_bytes; i += 4)
> -		unpack_aux(I915_READ(ch_data + i),
> -			   recv + i, recv_bytes - i);
> +		intel_dp_unpack_aux(I915_READ(ch_data + i),
> +				    recv + i, recv_bytes - i);
>  
>  	ret = recv_bytes;
>  out:
> @@ -2159,7 +2158,7 @@ static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
>  	/* Setup AUX registers */
>  	for (i = 0; i < sizeof(aux_msg); i += 4)
>  		I915_WRITE(EDP_PSR_AUX_DATA1(dev) + i,
> -			   pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
> +			   intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
>  
>  	I915_WRITE(EDP_PSR_AUX_CTL(dev),
>  		   DP_AUX_CH_CTL_TIME_OUT_400us |
> -- 
> 1.9.3
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 1/2] drm/i915: VLV/CHV PSR: Increase wait delay time before active PSR.

[Rodrigo Vivi]

Since active function on VLV immediately activate PSR let's give more
time for idleness. Different from core platforms where we have idle_frames
count.

Also kms_psr_sink_crc now is automated and always get this:

[drm:intel_enable_pipe] enabling pipe A
[drm:intel_edp_backlight_on]
[drm:intel_panel_enable_backlight] pipe
[drm:intel_panel_enable_backlight] pipe A
[drm:intel_panel_actually_set_backlight] set backlight PWM = 7812

PSR gets enabled somewhere here after backlight.

[drm:intel_get_hpd_pins] hotplug event received, stat 0x00000000, dig 0x0
[drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
[drm:vlv_update_wm] Setting FIFO watermarks - A: plane=391, cursor=63, sp

PSR gets flushed around here by intel_atomic_commit

[drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
[drm:vlv_update_wm] Setting FIFO watermarks - A: plane=391, cursor=63, sp
[drm:intel_set_memory_cxsr] memory self-refresh is enabled
[drm:intel_connector_check_state] [CONNECTOR:39:eDP-1]
[drm:check_encoder_state] [ENCODER:30:DAC-30]
[drm:check_encoder_state] [ENCODER:31:TMDS-31]
[drm:check_encoder_state] [ENCODER:36:TMDS-36]
[drm:check_encoder_state] [ENCODER:38:TMDS-38]
[drm:check_crtc_state] [CRTC:21]
[drm:check_crtc_state] [CRTC:26]
[drm:intel_psr_activate [i915]] *ERROR* PSR Active
[drm:intel_get_hpd_pins] hotplug event received, stat 0x00000000, dig 0x
[drm:intel_set_cpu_fifo_underrun_reporting [i915]] *ERROR* pipe A underrun
[drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe A FIFO
Underrun.

It is true that in a product we won't keep disabling and enabling planes so
frequently, but for safeness let's stay conservative.

It is also true that 500ms is an etternity. But PSR is anyway a power saving
feature for idle scenario. So if it is idle feature stays on and 500ms to get
it reanabled is not that insane.

v2: Rebase over intel_psr.c and fix typo.
v3: Revival: Manual tests indicated that this is needed. With a short delay
    there is a huge risk of getting blank screens when planes are being enabled.
v4: Revival 2 with reasonable delay. 1/2 sec instead of 5. VBT is 10 sec but
    actually time for link training what we aren't doing, but with only 100 sec
    in some cases kms_psr_sink_crc manual was showing blank screen,
    so let's use this for now. Also changed comment by a FIXME.
v5: Rebase after a long time, remove FIXME and update comment above.

Reviewed-by: Durgadoss R <durgadoss.r@intel.com> (v4)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_psr.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index acd8ec8..0f446b7 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -698,6 +698,7 @@ void intel_psr_flush(struct drm_device *dev,
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_crtc *crtc;
 	enum pipe pipe;
+	int delay = msecs_to_jiffies(HAS_DDI(dev) ? 100 : 500);
 
 	mutex_lock(&dev_priv->psr.lock);
 	if (!dev_priv->psr.enabled) {
@@ -733,7 +734,7 @@ void intel_psr_flush(struct drm_device *dev,
 
 	if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
 		schedule_delayed_work(&dev_priv->psr.work,
-				      msecs_to_jiffies(100));
+				      msecs_to_jiffies(delay));
 	mutex_unlock(&dev_priv->psr.lock);
 }
 
-- 
1.9.3

_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH] drm/i915: VLV/CHV PSR: Increase wait delay time before active PSR.

[Rodrigo Vivi]

Since active function on VLV immediately activate PSR let's give more
time for idleness. Different from core platforms where we have idle_frames
count.

Also kms_psr_sink_crc now is automated and always get this:

[drm:intel_enable_pipe] enabling pipe A
[drm:intel_edp_backlight_on]
[drm:intel_panel_enable_backlight] pipe
[drm:intel_panel_enable_backlight] pipe A
[drm:intel_panel_actually_set_backlight] set backlight PWM = 7812

PSR gets enabled somewhere here after backlight.

[drm:intel_get_hpd_pins] hotplug event received, stat 0x00000000, dig 0x0
[drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
[drm:vlv_update_wm] Setting FIFO watermarks - A: plane=391, cursor=63, sp

PSR gets flushed around here by intel_atomic_commit

[drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
[drm:vlv_update_wm] Setting FIFO watermarks - A: plane=391, cursor=63, sp
[drm:intel_set_memory_cxsr] memory self-refresh is enabled
[drm:intel_connector_check_state] [CONNECTOR:39:eDP-1]
[drm:check_encoder_state] [ENCODER:30:DAC-30]
[drm:check_encoder_state] [ENCODER:31:TMDS-31]
[drm:check_encoder_state] [ENCODER:36:TMDS-36]
[drm:check_encoder_state] [ENCODER:38:TMDS-38]
[drm:check_crtc_state] [CRTC:21]
[drm:check_crtc_state] [CRTC:26]
[drm:intel_psr_activate [i915]] *ERROR* PSR Active
[drm:intel_get_hpd_pins] hotplug event received, stat 0x00000000, dig 0x
[drm:intel_set_cpu_fifo_underrun_reporting [i915]] *ERROR* pipe A underrun
[drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe A FIFO
Underrun.

It is true that in a product we won't keep disabling and enabling planes so
frequently, but for safeness let's stay conservative.

It is also true that 500ms is an etternity. But PSR is anyway a power saving
feature for idle scenario. So if it is idle feature stays on and 500ms to get
it reanabled is not that insane.

v2: Rebase over intel_psr.c and fix typo.
v3: Revival: Manual tests indicated that this is needed. With a short delay
    there is a huge risk of getting blank screens when planes are being enabled.
v4: Revival 2 with reasonable delay. 1/2 sec instead of 5. VBT is 10 sec but
    actually time for link training what we aren't doing, but with only 100 sec
    in some cases kms_psr_sink_crc manual was showing blank screen,
    so let's use this for now. Also changed comment by a FIXME.
v5: Rebase after a long time, remove FIXME and update comment above.
v6: msecs_to_jiffies is already on delay. remove duplication.

Reviewed-by: Durgadoss R <durgadoss.r@intel.com> (v4)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_psr.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index acd8ec8..bec13b8 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -698,6 +698,7 @@ void intel_psr_flush(struct drm_device *dev,
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_crtc *crtc;
 	enum pipe pipe;
+	int delay = msecs_to_jiffies(HAS_DDI(dev) ? 100 : 500);
 
 	mutex_lock(&dev_priv->psr.lock);
 	if (!dev_priv->psr.enabled) {
@@ -732,8 +733,7 @@ void intel_psr_flush(struct drm_device *dev,
 	}
 
 	if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
-		schedule_delayed_work(&dev_priv->psr.work,
-				      msecs_to_jiffies(100));
+		schedule_delayed_work(&dev_priv->psr.work, delay);
 	mutex_unlock(&dev_priv->psr.lock);
 }
 
-- 
1.9.3

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH] drm/i915: VLV/CHV PSR: Increase wait delay time before active PSR.

[shuang.he]

Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6861
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
ILK                                  295/295              295/295
SNB                                  315/315              315/315
IVB                                  342/342              342/342
BYT                 -2              285/285              283/285
HSW                                  378/378              378/378
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
*BYT  igt@gem_partial_pwrite_pread@reads      PASS(1)      FAIL(1)
*BYT  igt@gem_partial_pwrite_pread@reads-display      PASS(1)      FAIL(1)
Note: You need to pay more attention to line start with '*'
_______________________________________________
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Re: [PATCH] drm/i915: VLV/CHV PSR: Increase wait delay time before active PSR.

[Daniel Vetter]

On Fri, Jul 24, 2015 at 04:42:27PM -0700, Rodrigo Vivi wrote:
> Since active function on VLV immediately activate PSR let's give more
> time for idleness. Different from core platforms where we have idle_frames
> count.
> 
> Also kms_psr_sink_crc now is automated and always get this:
> 
> [drm:intel_enable_pipe] enabling pipe A
> [drm:intel_edp_backlight_on]
> [drm:intel_panel_enable_backlight] pipe
> [drm:intel_panel_enable_backlight] pipe A
> [drm:intel_panel_actually_set_backlight] set backlight PWM = 7812
> 
> PSR gets enabled somewhere here after backlight.
> 
> [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000000, dig 0x0
> [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
> [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=391, cursor=63, sp
> 
> PSR gets flushed around here by intel_atomic_commit
> 
> [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
> [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=391, cursor=63, sp
> [drm:intel_set_memory_cxsr] memory self-refresh is enabled
> [drm:intel_connector_check_state] [CONNECTOR:39:eDP-1]
> [drm:check_encoder_state] [ENCODER:30:DAC-30]
> [drm:check_encoder_state] [ENCODER:31:TMDS-31]
> [drm:check_encoder_state] [ENCODER:36:TMDS-36]
> [drm:check_encoder_state] [ENCODER:38:TMDS-38]
> [drm:check_crtc_state] [CRTC:21]
> [drm:check_crtc_state] [CRTC:26]
> [drm:intel_psr_activate [i915]] *ERROR* PSR Active
> [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000000, dig 0x
> [drm:intel_set_cpu_fifo_underrun_reporting [i915]] *ERROR* pipe A underrun
> [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe A FIFO
> Underrun.
> 
> It is true that in a product we won't keep disabling and enabling planes so
> frequently, but for safeness let's stay conservative.
> 
> It is also true that 500ms is an etternity. But PSR is anyway a power saving
> feature for idle scenario. So if it is idle feature stays on and 500ms to get
> it reanabled is not that insane.
> 
> v2: Rebase over intel_psr.c and fix typo.
> v3: Revival: Manual tests indicated that this is needed. With a short delay
>     there is a huge risk of getting blank screens when planes are being enabled.
> v4: Revival 2 with reasonable delay. 1/2 sec instead of 5. VBT is 10 sec but
>     actually time for link training what we aren't doing, but with only 100 sec
>     in some cases kms_psr_sink_crc manual was showing blank screen,
>     so let's use this for now. Also changed comment by a FIXME.
> v5: Rebase after a long time, remove FIXME and update comment above.
> v6: msecs_to_jiffies is already on delay. remove duplication.
> 
> Reviewed-by: Durgadoss R <durgadoss.r@intel.com> (v4)
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_psr.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index acd8ec8..bec13b8 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -698,6 +698,7 @@ void intel_psr_flush(struct drm_device *dev,
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct drm_crtc *crtc;
>  	enum pipe pipe;
> +	int delay = msecs_to_jiffies(HAS_DDI(dev) ? 100 : 500);

Note that for a timeout you should be using our own
msecs_to_jiffies_timeout if it's for a timeout. This is needed since you
can't know when the next jiffy update happens and that might be right
away, therefore waiting for 10 jiffies might only be a wait for 9/HZ.
Anyway tiny nitpick.
-Daniel

>  
>  	mutex_lock(&dev_priv->psr.lock);
>  	if (!dev_priv->psr.enabled) {
> @@ -732,8 +733,7 @@ void intel_psr_flush(struct drm_device *dev,
>  	}
>  
>  	if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
> -		schedule_delayed_work(&dev_priv->psr.work,
> -				      msecs_to_jiffies(100));
> +		schedule_delayed_work(&dev_priv->psr.work, delay);
>  	mutex_unlock(&dev_priv->psr.lock);
>  }
>  
> -- 
> 1.9.3
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH] drm/i915: VLV/CHV PSR: Increase wait delay time before active PSR.

[Vivi, Rodrigo]

On Mon, 2015-07-27 at 10:36 +0200, Daniel Vetter wrote:
> On Fri, Jul 24, 2015 at 04:42:27PM -0700, Rodrigo Vivi wrote:
> > Since active function on VLV immediately activate PSR let's give more
> > time for idleness. Different from core platforms where we have idle_frames
> > count.
> > 
> > Also kms_psr_sink_crc now is automated and always get this:
> > 
> > [drm:intel_enable_pipe] enabling pipe A
> > [drm:intel_edp_backlight_on]
> > [drm:intel_panel_enable_backlight] pipe
> > [drm:intel_panel_enable_backlight] pipe A
> > [drm:intel_panel_actually_set_backlight] set backlight PWM = 7812
> > 
> > PSR gets enabled somewhere here after backlight.
> > 
> > [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000000, dig 0x0
> > [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
> > [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=391, cursor=63, sp
> > 
> > PSR gets flushed around here by intel_atomic_commit
> > 
> > [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
> > [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=391, cursor=63, sp
> > [drm:intel_set_memory_cxsr] memory self-refresh is enabled
> > [drm:intel_connector_check_state] [CONNECTOR:39:eDP-1]
> > [drm:check_encoder_state] [ENCODER:30:DAC-30]
> > [drm:check_encoder_state] [ENCODER:31:TMDS-31]
> > [drm:check_encoder_state] [ENCODER:36:TMDS-36]
> > [drm:check_encoder_state] [ENCODER:38:TMDS-38]
> > [drm:check_crtc_state] [CRTC:21]
> > [drm:check_crtc_state] [CRTC:26]
> > [drm:intel_psr_activate [i915]] *ERROR* PSR Active
> > [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000000, dig 0x
> > [drm:intel_set_cpu_fifo_underrun_reporting [i915]] *ERROR* pipe A underrun
> > [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe A FIFO
> > Underrun.
> > 
> > It is true that in a product we won't keep disabling and enabling planes so
> > frequently, but for safeness let's stay conservative.
> > 
> > It is also true that 500ms is an etternity. But PSR is anyway a power saving
> > feature for idle scenario. So if it is idle feature stays on and 500ms to get
> > it reanabled is not that insane.
> > 
> > v2: Rebase over intel_psr.c and fix typo.
> > v3: Revival: Manual tests indicated that this is needed. With a short delay
> >     there is a huge risk of getting blank screens when planes are being enabled.
> > v4: Revival 2 with reasonable delay. 1/2 sec instead of 5. VBT is 10 sec but
> >     actually time for link training what we aren't doing, but with only 100 sec
> >     in some cases kms_psr_sink_crc manual was showing blank screen,
> >     so let's use this for now. Also changed comment by a FIXME.
> > v5: Rebase after a long time, remove FIXME and update comment above.
> > v6: msecs_to_jiffies is already on delay. remove duplication.
> > 
> > Reviewed-by: Durgadoss R <durgadoss.r@intel.com> (v4)
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_psr.c | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> > index acd8ec8..bec13b8 100644
> > --- a/drivers/gpu/drm/i915/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > @@ -698,6 +698,7 @@ void intel_psr_flush(struct drm_device *dev,
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> >  	struct drm_crtc *crtc;
> >  	enum pipe pipe;
> > +	int delay = msecs_to_jiffies(HAS_DDI(dev) ? 100 : 500);
> 
> Note that for a timeout you should be using our own
> msecs_to_jiffies_timeout if it's for a timeout. This is needed since you
> can't know when the next jiffy update happens and that might be right
> away, therefore waiting for 10 jiffies might only be a wait for 9/HZ.
> Anyway tiny nitpick.

This is actually only used on schedule_delayed_work that receives the
numer of jiffies to wait.
I believe to avoid confusion I should let the msecs_to_jiffies on
schedule_delayed_work only and delay in ms. Do you want another v++?

> -Daniel
> 
> >  
> >  	mutex_lock(&dev_priv->psr.lock);
> >  	if (!dev_priv->psr.enabled) {
> > @@ -732,8 +733,7 @@ void intel_psr_flush(struct drm_device *dev,
> >  	}
> >  
> >  	if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
> > -		schedule_delayed_work(&dev_priv->psr.work,
> > -				      msecs_to_jiffies(100));
> > +		schedule_delayed_work(&dev_priv->psr.work, delay);
> >  	mutex_unlock(&dev_priv->psr.lock);
> >  }
> >  
> > -- 
> > 1.9.3
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 

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Re: [PATCH] drm/i915: VLV/CHV PSR: Increase wait delay time before active PSR.

[Daniel Vetter]

On Mon, Jul 27, 2015 at 06:37:28PM +0000, Vivi, Rodrigo wrote:
> On Mon, 2015-07-27 at 10:36 +0200, Daniel Vetter wrote:
> > On Fri, Jul 24, 2015 at 04:42:27PM -0700, Rodrigo Vivi wrote:
> > > Since active function on VLV immediately activate PSR let's give more
> > > time for idleness. Different from core platforms where we have idle_frames
> > > count.
> > > 
> > > Also kms_psr_sink_crc now is automated and always get this:
> > > 
> > > [drm:intel_enable_pipe] enabling pipe A
> > > [drm:intel_edp_backlight_on]
> > > [drm:intel_panel_enable_backlight] pipe
> > > [drm:intel_panel_enable_backlight] pipe A
> > > [drm:intel_panel_actually_set_backlight] set backlight PWM = 7812
> > > 
> > > PSR gets enabled somewhere here after backlight.
> > > 
> > > [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000000, dig 0x0
> > > [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
> > > [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=391, cursor=63, sp
> > > 
> > > PSR gets flushed around here by intel_atomic_commit
> > > 
> > > [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
> > > [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=391, cursor=63, sp
> > > [drm:intel_set_memory_cxsr] memory self-refresh is enabled
> > > [drm:intel_connector_check_state] [CONNECTOR:39:eDP-1]
> > > [drm:check_encoder_state] [ENCODER:30:DAC-30]
> > > [drm:check_encoder_state] [ENCODER:31:TMDS-31]
> > > [drm:check_encoder_state] [ENCODER:36:TMDS-36]
> > > [drm:check_encoder_state] [ENCODER:38:TMDS-38]
> > > [drm:check_crtc_state] [CRTC:21]
> > > [drm:check_crtc_state] [CRTC:26]
> > > [drm:intel_psr_activate [i915]] *ERROR* PSR Active
> > > [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000000, dig 0x
> > > [drm:intel_set_cpu_fifo_underrun_reporting [i915]] *ERROR* pipe A underrun
> > > [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe A FIFO
> > > Underrun.
> > > 
> > > It is true that in a product we won't keep disabling and enabling planes so
> > > frequently, but for safeness let's stay conservative.
> > > 
> > > It is also true that 500ms is an etternity. But PSR is anyway a power saving
> > > feature for idle scenario. So if it is idle feature stays on and 500ms to get
> > > it reanabled is not that insane.
> > > 
> > > v2: Rebase over intel_psr.c and fix typo.
> > > v3: Revival: Manual tests indicated that this is needed. With a short delay
> > >     there is a huge risk of getting blank screens when planes are being enabled.
> > > v4: Revival 2 with reasonable delay. 1/2 sec instead of 5. VBT is 10 sec but
> > >     actually time for link training what we aren't doing, but with only 100 sec
> > >     in some cases kms_psr_sink_crc manual was showing blank screen,
> > >     so let's use this for now. Also changed comment by a FIXME.
> > > v5: Rebase after a long time, remove FIXME and update comment above.
> > > v6: msecs_to_jiffies is already on delay. remove duplication.
> > > 
> > > Reviewed-by: Durgadoss R <durgadoss.r@intel.com> (v4)
> > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/intel_psr.c | 4 ++--
> > >  1 file changed, 2 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> > > index acd8ec8..bec13b8 100644
> > > --- a/drivers/gpu/drm/i915/intel_psr.c
> > > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > > @@ -698,6 +698,7 @@ void intel_psr_flush(struct drm_device *dev,
> > >  	struct drm_i915_private *dev_priv = dev->dev_private;
> > >  	struct drm_crtc *crtc;
> > >  	enum pipe pipe;
> > > +	int delay = msecs_to_jiffies(HAS_DDI(dev) ? 100 : 500);
> > 
> > Note that for a timeout you should be using our own
> > msecs_to_jiffies_timeout if it's for a timeout. This is needed since you
> > can't know when the next jiffy update happens and that might be right
> > away, therefore waiting for 10 jiffies might only be a wait for 9/HZ.
> > Anyway tiny nitpick.
> 
> This is actually only used on schedule_delayed_work that receives the
> numer of jiffies to wait.
> I believe to avoid confusion I should let the msecs_to_jiffies on
> schedule_delayed_work only and delay in ms. Do you want another v++?

If you feel like, was kinda just an aside bikeshed really. I'm just
constantly confused about jiffies timeouts myself ;-)
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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[PATCH] drm/i915: VLV/CHV PSR: Increase wait delay time before active PSR.

[Rodrigo Vivi]

Since active function on VLV immediately activate PSR let's give more
time for idleness. Different from core platforms where we have idle_frames
count.

Also kms_psr_sink_crc now is automated and always get this:

[drm:intel_enable_pipe] enabling pipe A
[drm:intel_edp_backlight_on]
[drm:intel_panel_enable_backlight] pipe
[drm:intel_panel_enable_backlight] pipe A
[drm:intel_panel_actually_set_backlight] set backlight PWM = 7812

PSR gets enabled somewhere here after backlight.

[drm:intel_get_hpd_pins] hotplug event received, stat 0x00000000, dig 0x0
[drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
[drm:vlv_update_wm] Setting FIFO watermarks - A: plane=391, cursor=63, sp

PSR gets flushed around here by intel_atomic_commit

[drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
[drm:vlv_update_wm] Setting FIFO watermarks - A: plane=391, cursor=63, sp
[drm:intel_set_memory_cxsr] memory self-refresh is enabled
[drm:intel_connector_check_state] [CONNECTOR:39:eDP-1]
[drm:check_encoder_state] [ENCODER:30:DAC-30]
[drm:check_encoder_state] [ENCODER:31:TMDS-31]
[drm:check_encoder_state] [ENCODER:36:TMDS-36]
[drm:check_encoder_state] [ENCODER:38:TMDS-38]
[drm:check_crtc_state] [CRTC:21]
[drm:check_crtc_state] [CRTC:26]
[drm:intel_psr_activate [i915]] *ERROR* PSR Active
[drm:intel_get_hpd_pins] hotplug event received, stat 0x00000000, dig 0x
[drm:intel_set_cpu_fifo_underrun_reporting [i915]] *ERROR* pipe A underrun
[drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe A FIFO
Underrun.

It is true that in a product we won't keep disabling and enabling planes so
frequently, but for safeness let's stay conservative.

It is also true that 500ms is an etternity. But PSR is anyway a power saving
feature for idle scenario. So if it is idle feature stays on and 500ms to get
it reanabled is not that insane.

v2: Rebase over intel_psr.c and fix typo.
v3: Revival: Manual tests indicated that this is needed. With a short delay
    there is a huge risk of getting blank screens when planes are being enabled.
v4: Revival 2 with reasonable delay. 1/2 sec instead of 5. VBT is 10 sec but
    actually time for link training what we aren't doing, but with only 100 sec
    in some cases kms_psr_sink_crc manual was showing blank screen,
    so let's use this for now. Also changed comment by a FIXME.
v5: Rebase after a long time, remove FIXME and update comment above.
v6: msecs_to_jiffies is already on delay. remove duplication.
v7: use msecs_to_jiffies on schedule_delayed_work call.

Reviewed-by: Durgadoss R <durgadoss.r@intel.com> (v4)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_psr.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index acd8ec8..a04b4dc 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -698,6 +698,7 @@ void intel_psr_flush(struct drm_device *dev,
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_crtc *crtc;
 	enum pipe pipe;
+	int delay_ms = HAS_DDI(dev) ? 100 : 500;
 
 	mutex_lock(&dev_priv->psr.lock);
 	if (!dev_priv->psr.enabled) {
@@ -733,7 +734,7 @@ void intel_psr_flush(struct drm_device *dev,
 
 	if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
 		schedule_delayed_work(&dev_priv->psr.work,
-				      msecs_to_jiffies(100));
+				      msecs_to_jiffies(delay_ms));
 	mutex_unlock(&dev_priv->psr.lock);
 }
 
-- 
2.1.0

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Re: [PATCH] drm/i915: VLV/CHV PSR: Increase wait delay time before active PSR.

[Daniel Vetter]

On Thu, Jul 30, 2015 at 05:07:55PM -0700, Rodrigo Vivi wrote:
> Since active function on VLV immediately activate PSR let's give more
> time for idleness. Different from core platforms where we have idle_frames
> count.
> 
> Also kms_psr_sink_crc now is automated and always get this:
> 
> [drm:intel_enable_pipe] enabling pipe A
> [drm:intel_edp_backlight_on]
> [drm:intel_panel_enable_backlight] pipe
> [drm:intel_panel_enable_backlight] pipe A
> [drm:intel_panel_actually_set_backlight] set backlight PWM = 7812
> 
> PSR gets enabled somewhere here after backlight.
> 
> [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000000, dig 0x0
> [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
> [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=391, cursor=63, sp
> 
> PSR gets flushed around here by intel_atomic_commit
> 
> [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511
> [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=391, cursor=63, sp
> [drm:intel_set_memory_cxsr] memory self-refresh is enabled
> [drm:intel_connector_check_state] [CONNECTOR:39:eDP-1]
> [drm:check_encoder_state] [ENCODER:30:DAC-30]
> [drm:check_encoder_state] [ENCODER:31:TMDS-31]
> [drm:check_encoder_state] [ENCODER:36:TMDS-36]
> [drm:check_encoder_state] [ENCODER:38:TMDS-38]
> [drm:check_crtc_state] [CRTC:21]
> [drm:check_crtc_state] [CRTC:26]
> [drm:intel_psr_activate [i915]] *ERROR* PSR Active
> [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000000, dig 0x
> [drm:intel_set_cpu_fifo_underrun_reporting [i915]] *ERROR* pipe A underrun
> [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe A FIFO
> Underrun.
> 
> It is true that in a product we won't keep disabling and enabling planes so
> frequently, but for safeness let's stay conservative.
> 
> It is also true that 500ms is an etternity. But PSR is anyway a power saving
> feature for idle scenario. So if it is idle feature stays on and 500ms to get
> it reanabled is not that insane.

Yeah I really like this level of detail in commit messages for tricky
bugs. Queued for -next, thanks for the patch.
-Daniel

> 
> v2: Rebase over intel_psr.c and fix typo.
> v3: Revival: Manual tests indicated that this is needed. With a short delay
>     there is a huge risk of getting blank screens when planes are being enabled.
> v4: Revival 2 with reasonable delay. 1/2 sec instead of 5. VBT is 10 sec but
>     actually time for link training what we aren't doing, but with only 100 sec
>     in some cases kms_psr_sink_crc manual was showing blank screen,
>     so let's use this for now. Also changed comment by a FIXME.
> v5: Rebase after a long time, remove FIXME and update comment above.
> v6: msecs_to_jiffies is already on delay. remove duplication.
> v7: use msecs_to_jiffies on schedule_delayed_work call.
> 
> Reviewed-by: Durgadoss R <durgadoss.r@intel.com> (v4)
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_psr.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index acd8ec8..a04b4dc 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -698,6 +698,7 @@ void intel_psr_flush(struct drm_device *dev,
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct drm_crtc *crtc;
>  	enum pipe pipe;
> +	int delay_ms = HAS_DDI(dev) ? 100 : 500;
>  
>  	mutex_lock(&dev_priv->psr.lock);
>  	if (!dev_priv->psr.enabled) {
> @@ -733,7 +734,7 @@ void intel_psr_flush(struct drm_device *dev,
>  
>  	if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
>  		schedule_delayed_work(&dev_priv->psr.work,
> -				      msecs_to_jiffies(100));
> +				      msecs_to_jiffies(delay_ms));
>  	mutex_unlock(&dev_priv->psr.lock);
>  }
>  
> -- 
> 2.1.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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