From: Jesse Barnes <jbarnes@virtuousgeek.org>
To: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: save/restore GMBUS freq across suspend/resume on gen4
Date: Wed, 10 Dec 2014 12:37:29 -0800 [thread overview]
Message-ID: <20141210123729.29d182b1@jbarnes-t420> (raw)
In-Reply-To: <20141210203537.GH10649@intel.com>
On Wed, 10 Dec 2014 22:35:37 +0200
Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Wed, Dec 10, 2014 at 12:16:05PM -0800, Jesse Barnes wrote:
> > Should probably just init this in the GMbus code all the time,
> > based on the cdclk and HPLL like we do on newer platforms. Ville
> > has code for that in a rework branch, but until then we can fix
> > this bug fairly easily.
> >
> > References: https://bugs.freedesktop.org/show_bug.cgi?id=76301
> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
>
> My cdclk extraction code doesn't seem to agree with this register for
> this particular bug reporter at least. So I think I need to go double
> check my code. The other options are that GMBUS clock isn't derived
> from cdclk on that platform, or that the HPLL/cdclk bits in configdb
> are simply not valid for this particular chipset.
>
> In the meantime however, we can at least get some machines working
> with this patch. I'm not entirely sure which platforms have this
> register, but IS_GEN4() looks safe enough since my 946GZ has it and
> the reporter has a G41.
>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Great, thanks. Jani, can you pick this up? I'll bounce the original
over to stable@ too.
Thanks,
Jesse
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next prev parent reply other threads:[~2014-12-10 20:37 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-12-10 20:16 [PATCH] drm/i915: save/restore GMBUS freq across suspend/resume on gen4 Jesse Barnes
2014-12-10 20:35 ` Ville Syrjälä
2014-12-10 20:37 ` Jesse Barnes [this message]
2014-12-11 13:41 ` Jani Nikula
2014-12-15 9:11 ` Daniel Vetter
2014-12-11 6:38 ` shuang.he
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