Re: [RFC PATCH 05/10] drm/i915: split get/set pipe timings to pipe and transcoder parts

From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Jani Nikula <jani.nikula@intel.com>
Cc: Deepak M <m.deepak@intel.com>, intel-gfx@lists.freedesktop.org
Subject: Re: [RFC PATCH 05/10] drm/i915: split get/set pipe timings to pipe and transcoder parts
Date: Wed, 16 Mar 2016 17:02:59 +0200	[thread overview]
Message-ID: <20160316150259.GG4329@intel.com> (raw)
In-Reply-To: <6ca1f9599c04e226ae59aeee2dff4f8a4bac6b26.1458070700.git.jani.nikula@intel.com>

On Tue, Mar 15, 2016 at 09:51:13PM +0200, Jani Nikula wrote:
> Prep work for DSI transcoders. No functional changes.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 27 +++++++++++++++++++++++----
>  1 file changed, 23 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 7977a818326d..4bfad0199232 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -7648,11 +7648,10 @@ static void i8xx_compute_dpll(struct intel_crtc *crtc,
>  	crtc_state->dpll_hw_state.dpll = dpll;
>  }
>  
> -static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
> +static void intel_set_trans_timings(struct intel_crtc *intel_crtc)
>  {
>  	struct drm_device *dev = intel_crtc->base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	enum pipe pipe = intel_crtc->pipe;
>  	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
>  	const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
>  	uint32_t crtc_vtotal, crtc_vblank_end;
> @@ -7699,6 +7698,16 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
>  	I915_WRITE(VSYNC(cpu_transcoder),
>  		   (adjusted_mode->crtc_vsync_start - 1) |
>  		   ((adjusted_mode->crtc_vsync_end - 1) << 16));
> +}
> +
> +static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
> +{
> +	struct drm_device *dev = intel_crtc->base.dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	enum pipe pipe = intel_crtc->pipe;
> +	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
> +
> +	intel_set_trans_timings(intel_crtc);
>  
>  	/* Workaround: when the EDP input selection is B, the VTOTAL_B must be
>  	 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is

You split seems to be in the wrong place, as in we just want to split
out the PIPESRC thing from the rest. I'd just call them
set_pipe_timings() and set_pipe_src_size(). And we'll need to call the
latter even with DSI.

> @@ -7716,8 +7725,8 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
>  		   (intel_crtc->config->pipe_src_h - 1));
>  }
>  
> -static void intel_get_pipe_timings(struct intel_crtc *crtc,
> -				   struct intel_crtc_state *pipe_config)
> +static void intel_get_trans_timings(struct intel_crtc *crtc,
> +				    struct intel_crtc_state *pipe_config)
>  {
>  	struct drm_device *dev = crtc->base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -7749,6 +7758,16 @@ static void intel_get_pipe_timings(struct intel_crtc *crtc,
>  		pipe_config->base.adjusted_mode.crtc_vtotal += 1;
>  		pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
>  	}
> +}
> +
> +static void intel_get_pipe_timings(struct intel_crtc *crtc,
> +				   struct intel_crtc_state *pipe_config)
> +{
> +	struct drm_device *dev = crtc->base.dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	uint32_t tmp;
> +
> +	intel_get_trans_timings(crtc, pipe_config);
>  
>  	tmp = I915_READ(PIPESRC(crtc->pipe));
>  	pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
> -- 
> 2.1.4

-- 
Ville Syrjälä
Intel OTC
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