From: Patchwork <patchwork@emeril.freedesktop.org>
To: Navare@emeril.freedesktop.org, Manasi D <manasi.d.navare@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: ✓ Fi.CI.BAT: success for drm/i915/dp: Validate cached link rate and lane count before retraining
Date: Fri, 24 Mar 2017 10:56:30 -0000 [thread overview]
Message-ID: <20170324105630.864.93063@emeril.freedesktop.org> (raw)
In-Reply-To: <1490310692-24468-1-git-send-email-manasi.d.navare@intel.com>
== Series Details ==
Series: drm/i915/dp: Validate cached link rate and lane count before retraining
URL : https://patchwork.freedesktop.org/series/21797/
State : success
== Summary ==
Series 21797v1 drm/i915/dp: Validate cached link rate and lane count before retraining
https://patchwork.freedesktop.org/api/1.0/series/21797/revisions/1/mbox/
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-c:
pass -> INCOMPLETE (fi-bsw-n3050) fdo#100113
fdo#100113 https://bugs.freedesktop.org/show_bug.cgi?id=100113
fi-bdw-5557u total:278 pass:267 dwarn:0 dfail:0 fail:0 skip:11 time: 467s
fi-bdw-gvtdvm total:278 pass:256 dwarn:8 dfail:0 fail:0 skip:14 time: 454s
fi-bsw-n3050 total:237 pass:201 dwarn:0 dfail:0 fail:0 skip:35 time: 0s
fi-bxt-j4205 total:278 pass:259 dwarn:0 dfail:0 fail:0 skip:19 time: 545s
fi-bxt-t5700 total:278 pass:258 dwarn:0 dfail:0 fail:0 skip:20 time: 562s
fi-byt-j1900 total:278 pass:251 dwarn:0 dfail:0 fail:0 skip:27 time: 508s
fi-byt-n2820 total:278 pass:247 dwarn:0 dfail:0 fail:0 skip:31 time: 503s
fi-hsw-4770 total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 time: 433s
fi-hsw-4770r total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 time: 437s
fi-ilk-650 total:278 pass:228 dwarn:0 dfail:0 fail:0 skip:50 time: 440s
fi-ivb-3520m total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time: 511s
fi-ivb-3770 total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time: 496s
fi-kbl-7500u total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time: 476s
fi-skl-6260u total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time: 486s
fi-skl-6700hq total:278 pass:261 dwarn:0 dfail:0 fail:0 skip:17 time: 601s
fi-skl-6700k total:278 pass:256 dwarn:4 dfail:0 fail:0 skip:18 time: 490s
fi-skl-6770hq total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time: 526s
fi-skl-gvtdvm total:278 pass:265 dwarn:0 dfail:0 fail:0 skip:13 time: 464s
fi-snb-2520m total:278 pass:250 dwarn:0 dfail:0 fail:0 skip:28 time: 549s
fi-snb-2600 total:278 pass:249 dwarn:0 dfail:0 fail:0 skip:29 time: 416s
fd27e1e4c9b5dc11966b4953432bd6e0510da308 drm-tip: 2017y-03m-24d-08h-39m-20s UTC integration manifest
44ec18c drm/i915/dp: Validate cached link rate and lane count before retraining
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4286/
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next prev parent reply other threads:[~2017-03-24 10:56 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-23 23:11 [PATCH] drm/i915/dp: Validate cached link rate and lane count before retraining Manasi Navare
2017-03-24 10:56 ` Patchwork [this message]
2017-03-27 13:40 ` Ville Syrjälä
2017-03-27 15:26 ` Jani Nikula
2017-03-27 16:53 ` Manasi Navare
2017-03-27 17:21 ` Ville Syrjälä
2017-03-27 18:44 ` Manasi Navare
2017-03-28 7:34 ` Jani Nikula
2017-03-28 15:46 ` Manasi Navare
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