[PATCH 1/2] drm/i915: Make some RPS functions static

[PATCH 1/2] drm/i915: Make some RPS functions static

[Oscar Mateo]

They are not used anywhere else. Also, fix a small typo in a comment.

No functional changes.

Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c  | 8 ++++----
 drivers/gpu/drm/i915/intel_drv.h | 3 ---
 2 files changed, 4 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index e21ce9c..5d391e6 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -336,7 +336,7 @@ void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
 	__gen6_mask_pm_irq(dev_priv, mask);
 }
 
-void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask)
+static void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask)
 {
 	i915_reg_t reg = gen6_pm_iir(dev_priv);
 
@@ -347,7 +347,7 @@ void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask)
 	POSTING_READ(reg);
 }
 
-void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mask)
+static void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mask)
 {
 	lockdep_assert_held(&dev_priv->irq_lock);
 
@@ -357,7 +357,7 @@ void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mask)
 	/* unmask_pm_irq provides an implicit barrier (POSTING_READ) */
 }
 
-void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 disable_mask)
+static void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 disable_mask)
 {
 	lockdep_assert_held(&dev_priv->irq_lock);
 
@@ -405,7 +405,7 @@ void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
 	synchronize_irq(dev_priv->drm.irq);
 
 	/* Now that we will not be generating any more work, flush any
-	 * outsanding tasks. As we are called on the RPS idle path,
+	 * outstanding tasks. As we are called on the RPS idle path,
 	 * we will reset the GPU to minimum frequencies, so the current
 	 * state of the worker can be discarded.
 	 */
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index f60995f..74c1860 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1206,11 +1206,8 @@ void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
 /* i915_irq.c */
 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
-void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 mask);
 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
-void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
-void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
-- 
1.9.1

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[PATCH 2/2] drm/i915: Create vfuncs for the reset/enable/disable GuC functions

[Oscar Mateo]

Facilitates creating Gen-specific versions of these functions later on.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_guc_submission.c |  4 ++--
 drivers/gpu/drm/i915/i915_irq.c            | 12 +++++++++---
 drivers/gpu/drm/i915/intel_drv.h           |  3 ---
 drivers/gpu/drm/i915/intel_guc_log.c       |  6 +++---
 drivers/gpu/drm/i915/intel_uc.c            |  8 ++++----
 drivers/gpu/drm/i915/intel_uc.h            |  4 ++++
 6 files changed, 22 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
index 48a1e93..63cd9da 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -1302,7 +1302,7 @@ int intel_guc_suspend(struct drm_i915_private *dev_priv)
 	if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
 		return 0;
 
-	gen9_disable_guc_interrupts(dev_priv);
+	guc->disable_guc_interrupts(dev_priv);
 
 	ctx = dev_priv->kernel_context;
 
@@ -1329,7 +1329,7 @@ int intel_guc_resume(struct drm_i915_private *dev_priv)
 		return 0;
 
 	if (i915.guc_log_level >= 0)
-		gen9_enable_guc_interrupts(dev_priv);
+		guc->enable_guc_interrupts(dev_priv);
 
 	ctx = dev_priv->kernel_context;
 
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 5d391e6..23be825 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -413,14 +413,14 @@ void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
 	gen6_reset_rps_interrupts(dev_priv);
 }
 
-void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv)
+static void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv)
 {
 	spin_lock_irq(&dev_priv->irq_lock);
 	gen6_reset_pm_iir(dev_priv, dev_priv->pm_guc_events);
 	spin_unlock_irq(&dev_priv->irq_lock);
 }
 
-void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv)
+static void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv)
 {
 	spin_lock_irq(&dev_priv->irq_lock);
 	if (!dev_priv->guc.interrupts_enabled) {
@@ -432,7 +432,7 @@ void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv)
 	spin_unlock_irq(&dev_priv->irq_lock);
 }
 
-void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv)
+static void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv)
 {
 	spin_lock_irq(&dev_priv->irq_lock);
 	dev_priv->guc.interrupts_enabled = false;
@@ -4164,6 +4164,12 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
 	if (INTEL_GEN(dev_priv) >= 8)
 		dev_priv->rps.pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
 
+	if (INTEL_GEN(dev_priv) >= 9) {
+		dev_priv->guc.reset_guc_interrupts = gen9_reset_guc_interrupts;
+		dev_priv->guc.enable_guc_interrupts = gen9_enable_guc_interrupts;
+		dev_priv->guc.disable_guc_interrupts = gen9_disable_guc_interrupts;
+	}
+
 	if (IS_GEN2(dev_priv)) {
 		/* Gen2 doesn't have a hardware frame counter */
 		dev->max_vblank_count = 0;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 74c1860..442d378 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1234,9 +1234,6 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
 				     u8 pipe_mask);
 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
 				     u8 pipe_mask);
-void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
-void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
-void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
 
 /* intel_crt.c */
 void intel_crt_init(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c b/drivers/gpu/drm/i915/intel_guc_log.c
index 16d3b87..d402900 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -506,7 +506,7 @@ static void guc_flush_logs(struct intel_guc *guc)
 		return;
 
 	/* First disable the interrupts, will be renabled afterwards */
-	gen9_disable_guc_interrupts(dev_priv);
+	guc->disable_guc_interrupts(dev_priv);
 
 	/* Before initiating the forceful flush, wait for any pending/ongoing
 	 * flush to complete otherwise forceful flush may not actually happen.
@@ -623,7 +623,7 @@ int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val)
 		}
 
 		/* GuC logging is currently the only user of Guc2Host interrupts */
-		gen9_enable_guc_interrupts(dev_priv);
+		guc->enable_guc_interrupts(dev_priv);
 	} else {
 		/* Once logging is disabled, GuC won't generate logs & send an
 		 * interrupt. But there could be some data in the log buffer
@@ -656,7 +656,7 @@ void i915_guc_log_unregister(struct drm_i915_private *dev_priv)
 
 	mutex_lock(&dev_priv->drm.struct_mutex);
 	/* GuC logging is currently the only user of Guc2Host interrupts */
-	gen9_disable_guc_interrupts(dev_priv);
+	dev_priv->guc.enable_guc_interrupts(dev_priv);
 	guc_log_runtime_destroy(&dev_priv->guc);
 	mutex_unlock(&dev_priv->drm.struct_mutex);
 }
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 0178ba4..6df0d3b 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -337,7 +337,7 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
 		return 0;
 
 	guc_disable_communication(guc);
-	gen9_reset_guc_interrupts(dev_priv);
+	guc->reset_guc_interrupts(dev_priv);
 
 	/* We need to notify the guc whenever we change the GGTT */
 	i915_ggtt_enable_guc(dev_priv);
@@ -393,7 +393,7 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
 	intel_guc_auth_huc(dev_priv);
 	if (i915.enable_guc_submission) {
 		if (i915.guc_log_level >= 0)
-			gen9_enable_guc_interrupts(dev_priv);
+			guc->enable_guc_interrupts(dev_priv);
 
 		ret = i915_guc_submission_enable(dev_priv);
 		if (ret)
@@ -413,7 +413,7 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
 	 */
 err_interrupts:
 	guc_disable_communication(guc);
-	gen9_disable_guc_interrupts(dev_priv);
+	guc->disable_guc_interrupts(dev_priv);
 err_log_capture:
 	guc_capture_load_err_log(guc);
 err_submission:
@@ -452,7 +452,7 @@ void intel_uc_fini_hw(struct drm_i915_private *dev_priv)
 	guc_disable_communication(&dev_priv->guc);
 
 	if (i915.enable_guc_submission) {
-		gen9_disable_guc_interrupts(dev_priv);
+		dev_priv->guc.disable_guc_interrupts(dev_priv);
 		i915_guc_submission_fini(dev_priv);
 	}
 
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index 22ae52b..e862454 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -210,6 +210,10 @@ struct intel_guc {
 
 	/* GuC's FW specific notify function */
 	void (*notify)(struct intel_guc *guc);
+
+	void (*reset_guc_interrupts)(struct drm_i915_private *dev_priv);
+	void (*enable_guc_interrupts)(struct drm_i915_private *dev_priv);
+	void (*disable_guc_interrupts)(struct drm_i915_private *dev_priv);
 };
 
 struct intel_huc {
-- 
1.9.1

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Re: [PATCH 2/2] drm/i915: Create vfuncs for the reset/enable/disable GuC functions

[Michal Wajdeczko]

On Wed, Aug 23, 2017 at 04:58:25PM -0700, Oscar Mateo wrote:
> Facilitates creating Gen-specific versions of these functions later on.
> 
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_guc_submission.c |  4 ++--
>  drivers/gpu/drm/i915/i915_irq.c            | 12 +++++++++---
>  drivers/gpu/drm/i915/intel_drv.h           |  3 ---
>  drivers/gpu/drm/i915/intel_guc_log.c       |  6 +++---
>  drivers/gpu/drm/i915/intel_uc.c            |  8 ++++----
>  drivers/gpu/drm/i915/intel_uc.h            |  4 ++++
>  6 files changed, 22 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
> index 48a1e93..63cd9da 100644
> --- a/drivers/gpu/drm/i915/i915_guc_submission.c
> +++ b/drivers/gpu/drm/i915/i915_guc_submission.c
> @@ -1302,7 +1302,7 @@ int intel_guc_suspend(struct drm_i915_private *dev_priv)
>  	if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
>  		return 0;
>  
> -	gen9_disable_guc_interrupts(dev_priv);
> +	guc->disable_guc_interrupts(dev_priv);
>  
>  	ctx = dev_priv->kernel_context;
>  
> @@ -1329,7 +1329,7 @@ int intel_guc_resume(struct drm_i915_private *dev_priv)
>  		return 0;
>  
>  	if (i915.guc_log_level >= 0)
> -		gen9_enable_guc_interrupts(dev_priv);
> +		guc->enable_guc_interrupts(dev_priv);
>  
>  	ctx = dev_priv->kernel_context;
>  
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 5d391e6..23be825 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -413,14 +413,14 @@ void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
>  	gen6_reset_rps_interrupts(dev_priv);
>  }
>  
> -void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv)
> +static void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv)
>  {
>  	spin_lock_irq(&dev_priv->irq_lock);
>  	gen6_reset_pm_iir(dev_priv, dev_priv->pm_guc_events);
>  	spin_unlock_irq(&dev_priv->irq_lock);
>  }
>  
> -void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv)
> +static void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv)
>  {
>  	spin_lock_irq(&dev_priv->irq_lock);
>  	if (!dev_priv->guc.interrupts_enabled) {
> @@ -432,7 +432,7 @@ void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv)
>  	spin_unlock_irq(&dev_priv->irq_lock);
>  }
>  
> -void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv)
> +static void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv)
>  {
>  	spin_lock_irq(&dev_priv->irq_lock);
>  	dev_priv->guc.interrupts_enabled = false;
> @@ -4164,6 +4164,12 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
>  	if (INTEL_GEN(dev_priv) >= 8)
>  		dev_priv->rps.pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
>  
> +	if (INTEL_GEN(dev_priv) >= 9) {
> +		dev_priv->guc.reset_guc_interrupts = gen9_reset_guc_interrupts;
> +		dev_priv->guc.enable_guc_interrupts = gen9_enable_guc_interrupts;
> +		dev_priv->guc.disable_guc_interrupts = gen9_disable_guc_interrupts;
> +	}
> +
>  	if (IS_GEN2(dev_priv)) {
>  		/* Gen2 doesn't have a hardware frame counter */
>  		dev->max_vblank_count = 0;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 74c1860..442d378 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1234,9 +1234,6 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
>  				     u8 pipe_mask);
>  void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
>  				     u8 pipe_mask);
> -void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
> -void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
> -void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
>  
>  /* intel_crt.c */
>  void intel_crt_init(struct drm_i915_private *dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_guc_log.c b/drivers/gpu/drm/i915/intel_guc_log.c
> index 16d3b87..d402900 100644
> --- a/drivers/gpu/drm/i915/intel_guc_log.c
> +++ b/drivers/gpu/drm/i915/intel_guc_log.c
> @@ -506,7 +506,7 @@ static void guc_flush_logs(struct intel_guc *guc)
>  		return;
>  
>  	/* First disable the interrupts, will be renabled afterwards */
> -	gen9_disable_guc_interrupts(dev_priv);
> +	guc->disable_guc_interrupts(dev_priv);
>  
>  	/* Before initiating the forceful flush, wait for any pending/ongoing
>  	 * flush to complete otherwise forceful flush may not actually happen.
> @@ -623,7 +623,7 @@ int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val)
>  		}
>  
>  		/* GuC logging is currently the only user of Guc2Host interrupts */
> -		gen9_enable_guc_interrupts(dev_priv);
> +		guc->enable_guc_interrupts(dev_priv);
>  	} else {
>  		/* Once logging is disabled, GuC won't generate logs & send an
>  		 * interrupt. But there could be some data in the log buffer
> @@ -656,7 +656,7 @@ void i915_guc_log_unregister(struct drm_i915_private *dev_priv)
>  
>  	mutex_lock(&dev_priv->drm.struct_mutex);
>  	/* GuC logging is currently the only user of Guc2Host interrupts */
> -	gen9_disable_guc_interrupts(dev_priv);
> +	dev_priv->guc.enable_guc_interrupts(dev_priv);
>  	guc_log_runtime_destroy(&dev_priv->guc);
>  	mutex_unlock(&dev_priv->drm.struct_mutex);
>  }
> diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
> index 0178ba4..6df0d3b 100644
> --- a/drivers/gpu/drm/i915/intel_uc.c
> +++ b/drivers/gpu/drm/i915/intel_uc.c
> @@ -337,7 +337,7 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
>  		return 0;
>  
>  	guc_disable_communication(guc);
> -	gen9_reset_guc_interrupts(dev_priv);
> +	guc->reset_guc_interrupts(dev_priv);
>  
>  	/* We need to notify the guc whenever we change the GGTT */
>  	i915_ggtt_enable_guc(dev_priv);
> @@ -393,7 +393,7 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
>  	intel_guc_auth_huc(dev_priv);
>  	if (i915.enable_guc_submission) {
>  		if (i915.guc_log_level >= 0)
> -			gen9_enable_guc_interrupts(dev_priv);
> +			guc->enable_guc_interrupts(dev_priv);
>  
>  		ret = i915_guc_submission_enable(dev_priv);
>  		if (ret)
> @@ -413,7 +413,7 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
>  	 */
>  err_interrupts:
>  	guc_disable_communication(guc);
> -	gen9_disable_guc_interrupts(dev_priv);
> +	guc->disable_guc_interrupts(dev_priv);
>  err_log_capture:
>  	guc_capture_load_err_log(guc);
>  err_submission:
> @@ -452,7 +452,7 @@ void intel_uc_fini_hw(struct drm_i915_private *dev_priv)
>  	guc_disable_communication(&dev_priv->guc);
>  
>  	if (i915.enable_guc_submission) {
> -		gen9_disable_guc_interrupts(dev_priv);
> +		dev_priv->guc.disable_guc_interrupts(dev_priv);
>  		i915_guc_submission_fini(dev_priv);
>  	}
>  
> diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
> index 22ae52b..e862454 100644
> --- a/drivers/gpu/drm/i915/intel_uc.h
> +++ b/drivers/gpu/drm/i915/intel_uc.h
> @@ -210,6 +210,10 @@ struct intel_guc {
>  
>  	/* GuC's FW specific notify function */
>  	void (*notify)(struct intel_guc *guc);
> +
> +	void (*reset_guc_interrupts)(struct drm_i915_private *dev_priv);
> +	void (*enable_guc_interrupts)(struct drm_i915_private *dev_priv);
> +	void (*disable_guc_interrupts)(struct drm_i915_private *dev_priv);

These vfuncs are defined on the "guc" struct so you can drop "_guc" from
their names. And maybe they shall be closer to existing "interrupts_enabled"
field to keep all related stuff together. Then we can try to do like this:

- bool interrupts_enabled;
+ struct {
+	bool enabled;
+	void (*reset)(struct drm_i915_private *dev_priv);
+	void (*enable)(struct drm_i915_private *dev_priv);
+	void (*disable)(struct drm_i915_private *dev_priv);
+ } interrupts;


Thanks,
Michal

>  };
>  
>  struct intel_huc {
> -- 
> 1.9.1
> 
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[PATCH] drm/i915: Create vfuncs for the reset/enable/disable GuC functions

[Oscar Mateo]

Facilitates creating Gen-specific versions of these functions later on.

v2: Move everything into guc.interrupts (Michal)

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_guc_submission.c |  4 ++--
 drivers/gpu/drm/i915/i915_irq.c            | 18 ++++++++++++------
 drivers/gpu/drm/i915/intel_drv.h           |  3 ---
 drivers/gpu/drm/i915/intel_guc_log.c       |  6 +++---
 drivers/gpu/drm/i915/intel_uc.c            |  8 ++++----
 drivers/gpu/drm/i915/intel_uc.h            |  7 ++++++-
 6 files changed, 27 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
index 48a1e93..b469326 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -1302,7 +1302,7 @@ int intel_guc_suspend(struct drm_i915_private *dev_priv)
 	if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
 		return 0;
 
-	gen9_disable_guc_interrupts(dev_priv);
+	guc->interrupts.disable(dev_priv);
 
 	ctx = dev_priv->kernel_context;
 
@@ -1329,7 +1329,7 @@ int intel_guc_resume(struct drm_i915_private *dev_priv)
 		return 0;
 
 	if (i915.guc_log_level >= 0)
-		gen9_enable_guc_interrupts(dev_priv);
+		guc->interrupts.enable(dev_priv);
 
 	ctx = dev_priv->kernel_context;
 
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 5d391e6..9649df4 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -413,29 +413,29 @@ void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
 	gen6_reset_rps_interrupts(dev_priv);
 }
 
-void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv)
+static void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv)
 {
 	spin_lock_irq(&dev_priv->irq_lock);
 	gen6_reset_pm_iir(dev_priv, dev_priv->pm_guc_events);
 	spin_unlock_irq(&dev_priv->irq_lock);
 }
 
-void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv)
+static void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv)
 {
 	spin_lock_irq(&dev_priv->irq_lock);
-	if (!dev_priv->guc.interrupts_enabled) {
+	if (!dev_priv->guc.interrupts.enabled) {
 		WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
 				       dev_priv->pm_guc_events);
-		dev_priv->guc.interrupts_enabled = true;
+		dev_priv->guc.interrupts.enabled = true;
 		gen6_enable_pm_irq(dev_priv, dev_priv->pm_guc_events);
 	}
 	spin_unlock_irq(&dev_priv->irq_lock);
 }
 
-void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv)
+static void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv)
 {
 	spin_lock_irq(&dev_priv->irq_lock);
-	dev_priv->guc.interrupts_enabled = false;
+	dev_priv->guc.interrupts.enabled = false;
 
 	gen6_disable_pm_irq(dev_priv, dev_priv->pm_guc_events);
 
@@ -4164,6 +4164,12 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
 	if (INTEL_GEN(dev_priv) >= 8)
 		dev_priv->rps.pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
 
+	if (INTEL_GEN(dev_priv) >= 9) {
+		dev_priv->guc.interrupts.reset = gen9_reset_guc_interrupts;
+		dev_priv->guc.interrupts.enable = gen9_enable_guc_interrupts;
+		dev_priv->guc.interrupts.disable = gen9_disable_guc_interrupts;
+	}
+
 	if (IS_GEN2(dev_priv)) {
 		/* Gen2 doesn't have a hardware frame counter */
 		dev->max_vblank_count = 0;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 74c1860..442d378 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1234,9 +1234,6 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
 				     u8 pipe_mask);
 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
 				     u8 pipe_mask);
-void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
-void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
-void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
 
 /* intel_crt.c */
 void intel_crt_init(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c b/drivers/gpu/drm/i915/intel_guc_log.c
index 16d3b87..a067bba 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -506,7 +506,7 @@ static void guc_flush_logs(struct intel_guc *guc)
 		return;
 
 	/* First disable the interrupts, will be renabled afterwards */
-	gen9_disable_guc_interrupts(dev_priv);
+	guc->interrupts.disable(dev_priv);
 
 	/* Before initiating the forceful flush, wait for any pending/ongoing
 	 * flush to complete otherwise forceful flush may not actually happen.
@@ -623,7 +623,7 @@ int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val)
 		}
 
 		/* GuC logging is currently the only user of Guc2Host interrupts */
-		gen9_enable_guc_interrupts(dev_priv);
+		guc->interrupts.enable(dev_priv);
 	} else {
 		/* Once logging is disabled, GuC won't generate logs & send an
 		 * interrupt. But there could be some data in the log buffer
@@ -656,7 +656,7 @@ void i915_guc_log_unregister(struct drm_i915_private *dev_priv)
 
 	mutex_lock(&dev_priv->drm.struct_mutex);
 	/* GuC logging is currently the only user of Guc2Host interrupts */
-	gen9_disable_guc_interrupts(dev_priv);
+	dev_priv->guc.interrupts.disable(dev_priv);
 	guc_log_runtime_destroy(&dev_priv->guc);
 	mutex_unlock(&dev_priv->drm.struct_mutex);
 }
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 0178ba4..ff0f208 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -337,7 +337,7 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
 		return 0;
 
 	guc_disable_communication(guc);
-	gen9_reset_guc_interrupts(dev_priv);
+	guc->interrupts.reset(dev_priv);
 
 	/* We need to notify the guc whenever we change the GGTT */
 	i915_ggtt_enable_guc(dev_priv);
@@ -393,7 +393,7 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
 	intel_guc_auth_huc(dev_priv);
 	if (i915.enable_guc_submission) {
 		if (i915.guc_log_level >= 0)
-			gen9_enable_guc_interrupts(dev_priv);
+			guc->interrupts.enable(dev_priv);
 
 		ret = i915_guc_submission_enable(dev_priv);
 		if (ret)
@@ -413,7 +413,7 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
 	 */
 err_interrupts:
 	guc_disable_communication(guc);
-	gen9_disable_guc_interrupts(dev_priv);
+	guc->interrupts.disable(dev_priv);
 err_log_capture:
 	guc_capture_load_err_log(guc);
 err_submission:
@@ -452,7 +452,7 @@ void intel_uc_fini_hw(struct drm_i915_private *dev_priv)
 	guc_disable_communication(&dev_priv->guc);
 
 	if (i915.enable_guc_submission) {
-		gen9_disable_guc_interrupts(dev_priv);
+		dev_priv->guc.interrupts.disable(dev_priv);
 		i915_guc_submission_fini(dev_priv);
 	}
 
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index 22ae52b..0640a83 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -183,7 +183,12 @@ struct intel_guc {
 	struct drm_i915_gem_object *load_err_log;
 
 	/* intel_guc_recv interrupt related state */
-	bool interrupts_enabled;
+	struct {
+		bool enabled;
+		void (*reset)(struct drm_i915_private *dev_priv);
+		void (*enable)(struct drm_i915_private *dev_priv);
+		void (*disable)(struct drm_i915_private *dev_priv);
+	} interrupts;
 
 	struct i915_vma *ads_vma;
 	struct i915_vma *stage_desc_pool;
-- 
1.9.1

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✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Make some RPS functions static

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915: Make some RPS functions static
URL   : https://patchwork.freedesktop.org/series/29251/
State : success

== Summary ==

Series 29251v1 series starting with [1/2] drm/i915: Make some RPS functions static
https://patchwork.freedesktop.org/api/1.0/series/29251/revisions/1/mbox/

Test kms_flip:
        Subgroup basic-flip-vs-modeset:
                skip       -> PASS       (fi-skl-x1585l) fdo#101781
Test kms_pipe_crc_basic:
        Subgroup suspend-read-crc-pipe-c:
                fail       -> PASS       (fi-skl-6700k) fdo#100367

fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781
fdo#100367 https://bugs.freedesktop.org/show_bug.cgi?id=100367

fi-bdw-5557u     total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  time:453s
fi-bdw-gvtdvm    total:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  time:441s
fi-blb-e6850     total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  time:366s
fi-bsw-n3050     total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  time:561s
fi-bwr-2160      total:279  pass:184  dwarn:0   dfail:0   fail:0   skip:95  time:253s
fi-bxt-j4205     total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  time:517s
fi-byt-j1900     total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  time:531s
fi-byt-n2820     total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  time:525s
fi-elk-e7500     total:279  pass:230  dwarn:0   dfail:0   fail:0   skip:49  time:442s
fi-glk-2a        total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  time:609s
fi-hsw-4770      total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  time:444s
fi-hsw-4770r     total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  time:423s
fi-ilk-650       total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  time:421s
fi-ivb-3520m     total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:508s
fi-ivb-3770      total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:473s
fi-kbl-7500u     total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:470s
fi-kbl-7560u     total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  time:601s
fi-kbl-r         total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:593s
fi-pnv-d510      total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  time:527s
fi-skl-6260u     total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  time:463s
fi-skl-6700k     total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:480s
fi-skl-6770hq    total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  time:490s
fi-skl-gvtdvm    total:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  time:445s
fi-skl-x1585l    total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  time:505s
fi-snb-2520m     total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  time:548s
fi-snb-2600      total:279  pass:250  dwarn:0   dfail:0   fail:0   skip:29  time:406s

3adc9e3cacefe82619fc56ec78a0ca3a67a4b00c drm-tip: 2017y-08m-23d-21h-35m-35s UTC integration manifest
d7a66a3faa21 drm/i915: Create vfuncs for the reset/enable/disable GuC functions
27660efdf6ad drm/i915: Make some RPS functions static

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5482/
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Re: [PATCH 1/2] drm/i915: Make some RPS functions static

[Kamble, Sagar A]

Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>

-----Original Message-----
From: Mateo Lozano, Oscar 
Sent: Thursday, August 24, 2017 5:28 AM
To: intel-gfx@lists.freedesktop.org
Cc: Mateo Lozano, Oscar <oscar.mateo@intel.com>; Kamble, Sagar A <sagar.a.kamble@intel.com>; Vivi, Rodrigo <rodrigo.vivi@intel.com>
Subject: [PATCH 1/2] drm/i915: Make some RPS functions static

They are not used anywhere else. Also, fix a small typo in a comment.

No functional changes.

Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c  | 8 ++++----
 drivers/gpu/drm/i915/intel_drv.h | 3 ---
 2 files changed, 4 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index e21ce9c..5d391e6 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -336,7 +336,7 @@ void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
 	__gen6_mask_pm_irq(dev_priv, mask);
 }
 
-void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask)
+static void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask)
 {
 	i915_reg_t reg = gen6_pm_iir(dev_priv);
 
@@ -347,7 +347,7 @@ void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask)
 	POSTING_READ(reg);
 }
 
-void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mask)
+static void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mask)
 {
 	lockdep_assert_held(&dev_priv->irq_lock);
 
@@ -357,7 +357,7 @@ void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mask)
 	/* unmask_pm_irq provides an implicit barrier (POSTING_READ) */
 }
 
-void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 disable_mask)
+static void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 disable_mask)
 {
 	lockdep_assert_held(&dev_priv->irq_lock);
 
@@ -405,7 +405,7 @@ void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
 	synchronize_irq(dev_priv->drm.irq);
 
 	/* Now that we will not be generating any more work, flush any
-	 * outsanding tasks. As we are called on the RPS idle path,
+	 * outstanding tasks. As we are called on the RPS idle path,
 	 * we will reset the GPU to minimum frequencies, so the current
 	 * state of the worker can be discarded.
 	 */
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index f60995f..74c1860 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1206,11 +1206,8 @@ void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
 /* i915_irq.c */
 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
-void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 mask);
 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
-void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
-void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
-- 
1.9.1

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Re: [PATCH 1/2] drm/i915: Make some RPS functions static

[Rodrigo Vivi]

Since this on has no functional change and passed ci and is rv-b I
merged  patch 1 to dinq already

Thanks for patch and review.

For next time it would be good to send separated patches since patches
1 and 2 have no directly relation...
So CI test them individually.

On Thu, Aug 24, 2017 at 3:28 AM, Kamble, Sagar A
<sagar.a.kamble@intel.com> wrote:
> Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
>
> -----Original Message-----
> From: Mateo Lozano, Oscar
> Sent: Thursday, August 24, 2017 5:28 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Mateo Lozano, Oscar <oscar.mateo@intel.com>; Kamble, Sagar A <sagar.a.kamble@intel.com>; Vivi, Rodrigo <rodrigo.vivi@intel.com>
> Subject: [PATCH 1/2] drm/i915: Make some RPS functions static
>
> They are not used anywhere else. Also, fix a small typo in a comment.
>
> No functional changes.
>
> Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_irq.c  | 8 ++++----
>  drivers/gpu/drm/i915/intel_drv.h | 3 ---
>  2 files changed, 4 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index e21ce9c..5d391e6 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -336,7 +336,7 @@ void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
>         __gen6_mask_pm_irq(dev_priv, mask);
>  }
>
> -void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask)
> +static void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask)
>  {
>         i915_reg_t reg = gen6_pm_iir(dev_priv);
>
> @@ -347,7 +347,7 @@ void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask)
>         POSTING_READ(reg);
>  }
>
> -void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mask)
> +static void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mask)
>  {
>         lockdep_assert_held(&dev_priv->irq_lock);
>
> @@ -357,7 +357,7 @@ void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mask)
>         /* unmask_pm_irq provides an implicit barrier (POSTING_READ) */
>  }
>
> -void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 disable_mask)
> +static void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 disable_mask)
>  {
>         lockdep_assert_held(&dev_priv->irq_lock);
>
> @@ -405,7 +405,7 @@ void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
>         synchronize_irq(dev_priv->drm.irq);
>
>         /* Now that we will not be generating any more work, flush any
> -        * outsanding tasks. As we are called on the RPS idle path,
> +        * outstanding tasks. As we are called on the RPS idle path,
>          * we will reset the GPU to minimum frequencies, so the current
>          * state of the worker can be discarded.
>          */
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index f60995f..74c1860 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1206,11 +1206,8 @@ void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
>  /* i915_irq.c */
>  void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
>  void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
> -void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 mask);
>  void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
>  void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
> -void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
> -void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
>  void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
>  void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
>  void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
> --
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
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✗ Fi.CI.BAT: failure for series starting with [2/2] drm/i915: Create vfuncs for the reset/enable/disable GuC functions (rev3)

[Patchwork]

== Series Details ==

Series: series starting with [2/2] drm/i915: Create vfuncs for the reset/enable/disable GuC functions (rev3)
URL   : https://patchwork.freedesktop.org/series/29251/
State : failure

== Summary ==

  CHK     include/config/kernel.release
  CHK     include/generated/uapi/linux/version.h
  CHK     include/generated/utsrelease.h
  CHK     include/generated/bounds.h
  CHK     include/generated/timeconst.h
  CHK     include/generated/asm-offsets.h
  CALL    scripts/checksyscalls.sh
  CHK     scripts/mod/devicetable-offsets.h
  CHK     include/generated/compile.h
  CHK     kernel/config_data.h
  CC [M]  drivers/gpu/drm/i915/i915_irq.o
drivers/gpu/drm/i915/i915_irq.c: In function ‘intel_irq_init’:
drivers/gpu/drm/i915/i915_irq.c:4168:1: error: version control conflict marker in file
 <<<<<<< HEAD
 ^~~~~~~
drivers/gpu/drm/i915/i915_irq.c:4172:1: error: version control conflict marker in file
 =======
 ^~~~~~~
drivers/gpu/drm/i915/i915_irq.c:4176:1: error: version control conflict marker in file
 >>>>>>> drm/i915: Create vfuncs for the reset/enable/disable GuC functions
 ^~~~~~~
scripts/Makefile.build:302: recipe for target 'drivers/gpu/drm/i915/i915_irq.o' failed
make[4]: *** [drivers/gpu/drm/i915/i915_irq.o] Error 1
scripts/Makefile.build:561: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:561: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:561: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1019: recipe for target 'drivers' failed
make: *** [drivers] Error 2

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