* [PATCH] drm/i915/cnl: Get RC6 working.
@ 2017-10-23 21:20 Rodrigo Vivi
2017-10-23 21:45 ` ✓ Fi.CI.BAT: success for " Patchwork
` (5 more replies)
0 siblings, 6 replies; 10+ messages in thread
From: Rodrigo Vivi @ 2017-10-23 21:20 UTC (permalink / raw)
To: intel-gfx; +Cc: Wayne Boyer, Nathan Ciobanu, Rodrigo Vivi
On CNL, individual ware rate limit was added to each engine.
GT can only go to RC6 if both Render and Media engines are
idividually qualified. So we need to set their individual
wake rate limit.
+-----------------+---------------+--------------+--------------+
| | GT RC6 | Render C6 | Media C6 |
+-----------------+---------------+--------------+--------------+
| Wake rate limit | 0xA09C[31:16] | 0xA09C[15:0] | 0xA0A0[15:0] |
+-----------------+---------------+--------------+--------------+
Cc: Nathan Ciobanu <nathan.d.ciobanu@intel.com>
Cc: Wayne Boyer <wayne.boyer@intel.com>
Cc: Joe Konno <joe.konno@linux.intel.com>
Cc: David Weinehall <david.weinehall@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 15 +++++++++++----
2 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 68a58cce6ab1..f138eae82bf0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7905,6 +7905,7 @@ enum {
#define GEN6_RC1_WAKE_RATE_LIMIT _MMIO(0xA098)
#define GEN6_RC6_WAKE_RATE_LIMIT _MMIO(0xA09C)
#define GEN6_RC6pp_WAKE_RATE_LIMIT _MMIO(0xA0A0)
+#define GEN10_MEDIA_WAKE_RATE_LIMIT _MMIO(0xA0A0)
#define GEN6_RC_EVALUATION_INTERVAL _MMIO(0xA0A8)
#define GEN6_RC_IDLE_HYSTERSIS _MMIO(0xA0AC)
#define GEN6_RC_SLEEP _MMIO(0xA0B0)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5fdae39b1969..b193eda65e81 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6605,12 +6605,19 @@ static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
I915_WRITE(GEN6_RC_CONTROL, 0);
/* 2b: Program RC6 thresholds.*/
-
- /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
- if (IS_SKYLAKE(dev_priv))
+ if (INTEL_GEN(dev_priv) >= 10) {
+ I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 54);
+ I915_WRITE(GEN10_MEDIA_WAKE_RATE_LIMIT, 54);
+ } else if (IS_SKYLAKE(dev_priv)) {
+ /*
+ * WaRsDoubleRc6WrlWithCoarsePowerGating:skl Doubling WRL only
+ * when CPG is enabled
+ */
I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
- else
+ } else {
I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
+ }
+
I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
for_each_engine(engine, dev_priv, id)
--
2.13.5
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^ permalink raw reply related [flat|nested] 10+ messages in thread* ✓ Fi.CI.BAT: success for drm/i915/cnl: Get RC6 working.
2017-10-23 21:20 [PATCH] drm/i915/cnl: Get RC6 working Rodrigo Vivi
@ 2017-10-23 21:45 ` Patchwork
2017-10-23 22:17 ` [PATCH] " James Ausmus
` (4 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2017-10-23 21:45 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/cnl: Get RC6 working.
URL : https://patchwork.freedesktop.org/series/32491/
State : success
== Summary ==
Series 32491v1 drm/i915/cnl: Get RC6 working.
https://patchwork.freedesktop.org/api/1.0/series/32491/revisions/1/mbox/
Test chamelium:
Subgroup dp-hpd-fast:
pass -> INCOMPLETE (fi-kbl-7500u) fdo#102332
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
dmesg-warn -> PASS (fi-byt-j1900) fdo#101705
fdo#102332 https://bugs.freedesktop.org/show_bug.cgi?id=102332
fdo#101705 https://bugs.freedesktop.org/show_bug.cgi?id=101705
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:439s
fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:447s
fi-blb-e6850 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:371s
fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:528s
fi-bwr-2160 total:289 pass:183 dwarn:0 dfail:0 fail:0 skip:106 time:262s
fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:494s
fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:499s
fi-byt-j1900 total:289 pass:254 dwarn:0 dfail:0 fail:0 skip:35 time:491s
fi-byt-n2820 total:289 pass:249 dwarn:1 dfail:0 fail:0 skip:39 time:472s
fi-cfl-s total:289 pass:253 dwarn:4 dfail:0 fail:0 skip:32 time:549s
fi-elk-e7500 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:421s
fi-gdg-551 total:289 pass:178 dwarn:1 dfail:0 fail:1 skip:109 time:248s
fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:574s
fi-hsw-4770 total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:447s
fi-hsw-4770r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:429s
fi-ilk-650 total:289 pass:228 dwarn:0 dfail:0 fail:0 skip:61 time:437s
fi-ivb-3520m total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:494s
fi-ivb-3770 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:462s
fi-kbl-7500u total:70 pass:0 dwarn:0 dfail:0 fail:0 skip:0
fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:570s
fi-kbl-7567u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:478s
fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:584s
fi-pnv-d510 total:289 pass:222 dwarn:1 dfail:0 fail:0 skip:66 time:547s
fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:467s
fi-skl-6700hq total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:644s
fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:526s
fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:505s
fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:460s
fi-snb-2520m total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:563s
fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:0 skip:40 time:419s
5c82a37eff83ab4e60e760fbaf03db5ba0563497 drm-tip: 2017y-10m-23d-18h-06m-28s UTC integration manifest
bff589143fc6 drm/i915/cnl: Get RC6 working.
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6148/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH] drm/i915/cnl: Get RC6 working.
2017-10-23 21:20 [PATCH] drm/i915/cnl: Get RC6 working Rodrigo Vivi
2017-10-23 21:45 ` ✓ Fi.CI.BAT: success for " Patchwork
@ 2017-10-23 22:17 ` James Ausmus
2017-10-23 22:46 ` Rodrigo Vivi
2017-10-23 22:36 ` ✓ Fi.CI.IGT: success for " Patchwork
` (3 subsequent siblings)
5 siblings, 1 reply; 10+ messages in thread
From: James Ausmus @ 2017-10-23 22:17 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx, Nathan Ciobanu, Wayne Boyer
On Mon, Oct 23, 2017 at 02:20:01PM -0700, Rodrigo Vivi wrote:
> On CNL, individual ware rate limit was added to each engine.
s/ware/wake/
>
> GT can only go to RC6 if both Render and Media engines are
> idividually qualified. So we need to set their individual
s/idividually/individually/
> wake rate limit.
>
> +-----------------+---------------+--------------+--------------+
> | | GT RC6 | Render C6 | Media C6 |
> +-----------------+---------------+--------------+--------------+
> | Wake rate limit | 0xA09C[31:16] | 0xA09C[15:0] | 0xA0A0[15:0] |
> +-----------------+---------------+--------------+--------------+
>
> Cc: Nathan Ciobanu <nathan.d.ciobanu@intel.com>
> Cc: Wayne Boyer <wayne.boyer@intel.com>
> Cc: Joe Konno <joe.konno@linux.intel.com>
> Cc: David Weinehall <david.weinehall@linux.intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Matches my read of the spec. With the commit message nitpicking fixed :)
Reviewed-by: James Ausmus <james.ausmus@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 15 +++++++++++----
> 2 files changed, 12 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 68a58cce6ab1..f138eae82bf0 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7905,6 +7905,7 @@ enum {
> #define GEN6_RC1_WAKE_RATE_LIMIT _MMIO(0xA098)
> #define GEN6_RC6_WAKE_RATE_LIMIT _MMIO(0xA09C)
> #define GEN6_RC6pp_WAKE_RATE_LIMIT _MMIO(0xA0A0)
> +#define GEN10_MEDIA_WAKE_RATE_LIMIT _MMIO(0xA0A0)
> #define GEN6_RC_EVALUATION_INTERVAL _MMIO(0xA0A8)
> #define GEN6_RC_IDLE_HYSTERSIS _MMIO(0xA0AC)
> #define GEN6_RC_SLEEP _MMIO(0xA0B0)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 5fdae39b1969..b193eda65e81 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6605,12 +6605,19 @@ static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
> I915_WRITE(GEN6_RC_CONTROL, 0);
>
> /* 2b: Program RC6 thresholds.*/
> -
> - /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
> - if (IS_SKYLAKE(dev_priv))
> + if (INTEL_GEN(dev_priv) >= 10) {
> + I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 54);
> + I915_WRITE(GEN10_MEDIA_WAKE_RATE_LIMIT, 54);
> + } else if (IS_SKYLAKE(dev_priv)) {
> + /*
> + * WaRsDoubleRc6WrlWithCoarsePowerGating:skl Doubling WRL only
> + * when CPG is enabled
> + */
> I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
> - else
> + } else {
> I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
> + }
> +
> I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
> I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
> for_each_engine(engine, dev_priv, id)
> --
> 2.13.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH] drm/i915/cnl: Get RC6 working.
2017-10-23 22:17 ` [PATCH] " James Ausmus
@ 2017-10-23 22:46 ` Rodrigo Vivi
2017-10-24 12:50 ` David Weinehall
0 siblings, 1 reply; 10+ messages in thread
From: Rodrigo Vivi @ 2017-10-23 22:46 UTC (permalink / raw)
To: intel-gfx; +Cc: Wayne Boyer, Nathan Ciobanu, Rodrigo Vivi
On CNL, individual wake rate limit was added to each engine.
GT can only go to RC6 if both Render and Media engines are
individually qualified. So we need to set their individual
wake rate limit.
+-----------------+---------------+--------------+--------------+
| | GT RC6 | Render C6 | Media C6 |
+-----------------+---------------+--------------+--------------+
| Wake rate limit | 0xA09C[31:16] | 0xA09C[15:0] | 0xA0A0[15:0] |
+-----------------+---------------+--------------+--------------+
v2: - Tune Render and Media wake rate values according to some extra
info I got from HW engineers. Value can be tuned, but for now
these are the recommended values.
- Fix typos pointed by James.
Cc: Nathan Ciobanu <nathan.d.ciobanu@intel.com>
Cc: Wayne Boyer <wayne.boyer@intel.com>
Cc: Joe Konno <joe.konno@linux.intel.com>
Cc: David Weinehall <david.weinehall@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: James Ausmus <james.ausmus@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 15 +++++++++++----
2 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 68a58cce6ab1..f138eae82bf0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7905,6 +7905,7 @@ enum {
#define GEN6_RC1_WAKE_RATE_LIMIT _MMIO(0xA098)
#define GEN6_RC6_WAKE_RATE_LIMIT _MMIO(0xA09C)
#define GEN6_RC6pp_WAKE_RATE_LIMIT _MMIO(0xA0A0)
+#define GEN10_MEDIA_WAKE_RATE_LIMIT _MMIO(0xA0A0)
#define GEN6_RC_EVALUATION_INTERVAL _MMIO(0xA0A8)
#define GEN6_RC_IDLE_HYSTERSIS _MMIO(0xA0AC)
#define GEN6_RC_SLEEP _MMIO(0xA0B0)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5fdae39b1969..742d5455b201 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6605,12 +6605,19 @@ static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
I915_WRITE(GEN6_RC_CONTROL, 0);
/* 2b: Program RC6 thresholds.*/
-
- /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
- if (IS_SKYLAKE(dev_priv))
+ if (INTEL_GEN(dev_priv) >= 10) {
+ I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
+ I915_WRITE(GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
+ } else if (IS_SKYLAKE(dev_priv)) {
+ /*
+ * WaRsDoubleRc6WrlWithCoarsePowerGating:skl Doubling WRL only
+ * when CPG is enabled
+ */
I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
- else
+ } else {
I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
+ }
+
I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
for_each_engine(engine, dev_priv, id)
--
2.13.5
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH] drm/i915/cnl: Get RC6 working.
2017-10-23 22:46 ` Rodrigo Vivi
@ 2017-10-24 12:50 ` David Weinehall
2017-10-24 17:24 ` Rodrigo Vivi
0 siblings, 1 reply; 10+ messages in thread
From: David Weinehall @ 2017-10-24 12:50 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx, Nathan Ciobanu, Wayne Boyer
On Mon, Oct 23, 2017 at 03:46:12PM -0700, Rodrigo Vivi wrote:
> On CNL, individual wake rate limit was added to each engine.
>
> GT can only go to RC6 if both Render and Media engines are
> individually qualified. So we need to set their individual
> wake rate limit.
>
> +-----------------+---------------+--------------+--------------+
> | | GT RC6 | Render C6 | Media C6 |
> +-----------------+---------------+--------------+--------------+
> | Wake rate limit | 0xA09C[31:16] | 0xA09C[15:0] | 0xA0A0[15:0] |
> +-----------------+---------------+--------------+--------------+
>
> v2: - Tune Render and Media wake rate values according to some extra
> info I got from HW engineers. Value can be tuned, but for now
> these are the recommended values.
> - Fix typos pointed by James.
>
> Cc: Nathan Ciobanu <nathan.d.ciobanu@intel.com>
> Cc: Wayne Boyer <wayne.boyer@intel.com>
> Cc: Joe Konno <joe.konno@linux.intel.com>
> Cc: David Weinehall <david.weinehall@linux.intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Reviewed-by: James Ausmus <james.ausmus@intel.com>
I've verified that RC6 works with your patch applied.
Minor comments below, but nothing major. Great work!
Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 15 +++++++++++----
> 2 files changed, 12 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 68a58cce6ab1..f138eae82bf0 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7905,6 +7905,7 @@ enum {
> #define GEN6_RC1_WAKE_RATE_LIMIT _MMIO(0xA098)
> #define GEN6_RC6_WAKE_RATE_LIMIT _MMIO(0xA09C)
> #define GEN6_RC6pp_WAKE_RATE_LIMIT _MMIO(0xA0A0)
> +#define GEN10_MEDIA_WAKE_RATE_LIMIT _MMIO(0xA0A0)
> #define GEN6_RC_EVALUATION_INTERVAL _MMIO(0xA0A8)
> #define GEN6_RC_IDLE_HYSTERSIS _MMIO(0xA0AC)
> #define GEN6_RC_SLEEP _MMIO(0xA0B0)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 5fdae39b1969..742d5455b201 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6605,12 +6605,19 @@ static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
> I915_WRITE(GEN6_RC_CONTROL, 0);
>
> /* 2b: Program RC6 thresholds.*/
> -
> - /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
> - if (IS_SKYLAKE(dev_priv))
> + if (INTEL_GEN(dev_priv) >= 10) {
> + I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
> + I915_WRITE(GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
> + } else if (IS_SKYLAKE(dev_priv)) {
How about:
} else if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv)) {
I realise that this isn't code you're introducing, but fixing it at the
same time might make sense. We have a few other cases elsewhere with
where we apply Coarse PG even though (at least according to that
WA-test) we only need it on some Skylakes.
> + /*
> + * WaRsDoubleRc6WrlWithCoarsePowerGating:skl Doubling WRL only
> + * when CPG is enabled
> + */
> I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
> - else
> + } else {
> I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
> + }
> +
> I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
> I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
> for_each_engine(engine, dev_priv, id)
> --
> 2.13.5
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH] drm/i915/cnl: Get RC6 working.
2017-10-24 12:50 ` David Weinehall
@ 2017-10-24 17:24 ` Rodrigo Vivi
0 siblings, 0 replies; 10+ messages in thread
From: Rodrigo Vivi @ 2017-10-24 17:24 UTC (permalink / raw)
To: intel-gfx, Nathan Ciobanu, Wayne Boyer, Joe Konno
On Tue, Oct 24, 2017 at 12:50:13PM +0000, David Weinehall wrote:
> On Mon, Oct 23, 2017 at 03:46:12PM -0700, Rodrigo Vivi wrote:
> > On CNL, individual wake rate limit was added to each engine.
> >
> > GT can only go to RC6 if both Render and Media engines are
> > individually qualified. So we need to set their individual
> > wake rate limit.
> >
> > +-----------------+---------------+--------------+--------------+
> > | | GT RC6 | Render C6 | Media C6 |
> > +-----------------+---------------+--------------+--------------+
> > | Wake rate limit | 0xA09C[31:16] | 0xA09C[15:0] | 0xA0A0[15:0] |
> > +-----------------+---------------+--------------+--------------+
> >
> > v2: - Tune Render and Media wake rate values according to some extra
> > info I got from HW engineers. Value can be tuned, but for now
> > these are the recommended values.
> > - Fix typos pointed by James.
> >
> > Cc: Nathan Ciobanu <nathan.d.ciobanu@intel.com>
> > Cc: Wayne Boyer <wayne.boyer@intel.com>
> > Cc: Joe Konno <joe.konno@linux.intel.com>
> > Cc: David Weinehall <david.weinehall@linux.intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Reviewed-by: James Ausmus <james.ausmus@intel.com>
>
> I've verified that RC6 works with your patch applied.
> Minor comments below, but nothing major. Great work!
>
>
> Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
thanks. merged to dinq.
>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > drivers/gpu/drm/i915/intel_pm.c | 15 +++++++++++----
> > 2 files changed, 12 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 68a58cce6ab1..f138eae82bf0 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7905,6 +7905,7 @@ enum {
> > #define GEN6_RC1_WAKE_RATE_LIMIT _MMIO(0xA098)
> > #define GEN6_RC6_WAKE_RATE_LIMIT _MMIO(0xA09C)
> > #define GEN6_RC6pp_WAKE_RATE_LIMIT _MMIO(0xA0A0)
> > +#define GEN10_MEDIA_WAKE_RATE_LIMIT _MMIO(0xA0A0)
> > #define GEN6_RC_EVALUATION_INTERVAL _MMIO(0xA0A8)
> > #define GEN6_RC_IDLE_HYSTERSIS _MMIO(0xA0AC)
> > #define GEN6_RC_SLEEP _MMIO(0xA0B0)
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 5fdae39b1969..742d5455b201 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -6605,12 +6605,19 @@ static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
> > I915_WRITE(GEN6_RC_CONTROL, 0);
> >
> > /* 2b: Program RC6 thresholds.*/
> > -
> > - /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
> > - if (IS_SKYLAKE(dev_priv))
> > + if (INTEL_GEN(dev_priv) >= 10) {
> > + I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
> > + I915_WRITE(GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
> > + } else if (IS_SKYLAKE(dev_priv)) {
>
> How about:
>
> } else if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv)) {
I believe if IS_SKYLAKE(dev_priv) && *!* NEEDS_WaRsDisableCoarsePowerGating
since by name it seems WaRsDoubleRc6WrlWithCoarsePowerGating
is only needed with coarsepowergating on and the other one is disable
course power gating. right?
>
> I realise that this isn't code you're introducing, but fixing it at the
> same time might make sense. We have a few other cases elsewhere with
> where we apply Coarse PG even though (at least according to that
> WA-test) we only need it on some Skylakes.
Since this would change the behaviour of the wa on few SKL skus
I believe it deserves a different patch.
Also on that patch we would need to check if we need to extend this
Wa to other gen9 platforms. I'd say we probably need this on kbl and cfl :/
Thanks,
Rodrigo.
>
> > + /*
> > + * WaRsDoubleRc6WrlWithCoarsePowerGating:skl Doubling WRL only
> > + * when CPG is enabled
> > + */
> > I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
> > - else
> > + } else {
> > I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
> > + }
> > +
> > I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
> > I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
> > for_each_engine(engine, dev_priv, id)
> > --
> > 2.13.5
> >
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^ permalink raw reply [flat|nested] 10+ messages in thread
* ✓ Fi.CI.IGT: success for drm/i915/cnl: Get RC6 working.
2017-10-23 21:20 [PATCH] drm/i915/cnl: Get RC6 working Rodrigo Vivi
2017-10-23 21:45 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-10-23 22:17 ` [PATCH] " James Ausmus
@ 2017-10-23 22:36 ` Patchwork
2017-10-23 23:08 ` ✗ Fi.CI.BAT: failure for drm/i915/cnl: Get RC6 working. (rev2) Patchwork
` (2 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2017-10-23 22:36 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/cnl: Get RC6 working.
URL : https://patchwork.freedesktop.org/series/32491/
State : success
== Summary ==
Test drv_module_reload:
Subgroup basic-no-display:
pass -> DMESG-WARN (shard-hsw) fdo#102707 +1
Test perf:
Subgroup polling:
fail -> PASS (shard-hsw) fdo#102252
Test kms_busy:
Subgroup extended-modeset-hang-oldfb-with-reset-render-A:
dmesg-warn -> PASS (shard-hsw) fdo#102249
fdo#102707 https://bugs.freedesktop.org/show_bug.cgi?id=102707
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#102249 https://bugs.freedesktop.org/show_bug.cgi?id=102249
shard-hsw total:2540 pass:1433 dwarn:2 dfail:0 fail:8 skip:1097 time:9206s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6148/shards.html
_______________________________________________
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^ permalink raw reply [flat|nested] 10+ messages in thread* ✗ Fi.CI.BAT: failure for drm/i915/cnl: Get RC6 working. (rev2)
2017-10-23 21:20 [PATCH] drm/i915/cnl: Get RC6 working Rodrigo Vivi
` (2 preceding siblings ...)
2017-10-23 22:36 ` ✓ Fi.CI.IGT: success for " Patchwork
@ 2017-10-23 23:08 ` Patchwork
2017-10-23 23:30 ` ✓ Fi.CI.BAT: success " Patchwork
2017-10-24 0:20 ` ✓ Fi.CI.IGT: " Patchwork
5 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2017-10-23 23:08 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/cnl: Get RC6 working. (rev2)
URL : https://patchwork.freedesktop.org/series/32491/
State : failure
== Summary ==
Series 32491v2 drm/i915/cnl: Get RC6 working.
https://patchwork.freedesktop.org/api/1.0/series/32491/revisions/2/mbox/
Test gem_exec_reloc:
Subgroup basic-gtt-cpu-active:
pass -> FAIL (fi-gdg-551) fdo#102582 +2
Subgroup basic-write-cpu-active:
pass -> FAIL (fi-gdg-551)
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
pass -> SKIP (fi-hsw-4770r)
Subgroup suspend-read-crc-pipe-c:
pass -> INCOMPLETE (fi-skl-6700hq)
fdo#102582 https://bugs.freedesktop.org/show_bug.cgi?id=102582
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:442s
fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:451s
fi-blb-e6850 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:371s
fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:517s
fi-bwr-2160 total:289 pass:183 dwarn:0 dfail:0 fail:0 skip:106 time:263s
fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:497s
fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:500s
fi-byt-j1900 total:289 pass:253 dwarn:1 dfail:0 fail:0 skip:35 time:495s
fi-byt-n2820 total:289 pass:249 dwarn:1 dfail:0 fail:0 skip:39 time:476s
fi-cfl-s total:289 pass:253 dwarn:4 dfail:0 fail:0 skip:32 time:561s
fi-elk-e7500 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:418s
fi-gdg-551 total:289 pass:174 dwarn:1 dfail:0 fail:5 skip:109 time:249s
fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:580s
fi-hsw-4770 total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:446s
fi-hsw-4770r total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:409s
fi-ilk-650 total:289 pass:228 dwarn:0 dfail:0 fail:0 skip:61 time:429s
fi-ivb-3520m total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:490s
fi-ivb-3770 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:459s
fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:492s
fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:569s
fi-kbl-7567u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:477s
fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:584s
fi-pnv-d510 total:289 pass:222 dwarn:1 dfail:0 fail:0 skip:66 time:537s
fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:452s
fi-skl-6700hq total:247 pass:222 dwarn:0 dfail:0 fail:0 skip:24
fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:517s
fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:500s
fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:456s
fi-snb-2520m total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:561s
fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:0 skip:40 time:417s
5c82a37eff83ab4e60e760fbaf03db5ba0563497 drm-tip: 2017y-10m-23d-18h-06m-28s UTC integration manifest
eca827093a8a drm/i915/cnl: Get RC6 working.
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6150/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread* ✓ Fi.CI.BAT: success for drm/i915/cnl: Get RC6 working. (rev2)
2017-10-23 21:20 [PATCH] drm/i915/cnl: Get RC6 working Rodrigo Vivi
` (3 preceding siblings ...)
2017-10-23 23:08 ` ✗ Fi.CI.BAT: failure for drm/i915/cnl: Get RC6 working. (rev2) Patchwork
@ 2017-10-23 23:30 ` Patchwork
2017-10-24 0:20 ` ✓ Fi.CI.IGT: " Patchwork
5 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2017-10-23 23:30 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/cnl: Get RC6 working. (rev2)
URL : https://patchwork.freedesktop.org/series/32491/
State : success
== Summary ==
Series 32491v2 drm/i915/cnl: Get RC6 working.
https://patchwork.freedesktop.org/api/1.0/series/32491/revisions/2/mbox/
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:441s
fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:450s
fi-blb-e6850 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:371s
fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:522s
fi-bwr-2160 total:289 pass:183 dwarn:0 dfail:0 fail:0 skip:106 time:266s
fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:502s
fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:506s
fi-byt-j1900 total:289 pass:253 dwarn:1 dfail:0 fail:0 skip:35 time:493s
fi-byt-n2820 total:289 pass:249 dwarn:1 dfail:0 fail:0 skip:39 time:480s
fi-cfl-s total:289 pass:253 dwarn:4 dfail:0 fail:0 skip:32 time:559s
fi-elk-e7500 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:412s
fi-gdg-551 total:289 pass:178 dwarn:1 dfail:0 fail:1 skip:109 time:248s
fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:575s
fi-hsw-4770 total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:451s
fi-hsw-4770r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:433s
fi-ilk-650 total:289 pass:228 dwarn:0 dfail:0 fail:0 skip:61 time:431s
fi-ivb-3520m total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:493s
fi-ivb-3770 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:455s
fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:494s
fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:571s
fi-kbl-7567u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:477s
fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:579s
fi-pnv-d510 total:289 pass:222 dwarn:1 dfail:0 fail:0 skip:66 time:552s
fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:461s
fi-skl-6700hq total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:637s
fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:517s
fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:503s
fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:455s
fi-snb-2520m total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:565s
fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:0 skip:40 time:416s
5c82a37eff83ab4e60e760fbaf03db5ba0563497 drm-tip: 2017y-10m-23d-18h-06m-28s UTC integration manifest
f4e4165a1218 drm/i915/cnl: Get RC6 working.
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6151/
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread* ✓ Fi.CI.IGT: success for drm/i915/cnl: Get RC6 working. (rev2)
2017-10-23 21:20 [PATCH] drm/i915/cnl: Get RC6 working Rodrigo Vivi
` (4 preceding siblings ...)
2017-10-23 23:30 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2017-10-24 0:20 ` Patchwork
5 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2017-10-24 0:20 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/cnl: Get RC6 working. (rev2)
URL : https://patchwork.freedesktop.org/series/32491/
State : success
== Summary ==
Test drv_module_reload:
Subgroup basic-reload-inject:
dmesg-warn -> PASS (shard-hsw) fdo#102707 +1
Test perf:
Subgroup polling:
fail -> PASS (shard-hsw) fdo#102252
Test kms_busy:
Subgroup extended-modeset-hang-oldfb-with-reset-render-A:
dmesg-warn -> PASS (shard-hsw) fdo#102249
fdo#102707 https://bugs.freedesktop.org/show_bug.cgi?id=102707
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#102249 https://bugs.freedesktop.org/show_bug.cgi?id=102249
shard-hsw total:2540 pass:1433 dwarn:2 dfail:0 fail:8 skip:1097 time:9225s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6151/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2017-10-24 17:24 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz follow: Atom feed
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2017-10-23 21:20 [PATCH] drm/i915/cnl: Get RC6 working Rodrigo Vivi
2017-10-23 21:45 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-10-23 22:17 ` [PATCH] " James Ausmus
2017-10-23 22:46 ` Rodrigo Vivi
2017-10-24 12:50 ` David Weinehall
2017-10-24 17:24 ` Rodrigo Vivi
2017-10-23 22:36 ` ✓ Fi.CI.IGT: success for " Patchwork
2017-10-23 23:08 ` ✗ Fi.CI.BAT: failure for drm/i915/cnl: Get RC6 working. (rev2) Patchwork
2017-10-23 23:30 ` ✓ Fi.CI.BAT: success " Patchwork
2017-10-24 0:20 ` ✓ Fi.CI.IGT: " Patchwork
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